Abstract: In part, the invention relates to an optical coherence tomography system that includes one or more phased-locked loop circuits. In one embodiment, the phased-locked loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator wherein the phased-locked loop circuit is configured to generate a sample clock. The optical coherence tomography system can include an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. In one embodiment, the phased-locked loop circuit is configured to lock on a first signal in less than or equal to about 1 microseconds.

Abstract: A variable frequency synthesizer and method of outputting the variable frequency is disclosed. The synthesizer comprises a first reference frequency, a direct digital synthesizer (DDS) receiving the first reference frequency and outputting a tuned frequency, a variable frequency comb generator receiving the tuned frequency and outputting a variable frequency comb comprised of a plurality of comb lines, a mixer receiving the variable frequency comb and a signal from an oscillator and outputting an intermediate frequency, a phase lock loop (PLL) receiving a second reference frequency and the intermediate frequency and outputting a phase lock signal, and the oscillator receiving the phase lock signal and outputting a variable synthesized frequency.

Abstract: A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.

Abstract: A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.

Abstract: This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.

Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: A method and apparatus for measuring the duration of a transient signal with high precision.

Abstract: According to embodiments, dual path loop filter circuits are described which have, for example, a single charge pump. The current flow in the DPLF circuit is architected to source, during an injection time period, a first current to the loop filter, sink, also during the injection time period, a second current from the loop filter, wherein the first current has a magnitude of ?*I and the second current has a magnitude of ?*I, and sink, during a linearization time period, a third current from the loop filter, wherein the third current has a magnitude of (???)*I.

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract: A fractional rate LC VCO and compensating divider circuit to avoid bit-rate interference includes an LC PLL having an input for receiving a reference clock signal, an N-stage ring VCO with rotating injection having an input coupled to an output of the LC PLL and an output for providing an output clock signal, a first divider circuit having an input coupled to an output of the N-stage ring VCO and an output coupled to the LC PLL, a second divider circuit having an input coupled to the output of the LC PLL, and an M-stage reference ring PLL having an input coupled to an output of the second divider and an output coupled to the N-stage ring VCO.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: This invention describes a method by which a low cost low phase noise Phase Locked Loop or Phase Locked Loop based. Frequency Synthesizer can be realized. The new method, called a Translational Phase Lock Loop or TPLL, allows the conversion of a traditional voltage controlled oscillator or VCO signal so that the phase noise of the VCO signal is substantially identical to the noise that the loop is aimed to correct via comparison to a low noise reference oscillator. It overcomes additional problems associated with traditional and prior art phase lock loops in terms of unwanted spurious signals, complexity, and cost.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: A spread spectrum clock generator which includes a pulse train generator circuit and a modulating circuit configured to produce a modulating signal relating to a time derivative of an output of the pulse train generator circuit. In one embodiment the modulating circuit includes a active differentiator circuit and in another embodiment the modulating circuit includes a passive differentiator circuit. A modulator is included which is configured to produce a spread spectrum clock output which is frequency modulated by the modulating signal.

Abstract: A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.

Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.

Abstract: The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for.

Abstract: In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are alternating clock periods. A delta value based on the phase difference is determined. The method then adjusts a division value used by a divider to generate the feedback clock during the even cycle based on the delta value where the delta value is of a first polarity. Also, the method adjusts the division value used by the divider to generate the feedback clock during the odd cycle based on the delta value where the delta value is of a second polarity.

Abstract: A PLL circuit according to the present invention includes a VCO that outputs an VCO signal having a frequency according to an input voltage, a loop filter that feeds a voltage according to an input current to the VCO, a phase comparator that outputs a phase difference pulse having a width according to a phase difference between a first input signal and a second input signal, a charge pump circuit that receives the phase difference pulse, and inputs the current to the loop filter, and a phase-difference-pulse stop unit that stops the input of the phase difference pulse to the charge pump circuit in a non-input state in which an REF signal (reference frequency signal) is not input. The first input signal is the REF signal itself or a signal obtained by dividing the frequency of the REF signal, and the second input signal is the VCO signal itself or a signal obtained by dividing the frequency of the VCO signal.

Abstract: A delay locked loop includes a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal and a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal.

Abstract: A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.

Abstract: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

Abstract: Control circuitry and adjustable clock signal generation circuitry is provided to control the signal transmission rate for electronic devices and systems of electronic devices. The control circuitry may receive status signals indicating current clock rates of a signal transmitting and receiving circuit as well as current processing capacity from the signal receiving circuit. The control circuitry may then generate control signals which control adjustable clock signal generation circuitry. The adjustable clock signal generation circuitry may be used to adjust the rate of generated clock signals for the signal transmitting and receiving circuits which can increase or decrease the signal transmission rate between those circuits.

Abstract: This disclosure describes methods and techniques using Digital Phase Lock Loops (DPLLs) within a source chip to automatically phase align a plurality of clock signals at a plurality of clock pins on a plurality of target chips of varying distances and corresponding delays from the source chip by using each transmitted clock signal's reflected signal as a tuning reference.

Abstract: An integrated circuit with at least two LC-based phase-locked loop circuits and a high-speed serial interface circuit having multiple channels is provided. Each phase-locked loop circuit may include an oscillator having a varactor and multiple inductors. The oscillator may be configured to generate signals at different frequency ranges as determined by the inductors and the varactor. The LC-based phase-locked loop circuits may be produced such that all frequency ranges together provide the continuous coverage of an octave, thereby enabling the phase-locked loop circuits to generate a clock signal with high quality factors and desirable phase noise and jitter performance at an arbitrary frequency. Since the channels of the high-speed serial interface circuit may receive a clock signal having an arbitrary frequency, the high-speed serial interface circuit may be configured to support any communications protocol.

Abstract: A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Abstract: A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO.

Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.

Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.

Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.

Abstract: Systems and methods for Phase-Locked Loop (PLL) based frequency synthesizer comprising a dynamic fraction divider in a feedback loop. The dynamic fraction divider employs a dynamic divide ratio that dynamically changes with the jitters and noise spurs contained in an input signal to the PLL, and generates a feedback signal used to adjust the PLL output frequency. The dynamic divide ratio may be determined by comparing the phases of the PLL output signal and the input signal.

Abstract: The present invention discloses a noise filtering fractional-n frequency synthesizer and an operating method thereof. The noise filtering fractional-n frequency synthesizer comprises a filter, a frequency calibration loop, a phase calibration loop and a digitally controlled delay line. The filter receives a first frequency division signal and generates a filtered signal. The frequency calibration loop is coupled to the filter and generates a first control signal. The phase calibration loop is coupled to the filter and the frequency calibration loop, and generates a second control signal. The digitally controlled delay line is coupled to the phase calibration loop and receives the second control signal. Thus, quantization noise of the fractional-n frequency synthesizer can be reduced, and phase noise of the fractional-n frequency synthesizer can be improved. In addition, the system remains locked after the filter outputs the signal.

Abstract: A circuit for detecting a voltage change is described. The circuit includes a supply insensitive pulse generator that generates a pulse signal. The circuit also includes a time-to-digital converter coupled to the supply insensitive pulse generator. The time-to-digital converter generates a digital signal based on the pulse signal and a voltage. The circuit also includes a controller coupled to the time-to-digital converter that detects a voltage change based on the digital signal.

Abstract: In a phase locked loop, a first frequency divider divides the frequency of an input signal. A low-pass filter receives a frequency-divided signal output from the first frequency divider and having an average phase difference calculated by a calculation unit, cuts off high-frequency components of the received signal, and outputs a resultant signal. A voltage controlled oscillator varies the frequency of a signal to be output based on the signal output from the low-pass filter. A second frequency divider divides the frequency of the signal output from the voltage controlled oscillator. The calculation unit calculates a phase difference between signals individually output from the first frequency divider and the second frequency divider for each phase in one cycle of the signal output from the first frequency divider, and calculates an average phase difference based on the calculated phase differences.

Abstract: Apparatus and methods for phase-locked loops (PLLs) are provided. In certain implementations, a PLL includes a voltage controlled oscillator (VCO) including first and second frequency control circuits, which are coupled to first and second frequency control inputs, respectively. Additionally, the PLL can further include a loop filter, a high frequency pole circuit, and a low frequency pole circuit. The high frequency pole circuit can be electrically connected between the loop filter's output and the VCO's first frequency control input, and the low frequency pole circuit can be electrically connected between the loop filter's output and the VCO's second frequency control input.

Abstract: A phase locked loop including a flying-adder divider circuit configured to receive phases of a periodic signal from a frequency generator and output a feedback signal to a phase detector, and a method of generating a periodic signal using such a flying-adder circuit, are disclosed. The flying-adder divider circuit generally includes a flying-adder and one or two divide-by-N dividers. The flying-adder receives K phases of the periodic signal, where K is an integer of at least 2, and generates a divided periodic signal from the K phases. The phase locked loop may include flying-adder divider circuits inside and/or outside the loop.

Abstract: A clock data recovery circuit includes a phase detector circuit, a filter circuit, a parts per million (PPM) detector circuit, a PPM decoder circuit, a summation circuit, and a phase interpolator circuit. The phase detector circuit generates a phase error signal based on a periodic signal and a data signal. The filter circuit generates a filtered signal based on the phase error signal. The PPM detector circuit and the PPM decoder circuit generate control signals based on the filtered signal. The phase interpolator circuit generates the periodic signal. The clock data recovery circuit adjusts a phase of the periodic signal based on the filtered signal and the control signals in response to variations in a data rate of the data signal using spread-spectrum clocking in order to track changes in the data rate of the data signal.

Abstract: A bursty phase detector comprises upper and lower branches. The upper branch includes a voltage-controlled oscillator (VCO) providing a VCO phase; a phase detector with a first input for receiving a data stream and a second input coupled to the output of the VCO, the phase detector providing a phase error; a sample selector with a first input for receiving a sum of the VCO phase and the phase error, and a second input coupled to receive the data stream, the sample selector providing a data stream sample; a signal stream detector with a first input for receiving the sum of the VCO phase and the phase error, and a second input coupled to the output of the sample selector, the signal stream detector generating a data stream phase and a data stream detect signal. The lower branch includes a delay component with an input for receiving the data stream.

Abstract: In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.

Abstract: A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.

Abstract: Assuring acquisition of symbol timing in a full-duplex data transceiver under inter-symbol interference conditions. One embodiment includes a transmitter comprising a first local clock having a first free running frequency, and a receiver comprising a second local clock having a second frequency initially set to a value higher than the first free running frequency. A first type decision-directed timing recovery mechanism is intentionally limited to only decreasing the frequency of the second local clock. A second type decision-directed timing recovery mechanism is not limited to only decreasing the frequency. The receiver receives symbols, decrease the frequency of the second local clock to a third frequency value using the first type decision-directed timing recovery mechanism, disables the first type mechanism after reaching the third frequency, and then phase-lock the second local clock to the optimal phase under MMSE criteria using the second type decision-directed timing recovery mechanism.

Abstract: The ratio of the output frequency of the PLL to the reference frequency is governed by the ratio of the feedback divider to the output divider. For the case of a fixed-point delta-sigma modulator based PLL, the feedback divide factor can only be a non-recurring/terminating rational number in base-2 (binary) system and the output divide ratio is constrained to be an integer. Hence, the range or resolution of the output frequencies that are possible is inherently limited. To solve this problem, an additional gain factor is introduced in the feedback loop. The gain factor is determined by finding an initial gain factor for which the value of the feedback divide ratio can be represented precisely in the binary format. The closest power of two larger than the initial gain factor is used as the denominator to divide the initial gain factor.

Abstract: The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

Abstract: A pulse modulated neural integrator circuit is comprised of discrete analog electronic components and has a plurality of discrete stable states. In some embodiments, the pulse modulated neural integrator circuit is fabricated in whole or in part on an integrated circuit substrate using analog VLSI techniques. A phase locked loop circuit can use the pulse modulated neural integrator circuit in place of some conventional phase locked loop circuits.