Abstract: A digital pulse width modulation (PWM) controller is used for controlling the operating voltage of an electrical load and includes a setting module, a storage module and a control module. The setting module generates control parameters corresponding to different preset load currents and load voltages of the electrical load. The storage module stores the control parameters and the prestored load current and load voltage. The control module is in electronic communication with the storage module, and detects current load voltage and current load current of the electrical load, and compares the current load voltage and load current with the prestored load voltage. Thus, the control module can output the control parameters which are necessary to stabilize the operating voltage of the electrical load, by comparison with stored data.

Abstract: An input circuit comprises a buffer enable signal generating circuit for generating a buffer enable signal having an predetermined enable period in response to an external command, and a buffer circuit for buffering and outputting the external command and an external address signal in response to the buffer enable signal.

Abstract: A buffer circuit includes an amplifier circuit amplifying a difference between an input signal and a reference signal, providing a branch current that varies with a duty cycle of the input signal, and outputting a preliminary output signal on the basis of the amplified difference. The buffer circuit also includes a charge pump circuit charging/discharging a control node in response to the branch current to provide a control signal. The buffer circuit also includes a driver circuit configured to control pull-up strength and pull-down strength for the preliminary output signal based on control signal to thereby correct the duty cycle of the preliminary output signal in relation to a target duty cycle.

Abstract: A PWM circuit comprises: a charge and discharge circuit to receive a initial signal and, according to the initial signal, increase a voltage at an output end of thereof linearly or decrease the voltage; a comparator with a positive input end to receive a control signal and a negative input end connected to the output end of the charge and discharge circuit; a voltage transmission circuit with a first input end to receive the initial signal and a second input end to receive an output of the comparator, the voltage transmission circuit is configured to transmit the initial signal to an output end of the voltage transmission circuit when the output of the comparator is digital 1, and output digital 0 when the output of the comparator is digital 0.

Abstract: A device includes a logic circuit having first, second, and third input ports, a first output port, and a feedback path between the first output port and the third input port. In a first operating state, a logic state change at the first input port triggers a logic state change at the first output port, but a logic state change at the third input port does not trigger a logic state change at the first output port. This allows signals to be routed through the device. In a second operating state, a logic state change of the third input port triggers a logic state change of the first output port. This change is fed back, delayed by a time value, to the third input to maintain an oscillation with at least two edges. The frequency of this oscillation is used to determine a value of a measurement variable.

Abstract: An apparatus comprising a first circuit, a state machine, a compare circuit and a calibration circuit. The first circuit may be configured to generate a slew rate control signal and a calibration signal in response to (i) a plurality of control bits and (ii) an operation signal. The state machine may be configured to generate the operation signal and a plurality of intermediate control signals in response to (i) a compare signal and (ii) clock signal. The compare circuit may be configured to generate the compare signal in response to (i) a reference voltage and (ii) a capacitance signal. The calibration circuit may be configured to generate the capacitance signal in response to (i) the calibration signal and (ii) the plurality of intermediate control signals.

Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.

Abstract: A method and apparatus for duty-cycle correction with reduced current consumption have been described.

Abstract: Quadrature clocking schemes are widely used in modern communications systems, but often suffer from phase imbalance. Conventional solutions that attempt to address this phase imbalance, however, are generally large and use a substantial amount of power. Here, however, a correction circuit is provided that can locally correct for phase imbalance without the need for bulky and high power consuming circuitry.

Abstract: A method for controlling voltage crossing a power switch of a switched-mode power converter is disclosed. The method comprises the steps of: controlling a switch frequency of a power switch of a switched-mode power converter to a first frequency as activating the switched-mode power converter; and changing the switch frequency of the power switch to a second frequency after a specific amount of time; wherein the first frequency is lower than the second frequency.

Abstract: In a transmission device for differential communication, a first cathode-side element part is coupled between a first communication line and a cathode-side power supply line, a second cathode-side element part is coupled between a second communication line and the cathode-side power supply line, a first anode-side element part is coupled between the first communication line and an anode-side power supply line, and a second anode-side element part is coupled between the second communication line and the anode-side power supply line. A driving portion drives the element parts based on transmission data input from an outside. A target potential generating portion generates target potentials of the element parts based on potentials of the first communication line and the second communication line.

Abstract: An integrated circuit device includes a first rectangular wave signal generation section that outputs a first rectangular wave signal when an amplitude of an oscillation signal inputted is greater than a first amplitude, and a second rectangular wave signal generation section that outputs a second rectangular wave signal when the amplitude of the oscillation signal is greater than a second amplitude that is greater than the first amplitude, and that controls the power supply voltage of an oscillation circuit by the first and second rectangular wave signals so as to maintain an appropriate potential difference with respect to a stop voltage against changes in the oscillation stop voltage associated with changes in a temperature condition.

Abstract: There is provided a modulation profile generator and spread spectrum clock generator including the modulation profile generator. The modulation profile generator includes an input signal generator that generates an input signal; a function calculator that outputs a function calculation result in the form of a square root graph by using the input signal as an input of a function; and a profile generator that generates a non-linear modulation profile based on the function calculation result. As a result, it is possible to effectively reduce electromagnetic interference.

Abstract: There is disclosed a method and apparatus for generating, in an envelope tracking modulator of a mobile radio transmission apparatus, a pulse width modulated, PWM, signal representing a time-varying signal, the method comprising, for each time cycle: a) generating a rising ramp from a first voltage level to a second voltage level; b) generating a falling ramp from the second voltage level to the first voltage level; c) detecting a rising slope of the time-varying signal crossing the falling ramp and responsive thereto if the PWM signal is at the first voltage level, transitioning the PWM signal to the second voltage signal; d) detecting a falling slope of the time-varying signal crossing the rising ramp, and responsive thereto if the PWM signal is at the second voltage level, transitioning the PWM signal to the first voltage signal.

Abstract: A modulator using a polynomial interpolator is described herein. In a simple circuit implementation of the modulator, coefficients of a representative polynomial are generated with interpolation filters in the polynomial interpolator. Crossing points may be identified for each sampling period by incorporating a virtual carrier waveform with the representative polynomial to generate a switching output control. Among other applications, the described modulator may be used in a Class-D amplifier. The described implementations may further confer benefits such as micro-power low voltage operation, low sampling rate, and low harmonic distortion.

Abstract: A rising edge or a falling edge is finely adjusted, or a dead time and a period are adjusted with high accuracy. A waveform processing circuit includes: an integration circuit 11 receiving a rectangular or substantially-rectangular pulse and outputting a gradually increasing or decreasing signal obtained by integrating the pulse signal; a reference signal output circuit 12 outputting a constant value or a varying value as a reference signal; and a comparison circuit 13 comparing the output of the integration circuit with the output of the reference signal output circuit and outputting a pulse rising or falling at a timing when the difference between the outputs varies.

Abstract: A method is provided for controlling an actuator that can be switched into an on state and an off state by means of pulse duration modulation, as well as to a control system. The inventive method includes, but is not limited to defining a standard pulse repetition period for the square wave signal for a range of a nominal pulse-duty factor, and increasing the pulse repetition period of the square wave signal referred to the standard pulse repetition period if a nominal pulse-duty factor falls short of a first lower threshold value and/or if a nominal pulse-duty factor exceeds a first upper threshold value.

Abstract: An electronic oscillation signal generation circuit includes an electronic oscillation circuit, a DC voltage source for providing a DC voltage to the electronic oscillation circuit, a switch for electrically connecting the electronic oscillation circuit to ground when the switch is turned on so as to generate an analog oscillation signal after the switch is turned off, a conversion circuit for converting the analog oscillation signal to a digital oscillation signal, a counter for generating a control signal when the digital oscillation signal reaches a predetermined number of periods, a delay unit for generating a delay signal a predetermined time after a falling edge of the digital oscillation signal is triggered, and a pulse signal generation circuit electrically connected to the counter and the delay unit for generating a pulse signal according to the control signal and the delay signal so as to turn on the switch.

Abstract: A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal.

Abstract: This document discusses, among other things, a modulator including a first integrator configured to receive an input signal and a first feedback signal from an output stage, a second integrator configured to receive an output of the first integrator and a second feedback signal, and a comparator configured to be coupled to a regulated supply voltage, to receive an output of the second integrator and a modulation signal, and to provide a pulse width modulated representation of the input signal. The output stage is configured to be coupled to an unregulated supply voltage, and the second feedback signal can include a representation of an output of the comparator configured to reduce artifacts in the pulse width modulated representation of the input signal induced by changes in an amplitude of the unregulated supply voltage.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.

Abstract: A device and a method for implementing pulse width modulation for switching amplifiers (120) is described herein. In one embodiment, the device includes a sampling signal generator (202) to generate a sampling signal (208) and a modulation unit (102) operatively coupled to the sampling signal generator (202). The modulation unit (102) generates differential pulse width modulated waveforms based on the sampling signal (208) and differential input signals (220-1 and 220-2) such that at least one differential pulse width modulated waveform has a duty cycle equivalent to a pre-determined non-zero minimum pulse width at all values of the differential input signals (220-1 and 220-2).

Abstract: The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit comprising circuitry to latch the data signal with the first clock signal to produce a first latched signal, circuitry to latch the data signal with the second clock signal to produce a second latched signal, and circuitry that selects the first latched signal or the second latched signal depending on a transition of the data signal in a previous clock cycle.

Abstract: An active infrared induction instrument powered by a dry battery capable of reducing power consumption through the adjustment of the emitter pulse width. The infrared emitted LED emits infrared signals, which, after being reflected by an object, are received by the infrared photodiode. The infrared signals received the infrared signals received by the infrared photodiode then enter an integrated circuit chip through a comparator. The pulse widths of the infrared emission pulse signals are dynamically adjusted after the width of the pulse series is received by the discrimination chip, thus reducing the emission power consumption to save energy.

Abstract: A duty cycle correction circuit of a semiconductor memory apparatus includes a duty correction unit configured to determine a duty correction range in response to a duty correction range control signal, correct a duty of an inputted clock in response to duty correction codes to fall in the determined duty correction range, and generate a duty corrected clock; a duty detection unit configured to detect a duty of the duty corrected clock and output duty information; and a duty correction code generation unit configured to generate the duty correction codes based on the duty information.

Abstract: A spread-spectrum circuit including an inverter, a current source, a control unit and a shaping circuit is provided. An input terminal of the inverter receives an original clock signal. The current source is coupled to a current transmission terminal of the inverter. The control unit includes a control circuit, and changes the current magnitude of the current source according to the original clock signal to control the charging/discharging speed of an output terminal of the inverter, so that the output terminal outputs a voltage signal. The shaping circuit shapes the voltage signal into a spread-spectrum clock signal.

Abstract: A driving circuit device for driving a load is provided. The driving circuit device includes a control module including a power correction module, and providing a control signal to adjust a current flowing through the load; and a pulse width modulation module being in cooperation with the power correction module to modulate the control signal, and including a voltage providing unit providing a pulse width modulation signal; and a Schmitt trigger circuit.

Abstract: A method, apparatus and system are described for adjusting the frequency of one or more clock signals used by a device. The one or more clock signals are adjusted by a determined amount when a channel quality metric of an RF channel in use by the device indicates a degradation in the reception quality.

Abstract: Integrated circuits with pulse latches are provided. Pulse latches are controlled by clock pulse signals. The clock pulse signals are generated by pulse generators. The pulse generators are controlled by adaptive pulse width control circuitry to provide clock pulse signals with a minimum pulse width and with sufficient margin to tolerate for process, voltage, and temperature variations. The pulse width control circuitry may include a replica pulse generator, a test data generation circuit, a test latch, and a pulse width calibration circuit. The replica pulse generator controls the test latch. The test latch may attempt to latch the test data. The pulse width control circuit may determine if the test latch properly latches the test data with the given pulse width. The pulse width control circuit adjusts the pulse generator dynamically to provide a minimized pulse width.

Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.

Abstract: A duty cycle correction method includes detecting independently a relative delay time of two input differential signals; equating the sum of two relative delay time with the cycle of the input differential signals; and adjusting the two delay time to the same value. A corresponding implementation circuit includes two time delay units; two relative phase detectors connecting simultaneously with each of the two time delay units; a charge pump connecting with the output of each of the two relative phase detectors, with its output connecting to the two time delay units in order to form a loop; and a synthesis output unit connecting with both the time delay units, thereby generating output signals. The adjusting range of duty cycle becomes much wider. The implementation circuit is absolutely symmetrical, so a duty cycle with high accuracy can be obtain.

Abstract: There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width.

Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

Abstract: A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.

Abstract: A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.

Abstract: A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal.

Abstract: An integrated control circuit according to aspects of the present invention includes a capacitor to develop a first current during a first time duration in response to a charge current and to develop a second voltage during a second time duration in response to a discharge current. A comparator is also included and is coupled to the capacitor to indicate when the voltage on the capacitor reaches the second voltage. A control logic sets a duty ratio of a periodic output signal in response to the time it takes the capacitor to discharge from the first voltage to the second voltage. An oscillator is coupled to provide a timing signal to the control logic. In one aspect, the control logic includes an output that is coupled to the oscillator to change a frequency of the oscillator.

Abstract: Circuits and methods for providing a pulsed clock signal for use with pulsed latch circuits are described. A variable pulse generator is coupled to form a pulsed clock output responsive to a control signal and a clock input signal. A feedback loop is provided with a pulse monitor and a pulse control circuit. Samples of the pulsed clock signal are taken by the pulse monitor and an output is formed in the form of a pattern. The pulse control circuit receives the output of the monitor and determines whether it matches a predetermined pattern. Adjustments are made to the control signal to adaptively adjust the pulsed clock signal. The feedback loop may operate continuously. In alternative embodiments the feedback loop may be powered down. Methods for adaptively controlling a pulsed clock signal are disclosed.

Abstract: Data comprising a pulse signal is divided into predetermined data segments. The number of pulse-signal fluctuations in the data segment is counted. A transmitter transmits the unchanged data to a receiving portion in a case where the number of pulse-signal fluctuations does not exceed a predetermined number. On the other hand, in a case where the number of pulse-signal fluctuations exceeds the predetermined number, the pulse signal is converted so as to be unchanged at the fluctuation of the pulse signal but to be fluctuated when the pulse signal does not fluctuate. Then, the transmitter transmits the converted pulse signal to the receiving portion wherein only the converted pulse signal is converted to the original pulse signal.

Abstract: A pulse width modulation (PWM) frequency converter converts an input PWM signal to an output PWM signal having a different frequency while maintaining a substantially equal duty ratio. The PWM frequency converter samples the input PWM signal for a PWM cycle using a sampling clock. A filter module filters the resulting set of one or more PWM parameters to compensate for noise introduced by potential clock mismatch, clock jitter, ambient variations, and other non-deterministic issues, thereby generating filtered PWM parameters. The sampling employed by the filter module compares a difference between the one or more current PWM parameters and previous (or historical) PWM parameters from an earlier sampled PWM cycle to a predetermined change threshold in determining a filtered set of one or more PWM parameters. The filtered set of one or more PWM parameters then is used to generate one or more corresponding PWM cycles of the output signal.

Abstract: In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.

Abstract: A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold.

Abstract: A temperature sensor performs more precise temperature measurement, even when manufacturing fluctuations are present in semiconductor elements forming a circuit for generating a temperature-dependent current.

Abstract: A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.

Abstract: A pulse width modulation circuit may generate an adjustable output signal that periodically transitions between a first and a second state with an adjustable duty cycle. A first pulse generator circuit may be configured to generate a first pulse signal that periodically transitions at an adjustable delay with respect to a periodic reference signal. A second pulse generator circuit may be configured to generate a second pulse signal that periodically transitions at an adjustable delay with respect to the periodic reference signal. A logic circuit may be configured to generate the adjustable output signal based on both the first and the second pulse signals.

Abstract: A pulse signal generation circuit includes a transfer path configured to receives and transfer a first pulse signal, a pulse adjustment unit configured to adjust a pulse width of the first pulse signal by applying charges to the transfer path in response to a control signal, and a pulse output unit configured to output a second pulse signal of the adjusted pulse width in response to an output of the transfer path.

Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.

Abstract: A timing circuit and corresponding method are provided to generate an output timing signal in dependence on an input timing signal. The timing circuit comprises a plurality of circuit components, each circuit component configured to receive an input dependent on the input timing signal and to generate an output in dependence on that input. Each circuit component performs switching operations by switching its output level in response to a transition of its input level. Each circuit component exhibits a delay in switching its output level, the delay comprising a first delay associated with a first switching of its output level and a second delay associated with a second switching of its output level. The first switching is in an opposite direction to the second switching and the first delay and the second delay exhibit a change in magnitude as each circuit component repeatedly performs its switching operations.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.