Abstract: In an output driver circuit, the signal propagation time of an electrical signal which is to be transmitted between two selected driver stages is ascertained. If the ascertained signal propagation time is at least equal to half the period duration of the signal which is to be transmitted, the signal to be transmitted is delayed between the two selected driver stages such that a given signal edge change appears at the output of the other of the selected driver stages at a different time from other signal edge which follow the one given signal edge change in time, at driver stages which are situated upstream of the other of the selected driver stages. The inventive output driver circuit accordingly has a delay element which can be used to influence the signal propagation time between the selected driver stages.

Abstract: A delay circuit comprises a signal generator and a delay component. The signal generator comprises a terminal for receiving a trigger signal and an output for outputting a signal when receiving a trigger signal with a pre-determined characteristic. The delay mean comprises an input for receiving the signal outputted by the signal generator and an output for generating a signal delayed with a delay referred to the time the delay mean received the signal outputted by the signal generator.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: A circuit's performance may vary based on various factors such as, for example, process, voltage, and/or temperature. In one embodiment, a circuit includes an input terminal which receives an input signal, a delay selection section which delays the input signal by a delay amount selected by a performance variation indicator, an impedance selection section which outputs the delayed input signal as a compensated delayed signal, where the impedance selection section uses a driver impedance amount selected by the performance variation indicator, and an output terminal which outputs the compensated delayed signal. The circuit may also include a ring oscillator, a frequency counter which provides a count value which indicates a number of rising edges of an output of the ring oscillator which occur during a period of a reference frequency, and a decoder which uses the count value to output the performance variation indicator.

Abstract: A system, apparatus and method for delaying a signal, such as a high-speed signal are disclosed. A multi-stage delay cell is described in which the amount of delay applied to a signal depends on which stages are activated within the cell. In various embodiments of the invention, noise caused by transitions between various delay times within the cell is reduced by efficiently managing voltage states on each of the stages.

Abstract: In a circuit in which a signal arrival time with respect to a register is different in accordance with the change of a delay time of the circuit, a mechanism capable of adjusting a clock signal of the register is previously provided to deal with the case in which a set-up time in the register is not satisfied due to an increase of the delay time, and the delay time of the clock signal is changed in response to the change of the delay time of the circuit in respective modes. Thereby, the set-up time of data in the register can be satisfied, and an operation frequency of the circuit can be prevented from lowering.

Abstract: A delay time generation circuit is disclosed that includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of the last stage or a predetermined stage of the flip-flop circuits of the counter circuit. In the delay time generation circuit, a delay time is generated by the use of an output signal of one of the flip-flop circuits precedent to the last stage or the predetermined stage flip-flop circuit of the counter circuit at testing an electronic circuit. This configuration makes it possible to reduce the delay time without using a special high-speed clock.

Abstract: An input circuit (1?) provided with a time delay element (40), which circuit is capable of being tested by a controlled high level or low level connection, and a method for the operation thereof. The delay time of the time-delay element can be modified during operation of the input circuit. In particular, the elapsed delay time is read out prior to the testing of the input circuit and is restored again after testing, so that the test does not increase the effective input delay time for the process signals. In addition or as an alternative, the delay time is set to a minimum value prior to the test to enable rapid testing of the input circuit independent of the set delay time.

Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.

Abstract: A delay adjustor for adjusting the delay time of a signal, the adjustor comprising: a first capacitance unit and a variable capacitance unit serially coupled to the first capacitor wherein the capacitance of the variable capacitance unit is adjusted according to a first control signal and the variable capacitance unit comprises a plurality of second capacitors and at least a first switch coupled to the at least one capacitor of the second capacitors.

Abstract: A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

Abstract: The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.

Abstract: An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group (110) is fed with data outputted from a flip-flop circuit group (106), adjusts a delay of the data so as to synchronize the operation of a data output terminal group (114) with the operation of a logic circuit (100), and outputs the data to the data output terminal group (114). A clock delay adjustment circuit (109) similarly adjusts a delay of a clock outputted from an inverter (105) and outputs the clock to a clock output terminal (113). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit (100) while keeping the phase relationship between an external output clock and external output data.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The capacitor receives the first current as a sinking current or as a sourcing current. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage.

Abstract: A delay circuit comprises: N-stage circuits having a first circit to a N-th circuit connected in cascade, the input signal being input to the first circuit and a transmission signal delayed by a (k-1)-stage (where 2?k?N) circuit is input to a k-th circuit for sequential transmission; a common delay circuit for delaying the transmission signal of each stage commonly; and path control means for controlling a path of an i-th (1?i?N) circuit so that during a predetermined period from an edge timing of a signal input to the i-th circuit to an edge timing of the transmission signal delayed by the common delay circuit through the i-th circuit, the common delay circuit is connected to a signal path, and during the other period, the common delay circuit is disconnected from the signal path, wherein the delayed signal passing through the common delay circuit N times is generated.

Abstract: In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.

Abstract: A semiconductor device can accurately control the timings of various signals used in the semiconductor device using a simple configuration.

Abstract: Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input clock signal and an output clock signal, and has particular utility as the variable delay in a delay-locked loop (DLL). In one embodiment, a coarse unit delay provides a delayed representation of an input clock. The original and delayed versions of the input clock are presented to a phase mixer block, which is controllable to weight its output to a phase between one of the two input clock signals. The output of the phase mixer block is then provided to a controllable variable delay line capable of adding further coarse delay into the processed signal. To assist in boundary switching, multiplexers are provided in the path between the original and delayed versions of the input clock and the phase mixer block, which provides the ability to boundary shift without having to reset the phase mixer.

Abstract: A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

Abstract: A delay control circuit capable of controlling a delay time is disclosed. The delay control circuit includes a delay detecting circuit, a first pulse generator, a counter control circuit and a counter. The delay detecting circuit delays an input signal by a first time in response to an output signal and compares the input signal and the delayed input signal to generate a first signal. The first pulse generator generates a second signal in response to the input signal. The counter control circuit generates a count-up signal and a count-down signal in response to the first signal and the second signal. The counter generates the output signal in response to the count-up signal and the count-down signal to divide the first time by 2n intervals, wherein n is a positive integer.

Abstract: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

Abstract: A technique for operating a delay circuit is disclosed. In one particular exemplary embodiment, the technique may be realized by a delay circuit comprising a plurality of data paths. The delay circuit may receive a signal. The delay circuit may also stagger transmissions of the signal through the plurality of data paths. The delay circuit may additionally generate a plurality of signals based on the staggered transmissions. Each of the plurality of data paths in the delay circuit may comprise at least one of an inverter, a logic gate, a flip-flop, a latch, a register, or a resistor-capacitor (RC) delay element.

Abstract: A delay line including analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: The invention discloses a delay locked loop (DLL) architecture with a time cycle suppressor circuit suitable for use with synchronous integrated circuits containing a clock generator. Utilization of the improved delay locked loop architecture with a time cycle suppressor circuit disclosed herein enables reduction in the lock time of the synchronous circuit.

Abstract: A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a plurality of series-connected delay elements in a measurement delay line. The measurement delay line is coupled to a series of latches that correspond to respective groups of delay elements in the measurement delay line. The delay element to which the pulse has propagated when the next pulse is received causes a corresponding latch to be set. The clock reference signal propagates through a signal generating delay line, which contains a sub-multiple of the number of delay elements in the measurement delay line, starting at a location corresponding to the set latch. The latch may remain set for a large number of periods of the clock reference signal so that it is not necessary for the clock reference signal to propagate through the measurement delay line each cycle.

Abstract: A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal to the flip-flop to have the flip-flop generate the output signal. The judge unit receives the output signal and generates a judge signal, which is enabled when the clock period of the output signal is longer than that of the clock signal.

Abstract: A circuit for generating stable signal edges includes an output driver circuit having a current path for varying a charge on a capacitor in response to an input signal and constant current generation circuitry for maintaining a constant current through the current path of the output driver circuit and varying the charge on the capacitor to produce an output signal with a stable edge.

Abstract: A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.

Abstract: A method and apparatus for managing hysterisis in a delay line. In one embodiment, an integrated circuit includes a delay line. A selection circuit is coupled to an input of the delay line. The selection circuit includes two inputs: a first input coupled to convey a signal such as a data signal or a data strobe signal, while the second input is coupled to convey a dummy clock signal. Control logic is coupled to monitor activity within the delay line. Upon detecting a lack of activity for a predetermined time period, the control logic is configured to cause the selection circuit to allow the dummy clock signal to be conveyed to the input of the delay line.

Abstract: By forming adjacent wiring 4 adjacent to signal wiring 3 and using a control circuit 13 comprising a 2-input NAND 20 circuit or the like to input a signal S4 corresponding to a signal S3 in the signal wiring 3 to the adjacent wiring 4, it is made possible to change the delay of the signal S3 in the signal wiring 3 in several picoseconds, by using crosstalk with the signal S4 in the signal wiring 4.The inventive delay control circuit device can be provided by simply adding adjacent wiring 4 and a control circuit 13 to signal wiring 3. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Abstract: A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.

Abstract: Embodiments of the present invention relate to a circuit that varies the delay time of a clock signal in response to a frequency of the clock signal. The circuit may include a sensor and a delay circuit. The sensor may output a determination of the frequency of the clock signal. The delay time of the delay circuit may be responsive to the determination of a frequency of the clock signal. Accordingly, when the frequency of a clock signal varies, a delay of that clock signal can be varied to accommodate for the change in frequency.

Abstract: A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.

Abstract: A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.

Abstract: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.

Abstract: A delay circuit generates an output signal by delaying an input signal, and includes a ferroelectric capacitor having a first end and a second end, a means for inverting a polarization of the ferroelectric capacitor by producing an electric potential difference between the first end and the second end based on an electric potential of the input signal and a generation means for generating the output signal by delaying the input signal based on a change in an electric potential of the second end caused by the polarization inversion.

Abstract: A method and apparatus for a frequency-based slope-adjustment circuit block are described herein.

Abstract: A delay circuit is constructed by connecting taps TAP0–n for providing with a unit delay time (?) in series on multiple stages. Each tap has the same configuration and an objective signal is inputted to a signal input terminal IN1. The output terminal of a preceding stage tap is connected to a between-stages connecting terminal IN2. An output terminal O is connected to the between-stages connecting terminal of a next stage tap. The signal input terminal and the between-stages connecting terminal are connected to one input terminal of NAND gates 1, 2 and a tap selection signal is inputted to the other input terminal. The output terminal is connected to a NAND gate 3. One of the NAND gates 1, 2 functions as a logical inversion gate corresponding to a tap selection signal so as to enable propagation of the signal. At this time, in the other NAND gate, the output signal is fixed to high level and the NAND gate 3 also functions as a logical inversion gate.

Abstract: A clock delay compensation circuit for an integrated circuit having a first voltage domain and a second voltage domain, has a first delay element that receives a clock signal and generates a first delayed clock signal, and a multiplexer that receives the clock signal and the first delayed clock signal and generates a variable clock signal. The first delayed clock signal is selected when the second voltage domain is at a higher voltage level than the first voltage domain.

Abstract: Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the outputs of the delay paths. First and second gates receive the input pulse train and selectively provide the input pulse train to the first and second delay paths independent of the edge position of the input pulse train. A delay time setup circuit generates a CTRL signal for controlling the first and second gates and the loading of the delay data to the first and second delay path. The CTRL signal causes the gates to selectively switch the input pulse train from one delay path to another while the delay data is selectively loaded in the delay path not receiving the input pulse train.

Abstract: Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.

Abstract: A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.

Abstract: A delay circuit includes a plurality of delay units DI to DN. An input signal IS is input to the delay circuit, and the delay circuit outputs a delay signal. A comparison circuit stores, to a comparison result register, comparison result data of a pulse width time of a pulse of a test input signal IS input to the delay circuit and delay times of delay signals DSM to DSN output from taps PM to PN of the delay circuit. An adjustment circuit adjusts the delay time of the delay signal in the delay circuit. Adjustment data ADT of the delay time is set based on the comparison result data read from the comparison result register. The delay time after adjustment is confirmed by again inputting the test input signal after the delay time has been adjusted, and again reading the comparison result data from the comparison result register.

Abstract: The present invention provides a phase shift circuit that supports multiple frequency ranges. The phase shift circuit receives a plurality of control bits and causes a phase shift in a received signal, the phase shift corresponding to a number of time steps, the number depending on the control bits, and the time step is selected from a plurality of different time steps based on a frequency range associated with the received signal.

Abstract: An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to generate a second intermediate signal by delaying the first intermediate signal by inserting one of a plurality of fixed delays in response to a first control signal. The second delay circuit may be configured to generate the output signal by delaying the second intermediate signal by inserting a programmable delay in response to a second control signal.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: A delay locked loop includes a primary delay line having a plurality of series-connected delay elements, wherein each of the delay elements operates in response to a supply voltage provided on a voltage supply line. When the delay locked loop is configured to operate in response to an input clock signal having a relatively high frequency, the voltage supply line is coupled to receive a first supply voltage. When the delay locked loop is configured to operate in response to an input clock signal having a relatively low frequency, the voltage supply line is coupled to receive a second supply voltage, which is significantly lower than the first supply voltage. When operating in response to the first supply voltage, the delay elements exhibit relatively short delays. Conversely, when operating in response to the second supply voltage, the delay elements exhibit relatively long delays.

Abstract: A first PMOS transistor is connected between a supply terminal of a power supply voltage VCC and a connection node MON. A first NMOS transistor and a second NMOS transistor are connected between the connection node MON and ground. The first PMOS transistor and the first NMOS transistor are driven by an input signal. The second NMOS transistor is driven by a constant current IREF. In cooperation with the first NMOS transistor, the second NMOS transistor discharges the charge across a capacitor C1 connected to the connection node MON. A differential amplifier compares a potential at the connection node MON with a potential depending upon the constant current IREF, and outputs a result of the comparison.