Abstract: An Edge-Aligned Ratio Counter (EARC) that includes at least one processor coupled to at least one counter circuit is provided for determining a ratio between two clock signals by receiving a first and a second value in response to a first clock signal and generating a control signal under control of the loaded value by counting the pulses of the first clock signal and a second clock signal and captures the count of each clock signal in response to the control signal and determining a ratio between a frequency of the first clock signal and a frequency of the second clock signal using the differences of the captured counts taken at two different occurrences of the control signal.

Abstract: A design structure and method. The design structure comprises a selection circuit comprising a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

Abstract: An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched capacitor element being located in a second branch of the bridge circuit. A detector circuit is coupled to the first branch and to the second branch of the bridge circuit. Switching signals of the first switched capacitor element and of the second switched capacitor element are generated on the basis of an input clock signal of the integrated circuit.

Abstract: Phase-locked loop (PLL) fast lock circuit and method using a second frequency controlled feedback loop to complement a primary frequency and phase controlled feedback loop. The second loop may charge a capacitor controlling input voltage to a voltage controlled oscillator (VCO) up and down faster that the primary loop, such as using up and a down charge pumps. In some cases, the second loop uses a frequency detector to detect a difference between a reference and feedback signal frequencies; and in response uses logic to control two pump up and two pump down charge pumps. The frequency detector may be configured to receive a reset signal and a lock signal. The reset signal causes the second loop to send a strong pump up charge to the capacitor without waiting for a difference in the frequencies. The lock signal causes the frequency detector to stops counting the difference in the frequencies.

Abstract: A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal.

Abstract: A method and apparatus for filtering an electromyogram (EMG) signal from a raw signal which includes a contribution from an electrocardiogram (EKG) signal is disclosed. The method includes the steps of estimating an attribute (such as a Fourier transform) of both the EMG contribution to the raw signal and the EKG contribution to the raw signal and, dependent on both frequency spectrums, determining an EMG window in a frequency range and obtaining the EMG signal by passing it through a filter defined by the frequency range. The method is particularly used when monitoring a multi-channel electrical recording from a plurality of electrodes attached to a patient's diaphragm.

Abstract: Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: Frequency discriminator based on a variant of the DFT transform in which the usual twiddle factors are replaced with twiddle factors as for a DFT on a number of points which is the double as the actual number of sample points. The DFT so modified allows half-bin frequency discrimination, with few added computational burden. Two DFT shifted of half bin with respect to the zero frequency provide a linear response of the discrimination and good immunity to noise. The discriminator is particularly useful in FLL for tracking signals in a GPS receiver.

Abstract: In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular

Abstract: An image display system synchronizes the display of images on a plurality of display devices. The system includes a first computer system generating a first signal representing first image data to be displayed on a first display device, a second computer system generating a second signal representing second image data to be displayed on a second display device, and means for synchronizing the first and second image data. The synchronizing means includes a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.

Abstract: An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided.

Abstract: A circuit drives an LED array and controls the brightness of the LED array by regulating the current flowing through the array. The LED array is driven by a pulse-shaped current of which the mean value is regulated with at least one or two of the following types of modulation: frequency modulation, pulse-width modulation, and amplitude modulation.

Abstract: A method and system for monitoring a frequency of a clock signal is disclosed. The method and system comprise dividing a clock signal into a plurality of clock signal components. The method and system further comprise adding a delay to each of the clock signal components and comparing the plurality of signal components with each of the delayed clock signal components to monitor whether the clock signal is within a predetermined frequency range. The method and system includes providing an output signal indicative of a condition of the clock signal based upon the comparing step.

Abstract: A device for non-contacting interrogation, without auxiliary power, of system states of a part that is rotatable relative to a fixed part comprises a coil on the rotatable part and a coil on the fixed part. The coils are mutually coupled, one being fed by a signal generator generating different frequencies, whilst the other coil is supplemented with at least one capacitance to form a resonance circuit. Further impedances can be added by means of switch elements to change a resonance frequency and form an interrogation circuit. By determining a resonance frequency on a signal generator side it is possible to draw conclusions about an impedance on an opposite side and to assign this to a switch element which is closed.

Abstract: The present invention discloses a frequency detecting apparatus for detecting a frequency of an input clock. The frequency detecting apparatus includes: a pulse generator, a digital signal generator, and a decoder. The pulse generator is coupled to the input clock for extracting a period of the input clock to generate a pulse, and the digital signal generator is coupled to the pulse generator for converting the pulse into a plurality of logic values. The digital signal generator includes: a delay module coupled to the pulse, for delaying the pulse to generate a plurality of delayed pulses according to a plurality of delay amounts, respectively; and a sampling module coupled to the delay module for sampling the pulse to generate the logic values according to the delayed pulses, respectively. The decoder is coupled to the digital signal generator for determining the frequency of the input clock according to the logic values.

Abstract: An apparatus for reducing electromagnetic interference is provided. The apparatus includes a receiving module, a first comparing module, and a frequency spreading module. The receiving module receives a first signal with a first frequency and a second signal with a second frequency. The first comparing module is used for comparing the first frequency and the second frequency. The frequency spreading module is operated by a comparing result of the first comparing module. If the first frequency is higher than the second frequency, the frequency spreading module up-spreads the first frequency and down-spreads the second frequency.

Abstract: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: A verification support apparatus verifies an object. The object includes a plurality of clock domains and each clock domain includes a plurality of registers. The verification support apparatus includes an input receiving unit that receives logical circuit description information on the object; a specifying unit that specifies at least two registers in one clock domain that output data to an adjacent clock domain; and a detecting unit that detects, based on the logical circuit description information and specified registers, a re-convergence register in the adjacent clock domain that achieves convergence.

Abstract: A selection circuit and method. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: The present invention discloses a frequency comparator for comparing frequencies of a first signal and a second signal. The frequency comparator includes: a frequency detecting circuit for generating a reference signal according to the first signal and an input voltage; a frequency generator for generating the second signal according to the input voltage; a charge pump circuit for enabling a charging current according to either the reference signal or the second signal to increase an voltage level, and for enabling a discharging current according to the other signal to decrease the voltage level; and a decision logic coupled to the charge pump circuit for indicating a frequency relation between frequencies of the first signal and the second signal according to the voltage level.

Abstract: A frequency comparator comparing frequencies of a first clock signal and a reference clock signal. The frequency comparator includes a phase-frequency detector and a comparison module. The phase-frequency detector receives the first clock signal and the reference clock signal, and outputs an up clock signal and a down clock signal. The pulse-width difference between the up clock signal and the down clock signal corresponds to the phase difference between the first clock signal and the reference clock signal. The comparison module compares the frequencies of the first clock signal and the reference clock signal based on how many times the pulse width of the up clock signal is larger or shorter than that of the down clock signal in a predetermined period.

Abstract: To provide a broadband circuit from which a desired circuit characteristic is stably obtained over a wide frequency band with a small number of circuit devices and which can be easily designed. In the case of the broadband circuit to which a circuit device is connected through a transmission line including a signal transmission conductor, grounding conductor, and dielectric present between these conductors, an LILC 13 having a four-terminal line structure in which a pair of conductors are faced each other, having an impedance lower than that of a conductor connected to any terminal, and using a frequency band of an electromagnetic wave whose wavelength is shorter than a length approximately four times of the length of the circut device as an object frequency band is inserted into the transmission line and used as a low impedance device to the electromagnetic wave of the object frequency band.

Abstract: A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detector and an output controller, which determines whether or not the frequency of the clock signal is higher than a predetermined value. Embodiments of the invention have an increased accuracy, increased efficiency, and a reduced current consumption over conventional art.

Abstract: A method of frequency tracking based on recovered data, for use in an automatic frequency control subsystem at the receiver of a mobile station, is disclosed. The frequency tracking mechanism derives frequency error information from the recovered data to determine the adjustment needed at the mobile station's local voltage controlled oscillator in order to track the frequency of the base station.

Abstract: A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

Abstract: A digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived, for example, from a communications signal. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: An apparatus for generating a stabilized frequency signal is disclosed. The apparatus includes a quantum absorber having first, second, and third energy states. The quantum absorber is irradiated by a first radiation source that generates electromagnetic radiation having a frequency, ?L, that induces transitions between the first and third energy states. The quantum absorber is also irradiated by a second radiation source that generates electromagnetic radiation having a frequency, ?M, that induces transitions between the first and second energy states. A detector that generates a detector signal indicative of the level of radiation leaving the quantum absorber in a frequency range including ?L is used by a number of servo loops. One of the servo loops determines the value of ?L that minimizes or maximizes the detector signal and a second servo loop determines an offset signal that reduces the dependence of ?M on the intensity of the first radiation source.

Abstract: The present invention, generally speaking, provides a digital circuit and method for forming number streams for frequency and/or phase comparison of digital or digitized signals, referred to herein as clock signals, where typically one of the clock signals is a known clock signal and another of the clock signal is an unknown clock signal. The unknown clock signal may be derived from a communications signal, for example. The rate of the unknown clock signal may exceed the rate of the known clock signal. In an exemplary embodiment, an “alias” value (e.g., an integer 1, 2, 3, etc.) is applied to the circuit as an indication of the expected frequency range of the unknown clock signal. The number stream is formed accordingly.

Abstract: The method and the device thereof for dynamically calibrating a frequency is provided. The method includes steps of: (a) providing a first system frequency; (b) obtaining a first parameter of timer counting number; (c) providing a second system frequency; (d) obtaining a second parameter of timer counting number if there is a frequency drift between said first system frequency and said second system frequency; (e) obtaining a third parameter of timer interrupt interval by comparing said first parameter of timer counting number with said second parameter of timer counting number; and (f) calibrating a frequency output according to said third parameter of timer interrupt interval.

Abstract: The invention relates to signal conversion devices to be used for the receiving radio devices. The attained technical result is the detection and conversion of signals in an electrical two-terminal device, a data loss level being minimal.

Abstract: In one embodiment a system and method is arranged for bridging the dead-band when asynchronous signals are compared against each other. There is developed a pair of phase related signals from one of the signals, each phase related signal phase shifted from each other, but having the same frequency as the signal from which it was derived. The other frequency signal is compared against each of the phase-related developed signals to generate an error signal which quadrature rotates when the first and second signals are out of frequency with each other. A control signal is generated when the quadrature rotation is outside a certain limit. The error signal is controllably buffered to insure that the error signal only occurs when the frequencies are offset for a selected period of time.

Abstract: A method and circuit are disclosed for detecting the performance of an oscillator circuit. In particular, the circuit may detect a signal, such as the output of the oscillator circuit, failing to oscillate as desired. The second circuit may be capable of detecting whether the signal oscillates at a frequency that is less than a predetermined frequency. The second circuit may include timing circuits for determining whether the signal remains in a first logic state for at least a predetermined period of time and whether the signal remains in a second logic state for at least the predetermined period of time.

Abstract: The method and the device thereof for dynamically calibrating a frequency is provided. The method includes steps of: (a) providing a first system frequency; (b) obtaining a first parameter of timer counting number; (c) providing a second system frequency; (d) obtaining a second parameter of timer counting number if there is a frequency drift between said first system frequency and said second system frequency; (e) obtaining a third parameter of timer interrupt interval by comparing said first parameter of timer counting number with said second parameter of timer counting number; and (f) calibrating a frequency output according to said third parameter of timer interrupt interval.

Abstract: An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequency divider divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal. A frequency comparator compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.

Abstract: A phase-locked loop apparatus includes a ring oscillator including inverters, first and second transistors, a converter, mirror circuits. The first transistors control a current from a first voltage to the inverters. The second transistors control a current from the inverters. The converter converts the voltage output from the filter into a current. The first mirror circuit outputs a current in accordance with the current output from the converters. The second mirror circuit outputs a current according to the current output from the first mirror circuit to control the first transistors. The third mirror circuit outputs a current according to the current output from the second mirror circuit to control the second transistors. The converter, the first and second mirror circuits operate with a second voltage greater than the first voltage, and the ring oscillator and the third mirror circuit operate with the first voltage.

Abstract: A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached to the bus, so that a secondary bus clock speed may be set at the highest permissible speed existing at the time of system reset.

Abstract: A system and method of harmonic regulation includes a harmonic regulator configured to cancel or inject harmonics into a power conversion system. A resettable integrator is provided to determine at least one harmonic coefficient of the at least one error signal harmonic. The resettable integrator determines the at least one harmonic coefficient over a single signal period and is then reset. The harmonic regulator further includes at least one adder to determine a difference of the harmonic coefficient and the reference harmonic coefficient and a regulator is provided to determine an at least one axis harmonic reference signal. The harmonic regulator outputs a three-phase final electrical reference signal that is input into a DC/AC inverter of a power conversion system.

Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.

Abstract: The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detection circuit 5. The number of reference clock pulses in response to an RF signal pulse width (edge spacing) is detected by edge spacing detection circuit 3. The maximum value of the edge spacing in one frame, that is, the maximum edge spacing, is detected by maximum spacing detection circuit 4. The minimum value of the maximum edge spacing in multiple frames is detected by minimum spacing detection circuit 5. The maximum edge spacing minimum value is compared with a number that indicates the frame synchronizing signal period to perform frequency comparison. Edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detection circuit 5 are each constituted with registers.

Abstract: An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protection module monitors a different type of insecure condition. Each protection module asserts an alarm signal when an associated insecure condition is detected. The alarm signals asserted by the plurality of protection modules are stored.

Abstract: In digital signal demodulation and detection circuits, especially digital radio signal reception and processing circuits, the signals are received in analog form and have to be converted into logic levels. This is done in practice by comparing the level of the signal with its mean level. The mean level is established by an RC lowpass filter which introduces an inconvenient delay into the preparation of the mean level. The mean level of the signal, established by an RC filter is compared and applied to an input B of a comparator COMP, at the level of the analog signal delayed by a phase-shifter and applied to another input A of the comparator. In order that the delay introduced by the phase-shifter into the analog signal may be substantially the same as the delay given to the mean value by the RC circuit, the phase-shifter is made with the same RC circuit and an amplifier mounted so as to set up a phase shift transfer function of the (1−RCp)/(1+RCp) type where p is the Laplace variable.

Abstract: The objective of the invention is to provide technology to give high-speed DVD RF signal reading.

Abstract: An output stage suitable for low voltage operation and capable of providing an essentially symmetrical rail-to-rail output voltage including a first field effect device having a first drain, a first gate, and a first source coupled to a power supply VCC. The output stage further includes a second field effect device complimentary to the first field effect device, having a second drain, a second gate, and a second source coupled to a power supply having a nominal voltage of VEE. Further, the second drain is coupled to the first drain. Further, the output stage is an output sink network coupled to the second field effect device. The output sink network drives the second field effect device such that a current is produced in the first field effect device and a current in the second field effect device is essentially equal to a predetermined constant during operation of the output stage.

Abstract: An integrated circuit is described which is distinguished by the fact that there is integrated in it an RF filter device which can prevent or restrict the propagation of high-frequency interference signals through lines carrying DC voltages or low-frequency voltages. As a result, interference with the operation of the integrated circuit and/or of other integrated circuits or of other components of the system containing the integrated circuit can be prevented in a very simple yet extremely effective manner.

Abstract: A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.

Abstract: A present invention provides a frequency determination circuit to determine whether the frequency of a clock signal is higher or lower than a reference frequency with a high precision. A capacitor element is charged/discharged with a power supply voltage that is cycled by a switching transistor according to a clock signal. A comparator circuit compares a constant reference voltage produced by a bad gap regulator circuit from the power supply voltage with a voltage stored in the capacitor element. A high/low determination circuit determines, from the output signal of the comparator circuit, whether the clock signal frequency is higher or lower than a predetermined reference frequency. This makes it is possible to determine whether the clock signal has a low frequency or a high frequency with precision.

Abstract: A circuit for detecting abnormality of a subject clock signal, includes a frequency dividing circuit for frequency-dividing a monitoring clock signal to provide a frequency-divided monitoring clock signal; a shift register which stores the frequency-divided monitoring clock signal in synchronization with the subject clock signal; and a plurality of abnormality evaluation circuits. The abnormality evaluation circuits operate complementarily each other in accordance with an output signal of the shift register and detect abnormality of the subject clock signal for a period of time corresponding to the cycle of the monitoring clock signal.

Abstract: A flat panel display apparatus includes a sampling clock generator for generating a sampling clock signal with a frequency corresponding to a synchronous signal supplied from a host, a phase detector for detecting the phase difference between the sampling clock signal and the synchronous signal to generate a phase difference data, a comparator for comparing the phase difference data with a delay data corresponding to the synchronous signal to generate a correction signal, a micro-controller for generating the delay data and for increasing or decreasing the frequency divisional value of the sampling clock generator to adjust the frequency of the sampling clock signal in response to the correction signal, and an analog to digital converter for converting an analog video signal into corresponding digital video signal in response to the sampling clock signal.