Abstract: There is provided buffer circuitry that can include a data output circuit for connecting a first power supply to its output terminal when a data applied thereto is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level, a comparator for comparing the frequency of a clock signal applied thereto with a reference frequency, and a driving capability changing circuit for, only if the comparator outputs a comparison result indicating that the frequency of the clock signal is greater than the reference frequency, connecting a second power supply to the output terminal when the data is at a HIGH level, or connecting a ground to the output terminal when the data is at a LOW level.

Abstract: The present invention is a high frequency detection circuit (10) which includes a high frequency filter (12) and a frequency comparator (14) which compares the output of the high frequency filter with the incoming clock signal to determine if the high frequency filter is in operation. If operating, a status register is set which a microcontroller can poll to determine if an attack has been attempted. A microcode programmer can then control what sequence of events occur once the register has been set. Alternatively, detection of operation of the high frequency filter could automatically trigger a reset or interrupt of the microcontroller.

Abstract: Power-on-reset logic is included within an integrated circuit. The power-on-reset logic includes a power-on-reset cell. The power-on-reset cell causes a reset signal to be issued upon a power signal being connected to the integrated circuit. The power-on-reset cell includes a power down input connected to a power-down line. When a power-down signal is placed on the power-down line, the power-on-reset cell is inactivated so that the power-on-reset cell does not cause the reset signal to be issued upon the power signal being connected to the integrated circuit. The power-on-reset logic also includes a logic block connected to the power-down line and to a system clock. The logic block issues a reset when the power-down signal is placed on the power-down line and the system clock is active. For example, the logic block is a delay (D) flip-flop having a D input connected to the power down line and a clock input connected to the system clock.

Abstract: A system and technique of auto-configuring a first module to be in the same mode as a second module includes testing the frequency of a clock signal received from the second module to determine its mode of operation. The first module then auto-configures its ports to be in the same state as the second module. Additional test include the number of clock signals and symbol size to detect additional modes of operation. The first module is auto-configured as a result of the tests.

Abstract: An over frequency detection circuit which is based on the concept of a critical path in a design to protect an IC chip from running at a rate which will produce unpredictable results. The over frequency detection circuit will compare the output of a critical path generation circuit with that of a known path generation circuit. The known path generation circuit must have a delay which is guaranteed to be much shorter than the delay of the critical path generation circuit. If the output of the critical path generation circuit is not the same as the output of the known path generation circuit, then the critical path generation circuit has begun to fail and the IC chip should be disabled.

Abstract: A method and system for distinguishing valid DTMF signals from spurious DTMF noise includes detecting signals having a first signal component indicative of DTMF signals and having a second signal component having frequencies unrelated to DTMF frequencies. The second component is utilized in isolation from the DTMF frequencies of the first signal component. The analysis includes determining a signal level representative of the second signal component. If the signal level exceeds a predetermined threshold level, the first signal component is determined to be spurious noise. On the other hand, if the signal level is below the threshold level, the first signal component is passed to a DTMF-responsive system, such as a voicemail system or a voice response unit. Optionally, the operation includes requesting confirmation of the signal of interest, if the signal level of the second signal component falls within a range which includes the threshold level as its upper limit.

Abstract: Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Abstract: A circuit for detecting a predefined reoccurring phase point an periodic electrical signal has an input stage which rectifies the signal into first and second complementary signals. A Schmitt circuit has an input connected to the rectifier stage and produces a first intermediate signal in response to the voltage of the first complementary signal. A complementary Schmitt circuit is connected to the rectifier stage and produces a second intermediate signal in response to the voltage of the second complementary signal. An output stage that is connected to the Schmitt circuit and the complementary Schmitt circuit, responds to the first and second intermediate signals by producing an indication of each occurrence of the reoccurring phase point in the periodic electrical signal.

Abstract: A circuit for measuring the frequency of an electrical signal includes a detector that senses a reoccurring phase point the electrical signal. A divide-by-M counter is connected to the detector and produces a control signal upon every Mth occurrence of the indication, where M is a positive number greater than one. A clock signal generator is provided. An output counter counts cycles of the clock signal between occurrences of the control signal and divides the count by M to produce an output count that corresponds to the frequency of the electrical signal.

Abstract: A microprocessor with automatic and dynamic partname determination including performance number. The microprocessor includes circuitry that measures a core clock frequency for the microprocessor and circuitry that determines a performance indication for the microprocessor in response to the measured core clock frequency.

Abstract: A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.

Abstract: A frequency discriminator circuit that includes a signal shaping and power splitting circuit (20) responsive to a sinusoidal RF input signal for providing first and second substantially identical squarewave outputs having the same frequency as the sinusoidal RF signal, a digital delay line (19) responsive to the first squarewave output for providing a delayed replica of the first squarewave output, an exclusive OR gate (21) responsive to the second squarewave output and the delayed replica of the first squarewave output, low pass filters (23, 25) for averaging each of the inverted and non-inverted outputs of the exclusive OR gate, and a differential amplifier (27) for subtracting the outputs of the low pass filters from each other and providing an output indicative of the frequency of the RF input signal.

Abstract: A digital loss of lock detection (LLD) device for a phase looked loop (PLL) generates a locked frequency signal synchronized with a reference frequency signal. The LLD comprises first to fifth latching means for detecting when the reference clock failed high/low, when the locked clock failed high/low and when the reference clock is outside the tracking range of the PLL. The first to fifth latching means provide respectively a first to fifth error signals for each type of the above faults.

Abstract: A frequency difference detection apparatus includes a first PLL, a second PLL, a first phase difference detection unit, a second phase difference detection unit, a phase difference processing unit, and a frequency difference detection unit. The first PLL detects a phase difference between an input clock and an output clock in response to the input clock and performs control to gradually suppress the detected phase difference to zero. The second PLL detects a phase difference between the input clock and an output clock in response to the input clock and performs control to suppress the detected phase difference to zero at a speed higher than that of the first PLL. The first phase difference detection unit detects a phase difference between the input clock and the output clock from the first PLL. The second phase difference detection unit detects a phase difference between the input clock and the output clock from the second PLL.

Abstract: The present invention relates to a low frequency discriminator circuit comprised if apparatus for providing a rectangular wave input signal, apparatus for integrating the input signal, apparatus for detecting whether the integrated input signal falls between upper and lower thresholds respectively, and apparatus for providing an output signal indicating when the integrated input signal falls between the thresholds, whereby the frequency of the input signal may be determined to be between higher and lower limits.

Abstract: A frequency lock indicator (10) comprises a first delay (14), second delay (20), first sampler (24), second sampler (28), third sampler (32), fourth sampler (34), and lock indicator (36). The first delay (14) delays a rising edge of a frequency reference (12) which clocks the first sampler (24) on a rising edge and the third sampler (32) on a falling edge. The second delay (20) delays a rising edge of a feedback signal (18) to produce a delayed feedback signal (22) which clocks the second sampler (28) on a rising edge and the fourth sampler (34) on a falling edge. The first and third samplers sample an up-pump signal (26) and the second and fourth samplers sample a down-pump signal (30). The lock indicator (36) produces a lock indication signal (38) when the sampled up-pump signal substantially equal to the sampled down-pump signal.

Abstract: A delay detection circuit and a low-noise oscillation circuit using such a delay detection circuit. When the oscillation output of a VCO is to be supplied to two high frequency mixers, a .pi./2 phase shifter 24 in the front stage of one of the high frequency mixers gives a quadrature form. High frequency components are removed from the output voltage of the high frequency mixers by LPF. DC components are also removed from the output voltage of the high frequency mixers by HPF. The output voltages of low frequency mixers contain secondary phase noise components proportional to squared phase noise components and primary phase noise components proportional to the phase noise components and also depending on the delay time .tau. of a delay unit. When the output voltage of one of the low frequency mixers is subtracted from the output voltage of the other low frequency mixer, the secondary phase noise components are offset and the dependence on the delay time .tau.

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Abstract: A digital FM modulating apparatus includes a device for restricting modulation data between a lower limit data value and an upper limit data value which respectively correspond to a minimum allowable frequency and a maximum allowable frequency value of an FM modulated signal. The apparatus also includes a device for suppressing transitional variance in the restricted modulating data and a direct digital synthesizer for receiving the suppressed data and producing synthesized data corresponding to the FM modulated signal.

Abstract: A data communication receiver (10) uses a decision feedback demodulator (32) to remove data from a received signal. Quadrature components of the received signal define a received phase. The received phase is rotated (46) by an amount predicted to compensate for phase and frequency errors. After this rotation, a decision circuit (52) determines the modulation phase for a current symbol. A phase rotator (64) compares the modulation phase with the received phase to generate a measured phase error for the symbol. This measured phase error and measured phase errors from past symbols are averaged in a combination circuit (80) to produce a phase estimate. The past measured phase errors are also processed to determine the amount of change in measured phase error that has occurred over a number of symbols. This processing yields a frequency estimate. A phase rotator (94) merges the frequency and phase estimates for use in compensating a current received phase.

Abstract: A frequency demodulation circuit having an improved detection sensitivity is provided by forming an all-pass equalizer in a Quadrature-type demodulator capable of allowing a band covering at least a carrier frequency deviation to pass therethrough. The equalizer comprises a band-pass filter for detecting the frequency deviation of an inputted FM carrier signal, a gain-doubling amplifier and a substractor for performing subtraction between the signal inputted to the band-pass filter and the output of the amplifier. The operation of the circuit is such that a FM carrier signal is supplied to the band-pass filter through a phase shifter and to a phase comparator and the output of the substractor and the FM carrier signal are compared to each other by the phase comparator to thereby obtain a FM demodulated signal.

Abstract: A delay chain having a known number of delay elements providing various delayed outputs of its input, a first and a second register set, and preferably, an array of multiplexors, are provided to measure the frequency of a digital signal, and the high and low time of its period. The digital signal to be measured is provided to the delay chain as input. A first and a second sample of the various delayed outputs are taken at the beginning and the end of a known time period, and stored in the first and second registers, one delayed output per register bit. The sample results stored in the register sets are read out through the multiplexors, and used to determine the frequency of the digital signal being measured, and the high and low time of its period.

Abstract: A pulse measuring instrument for measuring various pulse signal parameters such as the pulse width, the signal period of an input signal, and the time interval between input signals is capable of measuring the signal parameters with a high degree of accuracy and simplicity by automatically calibrating the propagation time difference between the input signal paths in the circuit configuration in the measuring instrument. The pulse signal measuring instrument is first provided with a calibration signal at the input terminal to obtain calibration data. The calibration data includes various time difference data regarding signal propagation time difference between the different signal paths in the measuring instrument. The calibration data also includes the signal period of the calibration signal and standard pulse width of the calibration signal. The calibration data is stored in a computer in the pulse signal measuring instrument.