Insulated Gate Fet (e.g., Mosfet, Etc.) Patents (Class 327/434)
  • Publication number: 20140002174
    Abstract: A method and apparatus for current drain switching with a replica loop. The method comprises the steps of: matching a voltage across a current sense resistor with a voltage created by a reference current across a matched reference resistor; replicating an operating point of an output transistor using a scaled matched replica of the output transistor and the current sense resistor. The method then shifts a feedback voltage from the output sense resistor to the matched replica sensor and shifts the output of a gate from an output transistor to the replica transistor. A first switch is then actuated in order to preserve the gate charge of the output transistor. A second switch is actuated to sample and hold a drain voltage in the buffer in order to bias the drain of the replica transistor. The third switch is then activated to stop the output current.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Hua Guan, Eric B. Zeisel, Qi Lou
  • Publication number: 20140002175
    Abstract: A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Application
    Filed: December 13, 2012
    Publication date: January 2, 2014
    Applicant: Cyclos Semiconductor, Inc.
    Inventor: Cyclos Semiconductor, Inc.
  • Publication number: 20130343138
    Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.
    Type: Application
    Filed: August 28, 2013
    Publication date: December 26, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Dariusz KOWALCZYK
  • Patent number: 8610490
    Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
  • Patent number: 8610469
    Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of th
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 17, 2013
    Assignee: THAT Corporation
    Inventor: Gary K. Hebert
  • Patent number: 8604865
    Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: December 10, 2013
    Assignee: EM Microelectronic-Marin S.A.
    Inventors: Nicolas Pillin, David A. Kamp
  • Patent number: 8604841
    Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 10, 2013
    Assignee: ABB Research Ltd
    Inventors: Yanick Lobsiger, Dominik Bortis, Johann Walter Kolar, Matti Laitinen
  • Patent number: 8604864
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: December 10, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Patent number: 8598920
    Abstract: A gate driving circuit for driving a voltage-driven switching device is provided with a current limiting circuit for limiting a gate current ig that flows into a gate terminal through a gate resistor at turn-on to a current limit value IL which defines an upper limit value. The current limit value IL is set at a value which is larger than a gate current value I2 at turn-on of the switching device during a period when the Miller effect occurs but is smaller than a gate current value I1 at a point in time when a main current begins to flow at turn-on in a case where the gate current ig is not limited by the current limiting circuit. This arrangement makes a variation in a collector current of the switching device moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 3, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Nakatake, Shinichi Kinouchi, Tatsuya Kitamura
  • Publication number: 20130314128
    Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: Joseph M. HENSLEY, Franklin M. MURDEN
  • Publication number: 20130314146
    Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.
    Type: Application
    Filed: May 22, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Mu-Shan Lin
  • Publication number: 20130307608
    Abstract: A reference voltage generator includes a first transistor and a second transistor coupled in series between a current supply and ground. Gate insulating films of the first transistor and the second transistor are made of the same type of film with the same thickness. Impurities contained in gate electrodes of the first transistor and the second transistor have different conductivity types, or have the same conductivity type and different concentrations. The first transistor has a greater gate width than the second transistor. The first transistor and the second transistor operate in a subthreshold region when a reference voltage is output outside.
    Type: Application
    Filed: July 25, 2013
    Publication date: November 21, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Keita TAKAHASHI
  • Patent number: 8587363
    Abstract: There is provided a high frequency switching circuit reducing power consumption at the time of signal reception and signal transmission. The high frequency switching circuit includes a pulse generation unit generating a clock selecting pulse signal having a predetermined active period; a clock selection unit selecting a reference clock signal when the clock selecting pulse signal is in an active state and selecting a low-speed clock signal having a frequency lower than that of the reference clock signal when the clock selecting pulse signal is not in an active state; a voltage down unit accumulating negative charges in a capacitor to generate predetermined negative voltage; and a switching unit including at least one switch holding a turned-off state by being applied with the predetermined negative voltage.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: November 19, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Eiichiro Otobe
  • Patent number: 8587361
    Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans Taddiken, Thomas Boettner
  • Patent number: 8587362
    Abstract: A gate driver for driving a gate of a switching element Tr7 includes a driving part that drives the switching element according to a control signal and an active clamp circuit to clamp the voltage between the first and second main terminals of the switching element through the driving part. If a voltage applied between a first main terminal (drain) and a second main terminal (source) of the switching element exceeds a predetermined voltage, the active clamp circuit forcibly blocks a driving operation of the driving part from driving the switching element.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 19, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Osamu Machida, Hironori Aoki
  • Publication number: 20130300493
    Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.
    Type: Application
    Filed: May 7, 2013
    Publication date: November 14, 2013
    Applicant: MONOLITHIC POWER SYSTEMS, INC.
    Inventors: Da Chen, Zhengwei Zhang, Wei Mao
  • Publication number: 20130300492
    Abstract: A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power.
    Type: Application
    Filed: August 8, 2012
    Publication date: November 14, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Yu Zhao, Xiang Sun, Fei Wang, Dong Chen
  • Patent number: 8581656
    Abstract: A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: November 12, 2013
    Assignee: Infineon Technologies AG
    Inventor: Giacomo Curatolo
  • Patent number: 8575991
    Abstract: Disclosed herein is a resistor-sharing switching circuit including: a first switching device and a second switching device; and a resistor whose first end is connected to a control signal input end to which a control signal for controlling bodies of the first switching device and the second switching device is applied and whose second end is connected to the bodies of the first switching device and the second switching device.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 5, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yu Sin Kim, Sung Hwan Park
  • Patent number: 8570092
    Abstract: A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol includes a switch unit, first and second electronic switches, and first and second switch chips. When the switch unit outputs a high level signal to the first electronic switch, the connector transmits data according to LPC protocol. When the switch unit outputs a low level signal to the first electronic switch, the connector transmits data according to JTAG protocol.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 29, 2013
    Assignees: Hong Fu Jin Precision industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Jie Li
  • Publication number: 20130265100
    Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Valeria Bottarel, Giulio Ricotti, Fabio Quaglia
  • Publication number: 20130265097
    Abstract: An aspect of the present embodiment, there is provided a semiconductor integrated circuit, including a first transistor configured to switch whether or not a first node electrically connects to a second node, and a switch control circuit configured to supply higher potential to a substrate potential of the first transistor in a state of turning of the first transistor, when at least one of potentials of the first node and the second node is equal to or higher than a predetermined potential which is higher than a potential of a power supply.
    Type: Application
    Filed: February 25, 2013
    Publication date: October 10, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masafumi MIYAZAWA, Masaki NODA
  • Publication number: 20130265099
    Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.
    Type: Application
    Filed: May 28, 2013
    Publication date: October 10, 2013
    Inventors: Jerome Alexandre Bürki, Charles Allen Stafford, Daniel L. Stein
  • Publication number: 20130265098
    Abstract: A solid-state relay is provided, which includes a first transistor, a second transistor, a first transmission circuit, and a second transmission circuit. A gate of the first transistor is connected to one of a source and a drain of the second transistor, one of a source and a drain of the first transistor is connected to a first terminal, and the other of the source and the drain of the first transistor is connected to a second terminal. The first transmission circuit supplies a first signal to the gate of the first transistor. The second transmission circuit supplies a second signal to a gate of the second transistor. The first terminal is connected to the second terminal when the first transistor is turned on by the first signal.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 10, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Shunpei Yamazaki
  • Patent number: 8552792
    Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 8, 2013
    Assignees: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Dong-Liang Ren
  • Publication number: 20130257515
    Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Ladurner, Robert Illing
  • Publication number: 20130257516
    Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.
    Type: Application
    Filed: August 28, 2012
    Publication date: October 3, 2013
    Applicants: HON HAI PRECISION INDUSTRY CO., LTD., HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
    Inventor: DONG-LIANG REN
  • Patent number: 8547143
    Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: October 1, 2013
    Assignee: Yaskawa America, Inc.
    Inventors: Mahesh M. Swamy, Tsuneo Joe Kume
  • Patent number: 8547159
    Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 1, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: James Joseph Morra
  • Patent number: 8547162
    Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jacek Korec, Christopher B. Kocon, Shuming Xu
  • Patent number: 8547161
    Abstract: Embodiments of a circuit, which includes a device and a switch, which is electrically coupled to the device, to control power applied to the device, are described. This switch includes a control terminal, which controls the switch, and two other terminals, which can receive power to be applied to the device. Moreover, the circuit is configured to apply a voltage to the control terminal to ensure the switch remains open when a supply voltage is applied to one of the two other terminals while powering-up the circuit, thereby preventing spurious application of the supply voltage to the device.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: October 1, 2013
    Assignee: Google Inc.
    Inventors: Jinal Dalal, Srikanth Lakshmikanthan, Chris Lyon, Maire Mahony
  • Patent number: 8542058
    Abstract: A semiconductor device includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Myung-Hee Na, Edward J. Nowak
  • Patent number: 8519772
    Abstract: Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Albert M. Chu, Daryl M. Seitzer, Rohit Shetty, Douglas W. Stout
  • Patent number: 8519773
    Abstract: A method for switching between first and second voltages is provided. Initially, a first voltage is provided from a first input terminal to an output terminal through a first MOS transistor, and the first MOS transistor is deactivated. A back-gate of a second MOS transistor is shorted to the output terminal in response to the deactivation of the first MOS transistor and after a settling interval, and the second MOS transistor is activated while its back-gate is shorted to the terminal so as to provide a second voltage from a second input terminal to the output terminal.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: August 27, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Watanabe, Hiroaki Kojima, Kazuya Machida
  • Publication number: 20130214846
    Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 22, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Renesas Electronics Corporation
  • Patent number: 8508282
    Abstract: A LIN network comprises a transmit driver and a receive comparator for communicating low frequency signals on a single communication bus. The transmit driver is operably coupled to a high frequency detector to detect a high frequency component on the low frequency signal. In response to detecting the high frequency component the LIN network is arranged to perform one or both of the following: route the low frequency signal having a high frequency component through a low pass filter; and/or bypass the low frequency signal having a high frequency component from passing through an active device operably coupled between the transmit driver and the single communication bus.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: August 13, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Thierry Sicard
  • Publication number: 20130200941
    Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 8, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Nicola Maglione
  • Patent number: 8502594
    Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: August 6, 2013
    Assignee: Linear Technology Corporation
    Inventor: Jesper Steensgaard-Madsen
  • Patent number: 8502595
    Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Julie Lynn Stultz, James Joseph Morra, Steven Macaluso
  • Publication number: 20130194027
    Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
    Inventor: Mladen Ivankovic
  • Publication number: 20130187703
    Abstract: Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal.
    Type: Application
    Filed: March 12, 2013
    Publication date: July 25, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Micron Technology, Inc.
  • Patent number: 8487668
    Abstract: When there is a short circuit failure between the gate and emitter of a main switching element such as an IGBT, the temperature of a turn-on gate resistor or turn-off gate resistor is detected by a thermistor, and a drive circuit is protected by turning off a turn-on gate drive switching element or a turn-off gate drive switching element. Furthermore, instead of detecting the temperature of the turn-on gate resistor or turn-off gate resistor, a thermistor is connected in series with the turn-on gate drive switching element or turn-off gate drive switching element, the resistance change corresponding to a change in temperature of the thermistor is detected, and the drive circuit is protected by turning off the turn-on gate drive switching element or turn-off gate drive switching element.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 16, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasushi Abe
  • Patent number: 8487795
    Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: July 16, 2013
    Assignees: LSI Corporation, Oregon State University
    Inventors: Tao Jiang, Patrick Yin Chiang, Freeman Y. Zhong
  • Patent number: 8482336
    Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Pinping Sun, Kai D. Feng, Essam Mina
  • Patent number: 8482337
    Abstract: There is provided a high frequency semiconductor switch having an FET designed in consideration of characteristics required for a transmission terminal and a reception terminal. The high frequency semiconductor switch includes a plurality of field effect transistors that each include a source region and a drain region formed on a substrate to be spaced apart by a predetermined distance, a gate formed on the substrate to be disposed at the predetermined distance, a source contact formed on the substrate to be connected with the source region, and a drain contact formed on the substrate to be connected with the drain region. A distance between a source contact and a drain contact of a reception terminal side transistor is longer than a distance between a source contact and a drain contact of a transmission terminal side transistor.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Tsuyoshi Sugiura
  • Patent number: 8476940
    Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: July 2, 2013
    Assignee: STMicroelectronics International N.V.
    Inventor: Vinod Kumar
  • Publication number: 20130162327
    Abstract: A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.
    Type: Application
    Filed: January 23, 2013
    Publication date: June 27, 2013
    Applicant: LG Display Co., Ltd.
    Inventor: LG Display Co., Ltd.
  • Publication number: 20130162299
    Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC).
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventor: Chuan GONG
  • Patent number: 8471622
    Abstract: The invention provides a switching circuit of a power semiconductor device having connected in parallel SiC diodes with a small recovery current, capable of significantly reducing turn-on loss and recovery loss without increasing the noise in the MHz band, and contributing to reducing the loss and noise of inverters. The present invention provides a switching circuit and an inverter circuit of a power semiconductor device comprising a module combining Si-IGBT and SiC diodes, wherein an on-gate resistance is set smaller than an off-gate resistance.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: June 25, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ishikawa, Kazutoshi Ogawa, Masahiro Nagasu
  • Publication number: 20130154718
    Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Applicant: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Johan Hendrik Huijsing, Qinwen Fan, Kofi Afolabi Anthony Makinwa