Insulated Gate Fet (e.g., Mosfet, Etc.) Patents (Class 327/434)
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Patent number: 8779838Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.Type: GrantFiled: October 25, 2011Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Zhijian Yang, Ping-Chuan Wang, Kai D. Feng, Edwin J. Hostetter, Jr.
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Publication number: 20140191792Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a deep well, a first well, a first doped electrode region, a second doped electrode region and a high threshold voltage channel region. The substrate has a first type conductivity. The deep well is formed in the substrate and has a second type conductivity opposite to the first conductivity. The first well is formed in the deep well and has at least one of the first type conductivity and the second type conductivity. The first and the second doped electrode regions are formed in the first well. The second doped electrode is adjacent to the first doped electrode and has the second conductivity. The high threshold voltage channel region is formed in the first well and extending down from the surface of the substrate.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ching-Lin Chan, Chen-Yuan Lin, Cheng-Chi Lin, Shih-Chin Lien
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Publication number: 20140184309Abstract: A high voltage electrical switch including: a plurality of series connected semiconductor switches; a plurality of rectifiers wherein each rectifier is connected to a semiconductor switch control input of one of the semiconductor switches; a radio frequency signal generator; and a plurality of galvanic isolators, wherein each galvanic isolator connects the radio frequency signal generator to one of the plurality of rectifiers, wherein the plurality of semiconductor switches are isolated from one another.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: NXP B.V.Inventors: Peter Gerard Steeneken, Arnoud Pieter van der Wel
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Publication number: 20140184310Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a âTâ configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.Type: ApplicationFiled: March 5, 2014Publication date: July 3, 2014Applicant: Texas Instruments IncorporatedInventors: Vineet Mishra, Rajavelu Thinakaran
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Patent number: 8766702Abstract: A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction.Type: GrantFiled: April 5, 2012Date of Patent: July 1, 2014Assignee: Mitsubishi Electric CorporationInventors: Khalid Hassan Hussein, Toshiyuki Kumagai, Shoji Saito
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Publication number: 20140168881Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Inventors: Hong Yun Tan, Anant S. Deval, R. Kenneth Hose, JR.
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Publication number: 20140159798Abstract: The present invention provides an array substrate, a driving method and a display device. The array substrate comprises a plurality of gate lines. A first gate line of the two adjacent gate lines is coupled to a first switch unit and a second gate line is coupled to a second switch unit. The first switch unit and the second switch unit are coupled to a control line, and are coupled to a gate drive output channel. The second switch unit is turned off when the first switch unit is turned on under control of the control line, and the first switch unit is turned off when the second switch is turned on under control of the control line. According to the present invention, it is able to effectively reduce the number of the gate drive ICs and thereby to reduce the cost.Type: ApplicationFiled: December 9, 2013Publication date: June 12, 2014Applicants: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventor: Xin Duan
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Patent number: 8742829Abstract: The present invention is a method and circuitry for driving a high-threshold MOS device on low input voltages. The invention includes a circuit that operates on a supply voltage that is less than the threshold voltage of the high-threshold MOS device. The circuit includes one or more low threshold MOS inverters and one or more capacitors that operate at low input voltages. The one or more low threshold MOS inverters operate in a manner that the one or more capacitors get charged to a voltage greater than the low input voltage. Thereafter, the charged capacitor drives the high threshold MOS device.Type: GrantFiled: April 19, 2012Date of Patent: June 3, 2014Assignee: Micrel, Inc.Inventor: Michael Joseph Mottola
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Patent number: 8742827Abstract: A functional circuit is coupled to a power supply conductor by at least one power gating transistor. A switching device applies a gate drive voltage to a gate terminal of the power gating transistor via a resistive element. The power gating transistor provides a Miller capacitance between its drain and gate terminals. The Miller capacitance, the resistance of the resistive element, and the drive strength of the switching device are configured such that, in response to the switching device switching the gate drive voltage to allow more current to pass through the power gating transistor, the Miller capacitance provides a feedback mechanism competing against the switching device to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and the functional circuit through the power gating transistor is less than the saturation current of the power gating transistor.Type: GrantFiled: May 24, 2011Date of Patent: June 3, 2014Assignee: ARM LimitedInventors: Nicolaas Klarinus Johannes Van Winkelhoff, Mikael Brun
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Patent number: 8742802Abstract: A highly-reliable gate driving circuit achieved by suppressing the amount of hot-carriers generated in a MOSFET. In the gate driving circuit having NOEMI circuits, same-type NOEMI circuits are connected in series with a p-channel MOSFET constituting a gate charging circuit and an n-channel MOSFET constituting a gate discharging circuit, respectively, so as to suppress the amount of hot-carriers generated in the p-channel MOSFET and the n-channel MOSFET.Type: GrantFiled: November 16, 2011Date of Patent: June 3, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Akihiro Jonishi, Hitoshi Sumida
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Patent number: 8742828Abstract: A disconnecting apparatus for direct current interruption between a direct current source and an electrical device, in particular between a photovoltaic generator and an inverter, has a current-conducting mechanical switching contact and semiconductor electronics connected in parallel with the switching contact. The semiconductor electronics are non-conducting when the switching contact is closed, wherein a control input of the semiconductor electronics is wired with the switching contact in such a way that, when the switching contact opens, an arc voltage generated as a result of an arc via the switching contact switches the semiconductor electronics to become conducting.Type: GrantFiled: September 22, 2011Date of Patent: June 3, 2014Assignee: Ellenberger & Poensgen GmbHInventors: Michael Naumann, Thomas Zitzelsperger, Frank Gerdinand
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Patent number: 8742826Abstract: According to one embodiment, an active clamp circuit includes a first switch element, a first diode, a first resistance, a first control circuit and a second control circuit. The first diode is connected to the first switch element and breaks down by an overvoltage applied to the first switch element. The first resistance is connected to the first diode and detects a current through the first diode. The first control circuit is configured to amplify a voltage across the first resistance and controls a current through the first switch element. The second control circuit is configured to control a conduction of the first switch element in accordance with the voltage across the first resistance.Type: GrantFiled: February 28, 2012Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Miki Furuya, Satoru Kodama
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Publication number: 20140144240Abstract: Apparatus and methods for ultrasound probes are provided. In certain implementations, a receive switch for an ultrasound probe includes a first field effect transistor (FET) and a second FET electrically connected in series between a first terminal and a second terminal with the FETs' sources connected to one another. The receive switch includes a positive threshold detection and control circuit for turning off the receive switch when a voltage of the first terminal is greater than a positive threshold voltage, and a negative threshold detection and control circuit for turning off the receive switch when the first terminal's voltage is less than a negative threshold voltage. The receive switch further includes a gate bias circuit that can bias the gates of the first and second FETs so as to turn on the receive switch when no positive or negative high voltage conditions are detected on the first terminal.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: ANALOG DEVICES, INC.Inventors: Allen R. BARLOW, Gerard E. TAYLOR, Corey D. PETERSEN
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Publication number: 20140145783Abstract: A semiconductor integrated circuit includes an output MOS transistor and a back gate control circuit. The output MOS transistor includes a first electrode connected to a power supply terminal and a second electrode connected to an output terminal. The output MOS transistor is configured to turn on and off to cause communications to be performed with another semiconductor integrated circuit connected to the output terminal. The back gate control circuit is configured to control an electric potential at a back gate of the output MOS transistor so that a current path between the power supply terminal and the output terminal at a time when a power supply connected to the power supply terminal is turned off is interrupted.Type: ApplicationFiled: November 6, 2013Publication date: May 29, 2014Applicant: MITSUMI ELECTRIC CO., LTD.Inventors: Tomomitsu OHARA, Masato YOSHIKUNI
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Patent number: 8736349Abstract: The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current.Type: GrantFiled: August 28, 2012Date of Patent: May 27, 2014Assignee: National Chiao Tung UniversityInventors: Tsung-Lin Chen, Edward Yi Chang, Wei-Hua Chieng, Stone Cheng, Shyr-Long Jeng, Shin-Wei Huang
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Patent number: 8729952Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.Type: GrantFiled: August 16, 2012Date of Patent: May 20, 2014Assignee: TriQuint Semiconductor, Inc.Inventors: Xiaomin Yang, James P. Furino, Jr.
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Patent number: 8729926Abstract: According to one embodiment, an output signal circuit for use in a receiver is provided. The output signal circuit is provided with first and second transistors of an insulated gate field effect type, and a backgate bias generator. A source of the first transistor is capable of receiving an input signal. A source of the second transistor is capable of generating an output signal. A backgate bias generator produces a backgate bias voltage which is applied to backgate of the first and second transistors commonly.Type: GrantFiled: March 16, 2012Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Mei Lian Lim
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Patent number: 8729953Abstract: A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.Type: GrantFiled: January 23, 2013Date of Patent: May 20, 2014Assignee: LG Display Co., Ltd.Inventors: Yong-Min Ha, Kee-Jong Kim, Byeong-Koo Kim
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Patent number: 8717085Abstract: According to one embodiment, a resonant gate driver comprises a resonant path configured to couple a gate of a power transistor to a supply capacitor, and a low impedance path configured to couple the gate of the power transistor to a voltage rail. The resonant gate driver selectively utilizes the resonant path during charging and discharging of the gate, and selectively utilizes the low impedance path to couple the gate to the voltage rail when the gate is neither charging nor discharging. A method for use by the resonant gate driver for driving the power transistor comprises charging and discharging the gate of the power transistor by selectively coupling the gate to a supply capacitor through a resonant path, and utilizing a low impedance path to selectively couple the gate to a voltage rail when the gate is neither charging nor discharging.Type: GrantFiled: August 26, 2011Date of Patent: May 6, 2014Assignee: International Rectifier CorporationInventor: Marco Cioci
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Publication number: 20140118056Abstract: A semiconductor device includes a control section, a first arm, and a second arm; and has an H-bridge circuit to supply an input current supplied from a power source to an output terminal as a reversible electric current on the basis of a control signal outputted from the control section and a reverse-connection-time backflow prevention circuit to prevent an electric current in a direction opposite to the direction of the input current from being supplied to the H-bridge circuit. The first arm is formed over a first island. The second arm is formed over a second island. The control section and the reverse-connection-time backflow prevention circuit are formed over a third island.Type: ApplicationFiled: October 18, 2013Publication date: May 1, 2014Applicant: Renesas Electronics CorporationInventor: Kenji AMADA
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Publication number: 20140118057Abstract: A circuit includes a transformer having a first winding and a second winding, an input connected to a first terminal of the first winding, a first power transistor and a second power transistor. The first power transistor has a source, a gate, and a drain connected to a second terminal of the first winding. The second power transistor has a source connected to ground, a gate connected to a pulsed voltage drive source and a drain connected to the source of the first power transistor. The gate of the first power transistor is connected to a DC source or the same pulsed voltage drive source as the gate of the second power transistor. The first power transistor actively turns off independent of load current. Other circuit embodiments and corresponding load switching methods are also provided.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: Infineon Technologies Austria AGInventor: Mladen Ivankovic
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Patent number: 8710900Abstract: In one general aspect, an apparatus including a first voltage rail, and a second voltage rail. The apparatus includes a first P-type metal-oxide-semiconductor field effect transistor (MOSFET) PMOS device between the first voltage rail and the second voltage rail where the first PMOS device is configured to electrically couple the first voltage rail to the second voltage rail in response to the first PMOS device being activated. The apparatus can also include a second PMOS device configured to provide a charge pump voltage produced by a charge pump device to the second voltage rail in response to the second PMOS device being activated and the first PMOS device being deactivated. The apparatus can also include a pass gate, and a driver circuit coupled to the pass gate and configured to operate based on a voltage of the second voltage rail.Type: GrantFiled: March 22, 2012Date of Patent: April 29, 2014Assignee: Fairchild Semiconductor CorporationInventors: Nickole Gagne, Kenneth P. Snowdon
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Patent number: 8711598Abstract: A memory cell includes six transistors. The first and second P-type transistors have the sources coupled to a first voltage. The first and second N-type transistors have the drains coupled to drains of the first and second P-type transistors, respectively; the sources coupled to a second voltage; and the gates coupled to gates of the first and second P-type transistors, respectively. The third N-type transistor has the drain coupled to a write word line; the source coupled to drain of the first N-type transistor and gate of the second N-type transistor; and the gate coupled to a first write bit line. The fourth N-type transistor has the drain coupled to the write word line; the source coupled to drain of the second N-type transistor and gate of the first N-type transistor; and the gate coupled to a second write bit line. A memory cell array is also provided.Type: GrantFiled: November 21, 2012Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Hsin-Wen Chen, Chi-Chang Shuai, Shih-Chin Lin
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Patent number: 8710543Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.Type: GrantFiled: April 30, 2012Date of Patent: April 29, 2014Assignee: Sharp Kabushiki KaishaInventor: Yuhji Ichikawa
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Publication number: 20140113680Abstract: A switch control circuit has level shifters connected to a switch circuit to convert voltage levels of control signals, a negative potential generating circuit connected to the level shifter, to generate a negative potential, a negative potential output line supplying the negative potential to the level shifter, and a negative potential output line control circuit configured to control the potential of the negative potential output line. The negative potential output line control circuit has a power-supply setting circuit, an inverter inverting the output signal from the power-supply setting circuit, a first capacitor connected between an output terminal of the inverter and the negative potential output line, and a negative potential initialization circuit.Type: ApplicationFiled: December 26, 2013Publication date: April 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Toshiki SESHITA
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Patent number: 8704357Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.Type: GrantFiled: October 5, 2011Date of Patent: April 22, 2014Assignee: Rohm Co., Ltd.Inventor: Atsushi Kitagawa
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Patent number: 8698358Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.Type: GrantFiled: October 2, 2012Date of Patent: April 15, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Marvin L. Peak, Jr., Bradley M. Harrington, Matthew R. Harrington
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Patent number: 8698547Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.Type: GrantFiled: September 21, 2012Date of Patent: April 15, 2014Assignee: Fujitsu LimitedInventor: Hiroshi Nakao
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Publication number: 20140097884Abstract: An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.Type: ApplicationFiled: June 15, 2011Publication date: April 10, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Valery Neiman, Michael Priel
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Patent number: 8674757Abstract: The invention provides a switching system. The switching system comprises an H bridge, a current router, and a control circuit. The H bridge comprises a first switch and a second switch coupled to a first output node and a third switch and a fourth switch coupled to a second output node, wherein a load is coupled between the first output node and the second output node. The current router comprises a first shunt switch and a second shunt switch coupled between the first output node and the second output node. The control circuit generates a first control signal to control the first switch and the fourth switch, generates a second control signal to control the second switch and the third switch, generates a third control signal to control the first shunt switch, and generates a fourth control signal to control the second shunt switch.Type: GrantFiled: April 16, 2012Date of Patent: March 18, 2014Assignee: NeoEnergy Microelectronic, Inc.Inventors: Li-Te Wu, Wei-Chan Hsu
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Patent number: 8669805Abstract: A coupling circuit has a first and a second transistor (P1, P2) of a p-channel field-effect transistor type. A drain terminal of the first transistor (P1) is connected to a signal input (1), source terminals of the first and the second transistor (P1, P2) are commonly connected to a signal output (2), bulk terminals of the first and the second transistor (P1, P2) are commonly connected to a drain terminal of the second transistor (P2), and a gate terminal of the first transistor (P1) is connected to a gate terminal of the second transistor (P2). The coupling circuit further comprises a gate control circuit (10) with a charge pump circuit (110) which is configured to generate a negative potential. The gate control circuit (10) is configured to control a gate voltage at the gate terminals of the first and the second transistor (P1, P2) based on a negative potential.Type: GrantFiled: August 27, 2010Date of Patent: March 11, 2014Assignee: AMS AGInventors: Riccardo Serventi, Luigi Di Piro, Monica Schipani, Paolo D'Abramo
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Patent number: 8665004Abstract: A device for controlling (10) a power transistor (5), comprises: an amplifying device (15) for monitoring the transistor gate (5) via an output control signal, the device including: a first input connected to the transistor drain, the whole assembly forming a first circuit portion; a second input connected to the transistor source, the whole assembly forming a second circuit portion. The control device comprises means for producing a polarizing current (I1, I2), the current being injected into the first and second inputs (NEG, POS) so as to offset the drain-source voltage measurement and maintain a linear operating mode of the output control signal, prior to opening the transistor, and the same number of N semiconductor junctions in the first and second circuit portions. The device is applicable in particular on battery charging devices.Type: GrantFiled: January 4, 2007Date of Patent: March 4, 2014Assignee: Valeo Equipements Electriques MoteurInventor: Hugues Doffin
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Patent number: 8659345Abstract: A switch level circuit (110) with dead time self-adapting control, which minimizes the switching loss in a switching power supply converter with synchronous rectification by changing a dead time between a high-side control transistor (10) and a low-side synchronous rectifying transistor (11). The switch level circuit (110) includes the high-side control transistor (10) and the low-side synchronous rectifying transistor (11) which are controlled to be on and off by external control signals, and a waveform with a given duty cycle is outputted at a node (LX) between the two transistors. The switch level circuit (110) also includes a control module for adjusting the dead time.Type: GrantFiled: October 26, 2010Date of Patent: February 25, 2014Assignee: Southeast UniversityInventors: Shen Xu, Weifeng Sun, Miao Yang, Sichao Liu, Youshan Jin, Shengli Lu, Longxing Shi
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Publication number: 20140043092Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.Type: ApplicationFiled: October 22, 2013Publication date: February 13, 2014Applicant: Analog Devices, Inc.Inventor: Ahmed Mohamed Abdelatty ALI
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Publication number: 20140035656Abstract: According to one embodiment, a semiconductor device includes: a first switching element; a first interconnection; a first resistor; and a second interconnection. The first switching element includes a first control terminal, a first electrode terminal, and a first conductor terminal. The second switching element includes a second control terminal, a second electrode terminal, and a second conductor terminal. The first interconnection includes a first through a fourth interterminal interconnections. The first resistor is connected at a first end to the first control terminal. The second resistor is connected at a first end to the second control terminal and is connected at a second end to a second end of the first resistor. The second interconnection is provided between the first electrode terminal and the second electrode terminal and/or between the first control terminal and the second control terminal.Type: ApplicationFiled: March 7, 2013Publication date: February 6, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Kazuto Takao
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Publication number: 20140035657Abstract: In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Applicant: VISHAY-SILICONIXInventor: Trang VU
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Patent number: 8643427Abstract: A switching device includes: a first switching circuit, having a control node coupled to a first control signal, and arranged to selectively couple a signal node to a first amplifying circuit according to the first control signal; and a first control circuit, having a first control node and a second control node coupled to the control node of the first switching circuit and the signal node, respectively, wherein when the first switching circuit is controlled to electrically disconnect the signal node from the first amplifying circuit and a voltage level of the signal node reaches a first predetermined voltage level, the first control circuit is arranged to make the control node of the first switching circuit electrically connected to the signal node.Type: GrantFiled: May 16, 2011Date of Patent: February 4, 2014Assignee: MediaTek Singapore Pte. Ltd.Inventors: Ying-Chow Tan, Osama K A Shana'a
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Patent number: 8638129Abstract: A power circuit. One embodiment provides a circuit for driving a power transistor having a control electrode and a load path. The circuit includes a driver circuit configured to change the power transistor to a completely on or off state with the aid of a control signal supplied to the control electrode. A series circuit includes a semiconductor switching element and a capacitor. The series circuit is connected in parallel with the load path and the capacitor provides a supply voltage for the driver circuit.Type: GrantFiled: August 20, 2008Date of Patent: January 28, 2014Assignee: Infineon Technologies AGInventors: Peter Kanschat, Uwe Jansen, Gerald Deboy
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Patent number: 8633755Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.Type: GrantFiled: November 21, 2011Date of Patent: January 21, 2014Assignee: DENSO CORPORATIONInventors: Teppei Kawamoto, Ryotaro Miura
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Publication number: 20140015593Abstract: An RF switch includes a switchable RF transistor. The switchable RF transistor includes a stripe of a plurality of adjacent RF transistor fingers and at least one non-switchable dummy transistor that is arranged at an end of the stripe of the switchable RF transistor.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Franz Weiss, Hans Taddiken, Nikolay Ilkov, Winfried Bakalski, Jochen Essel, Herbert Kebinger
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Publication number: 20140015592Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.Type: ApplicationFiled: July 11, 2012Publication date: January 16, 2014Applicant: INFINEON TECHNOLOGIES DRESDEN GMBHInventor: Rolf Weis
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Publication number: 20140015594Abstract: The switching cell (1), comprises, between the terminals of a supply source (2) supplying a voltage (VC), a controlled power switch (T) and a current recirculation device (CRD) including a diode or a junction, between which there is defined a common terminal (O) of the cell (1). Across the current recirculation device (CRD) there are connected controlled electric charge supply means (TL, VL, DL; TH, VH, DH) comprising a first generator circuit (TL, VL, DL) for generating a low voltage, including a first d.c. voltage source (VL), an associated first controlled switch (TL), and a first diode (DL), and adapted to supply an electric charge sufficient to cause the reverse-recovery of the current recirculation device (CRD); and a second generator circuit (TH, VH, DH) for generating a higher voltage, including a second d.c.Type: ApplicationFiled: March 14, 2012Publication date: January 16, 2014Applicant: ET99 S.R.L.Inventors: Antonino Fratta, Paolo Guglielmi, Eric Giacomo Armando
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Publication number: 20140011463Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a switch having a stack of field-effect transistors (FETs) connected in series between first and second nodes. A capacitor connected in series with the switch is configured to inhibit a low-frequency blocker signal from mixing with a fundamental-frequency signal in the switch.Type: ApplicationFiled: July 6, 2013Publication date: January 9, 2014Inventors: Anuj Madan, Fikret Altunkilic, Guillaume Alexandre Blin
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Patent number: 8624637Abstract: A circuit for controlling the switching operation of a transistor is described. A gate driver circuit is operably connected to a control electrode of the transistor and is configured to charge and discharge the control electrode to switch the transistor on and off, respectively, in accordance with a control signal. The charging and discharging of the control electrode is done such that the corresponding transitions in the load current and the output voltage are smooth with a defined slope. A controllable switch is connected to the control electrode such that, when the switch closes, the control electrode is quickly discharged via the switch thus quickly switching off the transistor. A control logic circuit is configured to close the controllable switch for switching off the transistor when at least one of a number of conditions holds true.Type: GrantFiled: February 8, 2012Date of Patent: January 7, 2014Assignee: Infineon Technologies AGInventors: Michael Asam, Carmelo Fabio Giunta, Wolfgang Horchler, Markus Winkler
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Publication number: 20140002174Abstract: A method and apparatus for current drain switching with a replica loop. The method comprises the steps of: matching a voltage across a current sense resistor with a voltage created by a reference current across a matched reference resistor; replicating an operating point of an output transistor using a scaled matched replica of the output transistor and the current sense resistor. The method then shifts a feedback voltage from the output sense resistor to the matched replica sensor and shifts the output of a gate from an output transistor to the replica transistor. A first switch is then actuated in order to preserve the gate charge of the output transistor. A second switch is actuated to sample and hold a drain voltage in the buffer in order to bias the drain of the replica transistor. The third switch is then activated to stop the output current.Type: ApplicationFiled: June 27, 2012Publication date: January 2, 2014Applicant: QUALCOMM IncorporatedInventors: Hua Guan, Eric B. Zeisel, Qi Lou
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Publication number: 20140002175Abstract: A resonant clock distribution network architecture is proposed that is capable of single-step operation through the use of selective control in the resonant clock drivers and the deployment of flip-flops that require the clock to remain stable for a sufficiently long time between any two consecutive state updates. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.Type: ApplicationFiled: December 13, 2012Publication date: January 2, 2014Applicant: Cyclos Semiconductor, Inc.Inventor: Cyclos Semiconductor, Inc.
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Publication number: 20130343138Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.Type: ApplicationFiled: August 28, 2013Publication date: December 26, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Dariusz KOWALCZYK
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Patent number: 8610490Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.Type: GrantFiled: March 25, 2013Date of Patent: December 17, 2013Assignee: Micron Technology, Inc.Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
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Patent number: 8610469Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the re-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of thType: GrantFiled: October 18, 2012Date of Patent: December 17, 2013Assignee: THAT CorporationInventor: Gary K. Hebert
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Patent number: 8604865Abstract: A RFID transponder includes an electronic circuit and an antenna, the electronic circuit being integrated in a p-type substrate and comprising a modulator formed by a PMOS transistor whose drain, electrically connected to a pad of the antenna, and source, connected to the ground of the electronic circuit, are arranged in an n-type well provided in the p-type substrate. The PMOS transistor has a gate driven by a driving circuit which is arranged for providing at least a negative voltage, this negative voltage being low enough for turning on this PMOS transistor in response to a control signal provided by a logical unit of the electronic circuit.Type: GrantFiled: May 23, 2012Date of Patent: December 10, 2013Assignee: EM Microelectronic-Marin S.A.Inventors: Nicolas Pillin, David A. Kamp