Insulated Gate Fet (e.g., Mosfet, Etc.) Patents (Class 327/434)
  • Patent number: 8461905
    Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Zentrum Mikroelektronic Dresden AG
    Inventor: Mathias Krauss
  • Patent number: 8461881
    Abstract: Electrically isolating the gate terminals of a pair of semiconductor output devices increases the switching speed of a solid state relay. A time delay enables tuning of the isolated gate circuits facilitating simultaneous operation of the output devices.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: June 11, 2013
    Inventor: Larry A. Park
  • Patent number: 8451046
    Abstract: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: May 28, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Omid Oliaei, David Newman
  • Patent number: 8451045
    Abstract: An inverter control apparatus is provided that offers a ‘soft turn off’ to a gate operation of the inverter so as to securely protect the IGBT. In particular, an inverter control system according to the present invention may include a gate operating portion that controls turn on/off of an IGBT and forcibly turns off the IGBT if a short circuit or an over current is detected from the IGBT, a current buffer that amplifies a control current for the turn on/off of the IGBT that is outputted from the gate operating portion, and a filter that delays the forcible turn off control current that is outputted from the gate operating portion.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 28, 2013
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Jeongbin Yim, Daewoong Han, Gu Bae Kang, Byungsoon Min
  • Publication number: 20130127520
    Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.
    Type: Application
    Filed: November 22, 2011
    Publication date: May 23, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Jie ZHAN, Tsung-Hsin YU
  • Publication number: 20130127519
    Abstract: In one preferred form shown in FIGS. 2a to 2c there is provided a field effect transistor (24). The field effect transistor includes an off switch gate (42) and a switch bridge (44). The switch bridge (44) is provided for charging the off switch gate (42) such that the off switch gate (42) is able to screen the electric field of the control gate (32) of the field effect transistor.
    Type: Application
    Filed: October 3, 2011
    Publication date: May 23, 2013
    Inventor: Dac Thong Bui
  • Publication number: 20130127518
    Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.
    Type: Application
    Filed: September 21, 2012
    Publication date: May 23, 2013
    Applicant: FUJITSU LIMITED
    Inventor: FUJITSU LIMITED
  • Patent number: 8446207
    Abstract: A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off operation of the power MOSFET, the rate of discharging the gate terminal of the power MOSFET performed with the shut-off circuit being set such that the discharge rate provided if the gate voltage Vg is lower than the power-supply voltage Vp is slower than the rate of discharging the same provided if the gate voltage Vg is higher than the power-supply voltage Vp.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: May 21, 2013
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Kazuki Sasaki
  • Patent number: 8446050
    Abstract: A solid-state alternating current (AC) switch provides for the sequential turn-on of the associated solid-state switches to reduce the generation of electromagnetic interference (EMI). The solid-state AC switch includes at least first and second solid-state switches connected in series between an AC input and an AC load. A zero-cross detector circuit monitors the AC input to determine zero-crossings associated with the monitored AC input. A controller turns on the first solid-state switch and the second solid-state switch according to a turn-on sequence in which the first transistor is turned ON during a detected zero-crossing window associated with the first transistor and the second transistor is subsequently turned ON during a detected zero-crossing associated with the second transistor.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 21, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Robert D. Klapatch
  • Patent number: 8441128
    Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: May 14, 2013
    Assignee: Infineon Technologies AG
    Inventor: Daniel Domes
  • Publication number: 20130113526
    Abstract: A control signal generation circuit which generates a control signal for controlling a gate of an MOS transistor, comprises a first switching part connected to a current source and the gate and controlled based on an input signal; and a second switching part connected to the current source and the gate and controlled based on an input signal and control signal, wherein a voltage value of the control signal changes based on the input signal, and a slant of the voltage value with respect to time is switched to become smaller after the voltage value exceeds a threshold voltage of the MOS transistor compared with when the voltage value equals to or less than the threshold voltage of the MOS transistor.
    Type: Application
    Filed: March 28, 2012
    Publication date: May 9, 2013
    Applicant: ASAHI KASEI MICRODEVICES CORPORATION
    Inventors: Daisuke Matsuoka, Ryuzo Yamamoto
  • Publication number: 20130106494
    Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Inventors: Toshinari Takayanagi, Shingo Suzuki
  • Publication number: 20130099850
    Abstract: A voltage switch circuit uses PMOS transistors to withstand high voltage stress. Consequently, the NMOS transistors are not subject to high voltage stress. The lightly-doped PMOS transistors are compatible with a logic circuit manufacturing process. Consequently, the voltage switch circuit may be produced by a logic circuit manufacturing process.
    Type: Application
    Filed: March 19, 2012
    Publication date: April 25, 2013
    Applicant: eMemory Technology Inc.
    Inventors: Chen-Hao Po, Chiun-Chi Shen
  • Publication number: 20130099851
    Abstract: A semiconductor device having strain material is disclosed in a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.
    Type: Application
    Filed: April 17, 2012
    Publication date: April 25, 2013
    Applicant: QUALCOMM Incorporated
    Inventor: Haining Yang
  • Patent number: 8427225
    Abstract: To obtain a gate driving circuit in which rising of a constant current of a constant current circuit is fast and power saving is achieved, the gate driving circuit includes: a constant current driving circuit (28) for supplying a constant current; a gate terminal of a power semiconductor element (1), which is connected to an output terminal of the constant current driving circuit; a comparator (22) for comparing a voltage at the gate terminal with a predetermined voltage value and outputting a signal indicating that the voltage is higher than the predetermined voltage value; and a driving control section (20) for increasing a current from the constant current driving circuit in response to a signal for turning on the power semiconductor element, and reducing the current from the constant current driving circuit in response to the signal from the comparator.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: April 23, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Nakatake, Masaru Fuku, Tatsuya Okuda, Yoshikazu Tsunoda
  • Publication number: 20130093498
    Abstract: A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.
    Type: Application
    Filed: October 14, 2011
    Publication date: April 18, 2013
    Inventors: Boris RESHETNYAK, Dante E. PICCONE, Victor TEMPLE
  • Patent number: 8415987
    Abstract: An on-load tap changer with semiconductor IGBT switching elements for uninterrupted switching over between winding taps of a tapped transformer, has two load branches connectable with the respective winding taps and each load branch is electrically connected with a common load output line through a respective series circuit consisting of two oppositely connected IGBTs. A diode is connected parallel to each IGBT, and the two diodes in each load branch are connected oppositely to one another. A respective mechanical switch is connected in series with the series circuit of IGBTs and parallel diodes in each load branch. A respective varistor is connected parallel to each parallel circuit of IGBT and diode, and the varistors are so dimensioned that the respective varistor voltages are lower than the maximum blocking voltage of the respective parallel IGBTs but higher than the maximum instantaneous value of the tap voltage.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: April 9, 2013
    Assignee: Maschinenfabrik Reinhausen GmbH
    Inventors: Oliver Brueckl, Dieter Dohnal, Hans-Henning Lessmann-Mieske
  • Patent number: 8410840
    Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 2, 2013
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Tero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
  • Patent number: 8410842
    Abstract: A power switch circuit includes a control circuit, and first and second detecting circuits. The control circuit includes first and second field effect transistors (FETs) and first and second sensing resistors. The first detecting circuit includes two input terminals connected to the first and second ends of the first sensing resistor and an output terminal connected to the first FET. The first detecting circuit controls the first FET to be turned on or turned off according to the voltages of the first and second ends of the first sensing resistor. The second detecting circuit includes two input terminals connected to the first and second ends of the second sensing resistor and an output terminal connected to the second FET. The second detecting circuit controls the second FET to be turned on or turned off according to the voltages of the first and second ends of the second sensing resistor.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 2, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Yun Bai, Song-Lin Tong, Peng Chen
  • Patent number: 8405444
    Abstract: Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series coupled transistors with a parallel control transistor where the number of transistors in each group may be determined by an expected switch input voltage and a maximum allowable voltage drop for each transistor. A voltage of a particular state of an enable signal is shifted up to the switch input voltage by the level shift circuits. The particular state of the enable signal turns on the voltage switch such that the switch output voltage is substantially equal to the switch input voltage.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Giulio G. Marotta, Carlo Musilli, Stefano Perugini, Alessandro Torsi, Tommaso Vali
  • Patent number: 8405443
    Abstract: A pass transistor circuit according to an embodiment includes: a first input/output terminal connected to a first signal line; a second input/output terminal connected to a second signal line; a first device having a first terminal connected to a first power supply and a second terminal; a second device having a third terminal connected to the second terminal and a fourth terminal connected to a second power supply; a first transistor having one of source/drain connected to the second terminal, a gate receiving a first control signal; and a second transistor having a gate connected to the other one of source/drain of the first transistor, one of source/drain connected to the first input/output terminal, and the other one of source/drain connected to the second input/output terminal. One of the first and second devices is a nonvolatile memory device, the other one of the first and second devices is a MOSFET.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Tetsufumi Tanamoto, Takao Marukame, Mizue Ishikawa, Tomoaki Inokuchi, Yoshiaki Saito
  • Patent number: 8405445
    Abstract: In a complementary-MOSFET driving circuit for driving the charge multiplication gate of an EM-CCD, a ferrite bead is connected to a conduction-termination direction diode in parallel thereto, the conduction-termination direction diode being inserted into the gate electrodes of complementary MOSFETs in series therewith, the impedance of the ferrite bead at a switching frequency being lower than one-half of the gate-electrode impedance of the MOSFETs, a time during which the MOSFETs are brought into simultaneous conduction being shorter than ¼th of the switching period, the impedance of the ferrite bead at a frequency equivalent to ¼th of the switching period being higher than 2 times the gate-electrode impedance of the MOSFETs, a ferrite bead being connected to the drain electrodes of the complementary MOSFETs in series therewith, the impedance of the ferrite bead at the switching frequency being lower than one-half of the impedance of a capacitive load at the switching frequency, and the impedance of the ferr
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: March 26, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Kazuhiko Nakamura, Yutaka Muto, Kiyotaka Kogo
  • Publication number: 20130069923
    Abstract: To suppress malfunctions in a shift register circuit. A shift register having a plurality of flip-flop circuits is provided. The flip-flop circuit includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, and a transistor 15. When the transistor 13 or the transistor 14 is turned on in a non-selection period, the potential of a node A is set, so that the node A is prevented from entering into a floating state.
    Type: Application
    Filed: November 13, 2012
    Publication date: March 21, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130063116
    Abstract: Devices, systems and methods are provided for a switch to perform true reverse current blocking (TRCB). The device may include a PMOS switch, including a source port, a drain port, a gate port and an n-well region; an input voltage port coupled to the source port; an output voltage port coupled to the drain port; a switch control port coupled to the gate port; and comparator circuitry configured to compare an input voltage at the input voltage port with an output voltage at the output voltage port and select a maximum of the input voltage and the output voltage. The comparator circuitry may be further configured to couple the selected maximum to the n-well region.
    Type: Application
    Filed: July 10, 2012
    Publication date: March 14, 2013
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Ni Sun, Xinkuan Han, Jun Fan
  • Publication number: 20130063200
    Abstract: A CMOS circuit and a semiconductor device having small leakage current and a low threshold voltage, and which is operated at high speed and with a small voltage amplitude, including an output stage circuit having MOSTs configured such that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, and upon deactivation, a voltage is applied to the gate of each of the MOSTs to cause a reverse bias to be applied between the gate and source of the MOST. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 14, 2013
    Inventors: Kiyoo Itoh, Masanao Yamaoka
  • Patent number: 8390339
    Abstract: A semiconductor switch includes: a switch section, provided on a substrate, switching connection states among a plurality of terminals; a positive voltage generator generating a positive potential higher than a supply potential supplied from a power-supply line; a driver, connected to an output line of the positive voltage generator, supplying a control signal to the switch section in response to a terminal switching signal; and a voltage controller, provided on the same substrate, controlling to connect the output line of the positive voltage generator to the power-supply line for a first period corresponding to a change in the connection states, and controlling to disconnect the output line from the power-supply line after the first period.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiki Seshita
  • Patent number: 8378734
    Abstract: A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: February 19, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Yong-Min Ha, Kee-Jong Kim, Byeoung-Koo Kim
  • Patent number: 8378718
    Abstract: A switching circuit for switching a time-varying input signal, the switching circuit comprising: at least one switch including a N-channel MOSFET and a P-channel MOSFET, each having a gate configured to receive a drive signal to change the ON/OFF state of the switch; and a drive circuit configured and arranged so as to selectively apply a pair of drive signals to change the ON/OFF state of the switch, the drive circuit being configured and arranged to generate the drive signals as a function of (a) a pair DC signal components sufficient to change the ON/OFF state of the switch and (b) a pair of time-varying signal components as at least a partial replica of the signal present on the source terminal of each MOSFET so that when applied with the DC signals to the gates of the n-channel MOSFET and p-channel MOSFET respectively, the drive signals will be at the appropriate level to maintain the ON/OFF state of the switch and keep the gate-source voltages of each MOSFET within the gate-source breakdown limit of the
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: February 19, 2013
    Assignee: THAT Corporation
    Inventor: Gary Hebert
  • Publication number: 20130033301
    Abstract: A structure of an output stage, and the structure includes a first electrode, a second electrode, a third electrode, a plurality of first auxiliary electrodes, a plurality of second auxiliary electrodes, a plurality of third auxiliary electrodes, a plurality of fourth auxiliary electrodes, a first switching unit, and a second switching unit. Wherein, a plurality of first currents flow through the turned-on first switching unit, and a first flowing direction of the first currents in the turned-on first switching unit is from the first electrode to the second electrode. A plurality of second currents flow through the turned-on second switching unit, and a second flowing direction of the second currents in the turned-on second switching unit is from the second electrode to the third electrode.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 7, 2013
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventor: Wei-Kai Tseng
  • Publication number: 20130033302
    Abstract: A switch may include a MOS transistor alternatively operating in an ON phase and an OFF phase, a first voltage level shifter, and a second voltage level shifter. The MOS transistor may include a source for receiving an input signal, a drain for connecting to a load, and a gate. The first voltage level shifter may be selectively coupled between the source and the gate during the ON phase, and the second voltage level shifter may be selectively coupled between the gate and the source during the OFF phase.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: Analog Devices, Inc.
    Inventor: Ahmed Mohamed Abdelatty ALI
  • Patent number: 8368453
    Abstract: A switch can be implemented by a switch circuit, which can include a pair of NMOS transistors connected in series as pass-through transistors to transmit an input signal at an input terminal to produce an output signal at output terminal in response to an active state of a switching signal, and a pair of PMOS transistors connected in series as pass-through transistors to transmit the input signal at the input terminal to produce the output signal at output terminal in response to the active state of the switching signal. The switch circuit can also include a switch network connecting, in response to the active state of the switching signal, sources to bodies of the pairs of NMOS and PMOS transistors, and connecting, in response to an inactive state of the switching signal, the bodies of the pair of NMOS transistors to a first reference voltage, the bodies of the pair of PMOS transistors to a second reference voltage, and the sources of the pairs of NMOS and PMOS transistors to a third reference voltage.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 5, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Enrique Company Bosch, John Anthony Cleary
  • Publication number: 20130026829
    Abstract: An electronic circuit includes an electronic switch with a control terminal and a load path between a first and a second load terminal, and a drive circuit with an output terminal coupled to the control terminal of the electronic switch. The drive circuit includes a first input terminal and a second input terminal, a first drive unit coupled between the first input terminal and the output terminal and including a charge pump and drive unit, and a second drive unit coupled between the second input terminal and the output terminal and including a further electronic switch coupled between the output terminal and a terminal for a reference potential.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Veli Kartal
  • Publication number: 20130015905
    Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 17, 2013
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventor: Michael A. Briere
  • Patent number: 8350840
    Abstract: A switching circuit and a DC-DC converter including the same are provided. The switching circuit includes an output terminal, a plurality of input terminals, and a plurality of switches configured to selectively connect the plurality of input terminals to the output terminal. The plurality of switches include a first switch directly connected to the output terminal and a plurality of second switches connecting the plurality of input terminals to the first switch. The first switch is implemented using a high-voltage transistor. Each of the second switches is implemented using a low-voltage transistor. A gate of the high-voltage transistor is at least two times longer than a gate of the low-voltage transistor. The DC-DC converter increases or decreases a signal selected from among a plurality of input signals input through the input terminals by a predetermined voltage level.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Jin Kim, Jae Sung Kang, Si Woo Kim, Jong-Hyun Kim
  • Publication number: 20130002340
    Abstract: A stage circuit is capable of concurrently or progressively supplying scan signals. The stage circuit includes a progressive driver including a first transistor and a second transistor, and a concurrent driver including an 11th transistor and a 12th transistor. When the first transistor, the second transistor, the 11th transistor, and the 12th transistor are turned off, lower voltages than voltages applied to source electrodes are applied to gate electrodes such that the transistors can be stably turned off.
    Type: Application
    Filed: October 11, 2011
    Publication date: January 3, 2013
    Inventors: Bo-Yong Chung, Deok-Young Choi, Yong-Jae Kim
  • Publication number: 20130005279
    Abstract: According to one embodiment, a semiconductor switch includes a switch section, a driver, and a power supply. The switch section switches a connection between a common terminal and a plurality of radio-frequency terminals. The driver outputs a control signal to the switch section based on a terminal switching signal. The power supply generates a first potential based on a reference potential varying in accordance with temperature and outputs the first potential to the driver.
    Type: Application
    Filed: March 16, 2012
    Publication date: January 3, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshifumi ISHIMORI, Toshiki Seshita
  • Publication number: 20130002204
    Abstract: A signal transmitting-receiving circuit includes a first circuit including a first MOS transistor having a gate and a drain, a second MOS transistor having a gate and a drain connected to the gate and drain of the first MOS transistor, and a source connected to ground, and a transmitting terminal transmitting a signal connected to the drains of the first and second MOS transistors; and a second circuit including a receiving terminal receiving the signal transmitted from the transmitting terminal of the first circuit connected to the transmitting terminal, a third MOS transistor having a gate connected to the receiving terminal, a drain connected to a reference voltage generator circuit and a source connected to ground, a resistor connected between the third MOS transistor and the reference voltage generator circuit, and an output terminal connected between the resistor and the third MOS transistor.
    Type: Application
    Filed: March 14, 2011
    Publication date: January 3, 2013
    Inventor: Masashi Oshima
  • Patent number: 8344788
    Abstract: The semiconductor device includes a power element which is in an on state when voltage is not applied to a gate, a switching field-effect transistor for applying first voltage to the gate of the power element, and a switching field-effect transistor for applying voltage lower than the first voltage to the gate of the power element. The switching field-effect transistors have small off-state current.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 8339181
    Abstract: A low-side driver circuit includes a low-side driver integrated circuit and a controllable switch. The low-side driver integrated circuit is responsive to an on-off command input signal to selectively operate in an ON mode and an OFF mode. The controllable switch is responsive to the on-off command signal to selectively operate in a CLOSED mode and an OPEN mode. The low-side driver integrated circuit and the controllable switch are configured to simultaneously operate in the ON mode and the CLOSED mode, respectively, and in the OFF mode and the OPEN mode, respectively. During a voltage transient the potential will be realized across the controllable switch, thus protecting the lower voltage rated low-side integrated circuit.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: December 25, 2012
    Assignee: Honeywell International Inc.
    Inventors: Alex Wedin, Dale Trumbo, Paul Stevens
  • Patent number: 8339180
    Abstract: Disclosed are an apparatus and a method for switching RF signals. An RF switching apparatus according to an exemplary embodiment of the present invention includes: a plurality of FETs passing or blocking high-frequency signals depending on driving voltage applied to a gate; a control power supply generating control voltage for controlling the passing or blocking of the high-frequency signals; and a charge pump increasing the level of the control voltage and outputting the corresponding voltage as the driving voltage. According to the exemplary embodiment of the present invention, it is possible to minimize insertion loss generated in an RF switch.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: December 25, 2012
    Assignee: Gwangju Institute of Science and Technology
    Inventor: Jong Soo Lee
  • Publication number: 20120319737
    Abstract: Disclosed herein are an inverter and an antenna circuit. The inverter that receives control signals, inverts the control signals including a first control signal, a second control signal, and a third control signal, and outputs the inverted control signals, includes: a first MOS transistor having a gate to which a first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which a third control signal is applied and a source to which a second control signal is applied; and a third MOS transistor having a gate to which a second control signal is applied and a source to which a third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 20, 2012
    Inventors: Yu Sin Kim, Sang Hee Kim, Dong Hyun Baek, Sun Woo Yun, Sung Hwan Park
  • Publication number: 20120313689
    Abstract: A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD1, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.
    Type: Application
    Filed: June 28, 2012
    Publication date: December 13, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Valeria Bottarel, Giulio Ricotti, Silvia Marabelli
  • Patent number: 8330524
    Abstract: A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
  • Publication number: 20120306562
    Abstract: This disclosure provides novel latching circuits, and pixel circuits and display devices that include such latching circuits. The latches herein include a switch positioned on an inverter coupling interconnect which couples two cross-coupled inverters of the latch. The switch is configured to control a passage of a current between the first and second inverters. By switching the switch OFF at a time a data voltage is transferred to the inverters, any leak current between the inverters can be interrupted. As a result, a malfunctioning of the data latch is prevented.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Inventors: Mitsuhide Miyamoto, Katsumi Matsumoto, Takahide Kuranaga
  • Publication number: 20120306464
    Abstract: Disclosed is a circuit arrangement, including a transistor component with a gate terminal, a control terminal, and a load path between a source and a drain terminal, and a drive circuit connected to the control terminal and configured to determine a load condition of the transistor component, to provide a drive potential to the control terminal, and to adjust the drive potential dependent on the load condition.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz HIRLER, Martin FELDTKELLER, Gerald DEBOY
  • Publication number: 20120306561
    Abstract: An I/O circuit includes: a boost module, a P path, an N path, a PMOS driving transistor, and an NMOS driving transistor, where: a rising edge of an output signal of a non-inverting port of the boost module is slower than a falling edge; a grid electrode of the PMOS driving transistor is connected to the non-inverting port of the boost module via the P path and a grid electrode of the NMOS driving transistor is connected to an inverting port of the boost module via the N path; and the P path includes an odd number of inverters connected in series and the N path includes an even number of inverters connected in series. The present invention also provides an integrated circuit.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wei CAO, Fangming DAI
  • Publication number: 20120306563
    Abstract: A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 6, 2012
    Applicants: National University Corporation TOYOHASHI UNIVERSITY OF TECHNOLOGY, Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro FUJIKAWA, Nobuo Shiga, Takashi Ohira, Kazuyuki Wada, Kazuya Ishioka, Hiroshi Ishioka
  • Patent number: 8324957
    Abstract: A current source is switchable between two precisely defined output currents. A terminal of a coupling capacitor is coupled to the gate of an output MOSFET. The other terminal of the capacitor is switched between two reference voltages to toggle the output MOSFET to output the selected one of the two currents. A switchable bias voltage source is coupled to the gate only during the on state of the output MOSFET to set the gate voltage of the output MOSFET. The current output of the current source is quickly and accurately changed. A reference MOSFET is not directly coupled to the output MOSFET, so there are no slow settling components coupled to the gate of the output MOSFET.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: December 4, 2012
    Assignee: Linear Technology Corporation
    Inventors: David Thomas, Richard Reay
  • Publication number: 20120299636
    Abstract: A functional circuit is coupled to a power supply conductor by at least one power gating transistor. A switching device applies a gate drive voltage to a gate terminal of the power gating transistor via a resistive element. The power gating transistor provides a Miller capacitance between its drain and gate terminals. The Miller capacitance, the resistance of the resistive element, and the drive strength of the switching device are configured such that, in response to the switching device switching the gate drive voltage to allow more current to pass through the power gating transistor, the Miller capacitance provides a feedback mechanism competing against the switching device to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and the functional circuit through the power gating transistor is less than the saturation current of the power gating transistor.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: ARM LIMITED
    Inventors: Nicolaas Klarinus Johannes Van Winkelhoff, Mikael Brun
  • Publication number: 20120286845
    Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.
    Type: Application
    Filed: May 13, 2011
    Publication date: November 15, 2012
    Inventor: James Joseph Morra