Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

Abstract: A gate driving circuit for driving a voltage-driven switching device is provided with a current limiting circuit for limiting a gate current ig that flows into a gate terminal through a gate resistor at turn-on to a current limit value IL which defines an upper limit value. The current limit value IL is set at a value which is larger than a gate current value I2 at turn-on of the switching device during a period when the Miller effect occurs but is smaller than a gate current value I1 at a point in time when a main current begins to flow at turn-on in a case where the gate current ig is not limited by the current limiting circuit. This arrangement makes a variation in a collector current of the switching device moderate at turn-on thereof when the collector current begins to flow, thereby reducing high-frequency noise.

Abstract: A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.

Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

Abstract: A reference voltage generator includes a first transistor and a second transistor coupled in series between a current supply and ground. Gate insulating films of the first transistor and the second transistor are made of the same type of film with the same thickness. Impurities contained in gate electrodes of the first transistor and the second transistor have different conductivity types, or have the same conductivity type and different concentrations. The first transistor has a greater gate width than the second transistor. The first transistor and the second transistor operate in a subthreshold region when a reference voltage is output outside.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: There is provided a high frequency switching circuit reducing power consumption at the time of signal reception and signal transmission. The high frequency switching circuit includes a pulse generation unit generating a clock selecting pulse signal having a predetermined active period; a clock selection unit selecting a reference clock signal when the clock selecting pulse signal is in an active state and selecting a low-speed clock signal having a frequency lower than that of the reference clock signal when the clock selecting pulse signal is not in an active state; a voltage down unit accumulating negative charges in a capacitor to generate predetermined negative voltage; and a switching unit including at least one switch holding a turned-off state by being applied with the predetermined negative voltage.

Abstract: A gate driver for driving a gate of a switching element Tr7 includes a driving part that drives the switching element according to a control signal and an active clamp circuit to clamp the voltage between the first and second main terminals of the switching element through the driving part. If a voltage applied between a first main terminal (drain) and a second main terminal (source) of the switching element exceeds a predetermined voltage, the active clamp circuit forcibly blocks a driving operation of the driving part from driving the switching element.

Abstract: A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power.

Abstract: The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal.

Abstract: A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal.

Abstract: Disclosed herein is a resistor-sharing switching circuit including: a first switching device and a second switching device; and a resistor whose first end is connected to a control signal input end to which a control signal for controlling bodies of the first switching device and the second switching device is applied and whose second end is connected to the bodies of the first switching device and the second switching device.

Abstract: A circuit for controlling a connector to transmit data according to Low Pin Count (LPC) protocol or Joint Test Action Group (JTAG) protocol includes a switch unit, first and second electronic switches, and first and second switch chips. When the switch unit outputs a high level signal to the first electronic switch, the connector transmits data according to LPC protocol. When the switch unit outputs a low level signal to the first electronic switch, the connector transmits data according to JTAG protocol.

Abstract: A solid-state relay is provided, which includes a first transistor, a second transistor, a first transmission circuit, and a second transmission circuit. A gate of the first transistor is connected to one of a source and a drain of the second transistor, one of a source and a drain of the first transistor is connected to a first terminal, and the other of the source and the drain of the first transistor is connected to a second terminal. The first transmission circuit supplies a first signal to the gate of the first transistor. The second transmission circuit supplies a second signal to a gate of the second transistor. The first terminal is connected to the second terminal when the first transistor is turned on by the first signal.

Abstract: An aspect of the present embodiment, there is provided a semiconductor integrated circuit, including a first transistor configured to switch whether or not a first node electrically connects to a second node, and a switch control circuit configured to supply higher potential to a substrate potential of the first transistor in a state of turning of the first transistor, when at least one of potentials of the first node and the second node is equal to or higher than a predetermined potential which is higher than a potential of a power supply.

Abstract: A low voltage isolation switch is suitable for receiving from a connection node a high voltage signal and transmitting said high voltage signal to a load via a connection terminal. The isolation switch includes a driving block connected between first and second voltage reference terminals and including a first driving transistor coupled between the first voltage reference (Vss) and a first driving circuit node and a second driving transistor coupled between the driving circuit node and the second supply voltage reference. The switch comprises an isolation block connected to the connection terminal (pzt), the connection node, and the driving central circuit node and including a voltage limiter block, a diode block and a control transistor. The control transistor is connected across the diode block between the connection node and the connection terminal and has a control terminal connected to the driving central circuit node.

Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.

Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.

Abstract: Embodiments of a circuit, which includes a device and a switch, which is electrically coupled to the device, to control power applied to the device, are described. This switch includes a control terminal, which controls the switch, and two other terminals, which can receive power to be applied to the device. Moreover, the circuit is configured to apply a voltage to the control terminal to ensure the switch remains open when a supply voltage is applied to one of the two other terminals while powering-up the circuit, thereby preventing spurious application of the supply voltage to the device.

Abstract: An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.

Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.

Abstract: A resonant gate drive circuit for a power switching device, having a gate-emitter capacitance, is adapted for use with a high frequency power converter. The resonant gate drive circuit comprises a signal input source, a power supply and a resonant inductor. An electrical isolator is connected between the signal input source and a switching node. The electrical isolator is connected to the power supply. A first bidirectional switch is connected between the resonant inductor and the power switching device and includes a first switch control circuit connected to the node to be controlled by a signal from the signal input source. A second bidirectional switch is connected between the power supply and the power switching device and includes a second switch control circuit connected to the node to be controlled by the signal from the input source.

Abstract: A semiconductor device includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.

Abstract: A method for switching between first and second voltages is provided. Initially, a first voltage is provided from a first input terminal to an output terminal through a first MOS transistor, and the first MOS transistor is deactivated. A back-gate of a second MOS transistor is shorted to the output terminal in response to the deactivation of the first MOS transistor and after a settling interval, and the second MOS transistor is activated while its back-gate is shorted to the terminal so as to provide a second voltage from a second input terminal to the output terminal.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: A LIN network comprises a transmit driver and a receive comparator for communicating low frequency signals on a single communication bus. The transmit driver is operably coupled to a high frequency detector to detect a high frequency component on the low frequency signal. In response to detecting the high frequency component the LIN network is arranged to perform one or both of the following: route the low frequency signal having a high frequency component through a low pass filter; and/or bypass the low frequency signal having a high frequency component from passing through an active device operably coupled between the transmit driver and the single communication bus.

Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.

Abstract: A switch circuit is described, where a switch to be controlled is formed of two NMOS transistors having their source terminals connected together and their gate terminals connected together. Their drain terminals are the input and output terminals of the switch. A driver circuit controls a bootstrap circuit that is formed of a latching circuit and a capacitor. When the switch is in an off state, the driver circuit connects the capacitor to a charging voltage source for charging the capacitor to a bootstrap voltage, and applies a non-zero voltage across the latching circuit. When the driver circuit is controlled to turn on the switch, the driver circuit disconnects the capacitor from the charging voltage source, and the latching circuit becomes conductive and effectively connects the capacitor across the gate and source terminals of the switch to turn it on with the bootstrap voltage. The bootstrap voltage across the capacitor maintains the latching circuit in a latched conductive state.

Abstract: This document discusses, among other things, apparatus and methods for passing a signal in a power down state. An example switch device can include a first depletion-mode transistor configured to pass an analog signal between a first node and a second node in a first state and to isolate the first node from the second node in a second state, a control circuit coupled to a control node of the first depletion-mode transistor and configured to isolate the control node from a first supply input in the first state and to couple the control node to the first supply input in the second state, and a tracking circuit configured to couple the control node of the first depletion-mode transistor to the first node during the first state and to isolate the control node of the first depletion-mode transistor from the first node in the second state.

Abstract: A cascode switch includes a first power transistor configured to be coupled to a load and a second power transistor coupled in series with the first power transistor so that the second power transistor is between ground and the first power transistor. The second power transistor is operable to switch on and off responsive to a pulse source coupled to a gate of the second power transistor. The first power transistor is operable to switch on and off responsive to the same pulse source as the second power transistor or a DC source coupled to a gate of the first power transistor. Alternatively or in addition, a transistor device is coupled to the gate of the first power transistor and operable to actively turn off the first power transistor independent of the load current.

Abstract: Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal.

Abstract: When there is a short circuit failure between the gate and emitter of a main switching element such as an IGBT, the temperature of a turn-on gate resistor or turn-off gate resistor is detected by a thermistor, and a drive circuit is protected by turning off a turn-on gate drive switching element or a turn-off gate drive switching element. Furthermore, instead of detecting the temperature of the turn-on gate resistor or turn-off gate resistor, a thermistor is connected in series with the turn-on gate drive switching element or turn-off gate drive switching element, the resistance change corresponding to a change in temperature of the thermistor is detected, and the drive circuit is protected by turning off the turn-on gate drive switching element or turn-off gate drive switching element.

Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Abstract: There is provided a high frequency semiconductor switch having an FET designed in consideration of characteristics required for a transmission terminal and a reception terminal. The high frequency semiconductor switch includes a plurality of field effect transistors that each include a source region and a drain region formed on a substrate to be spaced apart by a predetermined distance, a gate formed on the substrate to be disposed at the predetermined distance, a source contact formed on the substrate to be connected with the source region, and a drain contact formed on the substrate to be connected with the drain region. A distance between a source contact and a drain contact of a reception terminal side transistor is longer than a distance between a source contact and a drain contact of a transmission terminal side transistor.

Abstract: A single pole double throw (SPDT) semiconductor switch includes a series connection of a first transmitter-side transistor and a first reception-side transistor between a transmitter node and a reception node. Each of the two first transistors is provided with a gate-side variable impedance circuit, which provides a variable impedance connection between a complementary pair of gate control signals. Further, the body of each first transistor can be connected to a body bias control signal through a body-side variable impedance circuit. In addition, the transmitter node is connected to electrical ground through a second transmitter-side transistor, and the reception node is connected to electrical ground through a second reception-side transistor. Each of the second transistors can have a body bias that is tied to the body bias control signals for the first transistors so that switched-off transistors provide enhanced electrical isolation.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A method for reducing an off-current of a field effect transistor in which two electrodes of the field effect transistor have fixed voltage values and the rest electrode has an alternating voltage value by an AC voltage pulse generator to form an off-stress near source and drain junctions in turn.

Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC).

Abstract: The invention provides a switching circuit of a power semiconductor device having connected in parallel SiC diodes with a small recovery current, capable of significantly reducing turn-on loss and recovery loss without increasing the noise in the MHz band, and contributing to reducing the loss and noise of inverters. The present invention provides a switching circuit and an inverter circuit of a power semiconductor device comprising a module combining Si-IGBT and SiC diodes, wherein an on-gate resistance is set smaller than an off-gate resistance.

Abstract: A method of differential signal transfer from a differential input Vinp and Vinn having a common mode input voltage that can be higher than the power supply voltage by providing an input chopper having Vinp and Vinn as a differential input, providing an output chopper, capacitively coupling a differential output Voutp and Voutn of the input chopper to a differential input of the output chopper, capacitively coupling a clock to the input chopper and coupling the clock to the output chopper, the clock having a first phase and a second phase opposite from the first phase, the first phase being coupled to the gates of the first and second transistors and the second phase being coupled to the gates of the third and fourth transistors, and providing protection of the gates of the first through fourth transistors from excessive voltages. Various embodiments are disclosed.

Abstract: Electrically isolating the gate terminals of a pair of semiconductor output devices increases the switching speed of a solid state relay. A time delay enables tuning of the isolated gate circuits facilitating simultaneous operation of the output devices.

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract: In accordance with embodiments of the present disclosure, a circuit may include a transmission switch and a dummy switch coupled at its output to the output of the transmission switch. The transmission switch may be configured to be selectively enabled and disabled based on a control signal received at a gate of the transmission switch. The transmission switch may be further configured to receive a first polarity of a differential signal at its input and pass the first polarity of the differential signal to its output when enabled. The dummy switch may be configured to be disabled and to receive a second polarity of the differential signal at its input, the second polarity of opposite polarity of the first polarity.

Abstract: An inverter control apparatus is provided that offers a ‘soft turn off’ to a gate operation of the inverter so as to securely protect the IGBT. In particular, an inverter control system according to the present invention may include a gate operating portion that controls turn on/off of an IGBT and forcibly turns off the IGBT if a short circuit or an over current is detected from the IGBT, a current buffer that amplifies a control current for the turn on/off of the IGBT that is outputted from the gate operating portion, and a filter that delays the forcible turn off control current that is outputted from the gate operating portion.

Abstract: A control circuit includes: a first switching element having a source, a gate, and a drain; a battery configured to supply a voltage to the gate through a second switching element; a PWM signal generator circuit configured to supply a PWM signal to the gate through a third switching element; and a gate control circuit configured to, under a power-off condition, turn on the second switching element to supply the voltage of the battery to the gate and turns off the third switching element, and configured to under a power-on condition, turn on the third switching element to supply the PWM signal voltage to the gate and turns off the second switching element.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.