Abstract: A normally closed solid state power relay with an optionally optically coupled input circuit at an input terminal with a driver circuit electrically coupled to input terminal to drive one or more a power transistors, preferably MOSFET transistors so that the power transistor is held in the on state by the driver when no voltage or a low level voltage is applied to the input terminal, and the power transistor is held in the off state by the driver when a high level voltage is applied to the input terminal. An energy storage device, a battery or capacitor, is coupled to the driver to powers the driver with the energy storage device being charged by energy from the input terminal when said input terminal when a high level voltage is applied to the input terminal. The energy storage device is charged by leakage current through a diode or through a resistor from the input circuit when the input circuit is in a high state.

Abstract: An analog signal is input to an input terminal. An analog signal is output via an output terminal. A first transistor is an N-channel MOSFET, and is provided between the input terminal and the output terminal. A first resistor is provided between the gate of the first transistor and a first fixed voltage terminal (power supply terminal), which sets the gate of the first transistor to a high-impedance state.

Abstract: A switching circuit arrangement (100) comprises a field effect transistor (40) and circuitry (50, 52, 54, 60, 62) for biasing the gate voltage of the field effect transistor (40), in particular forcing the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level. In embodiments, reverse recovery as well as gate bounce are simultaneously mitigated. In one embodiment, the biasing circuitry comprises a biasing diode (52) connected in series to the gate (G) of the field effect transistor (40) to bias the gate voltage of the field effect transistor (40), as well as a clamping field effect transistor unit (62) connected between the gate (G) of the field effect transistor (40) and the source (S) of the field effect transistor (40) to force the gate voltage of the field effect transistor (40) under a certain threshold, in particular under a certain positive threshold level.

Abstract: A driver apparatus and method for driving a voltage driven type switching element that discharge an electrical charge stored at the gate terminal of the voltage driven type switching element at a discharge rate. The discharge rate is controlled so that the change rate over time of the voltage between the collector and emitter terminals of the voltage driven type switching element is limited to a second change rate during the turn-off operation. The starting time of the control of the change rate over time to attain the second change rate is delayed for a predetermined delay time after start of the turn-off operation and before a time when the voltage between the collector and emitter terminals first reaches the power source voltage level. During the delay time, the discharge rate is initially at a first change rate higher than the second change rate.

Abstract: A switching circuit for preventing malfunction of a switching device formed of a wide band-gap semiconductor used for switching a high-power main power supply includes a normally-off type FET having a gate electrode, a source electrode connected to the ground, and a drain electrode connected to a power supply potential Vdd, and a normally-on type FET having drain and source electrodes connected to the gate and source electrodes of the FET, respectively, and a gate electrode. In the absence of any power supply, the normally-on type FET turns on. As a result, the gate/source potential of FET attains to 0V, and FET is kept off.

Abstract: A circuit configuration includes an output stage having at least one inductive load and a switching transistor configuration for switching the at least one inductive load. A supply voltage has a first supply potential and a second supply potential for feeding the supply voltage to the output stage. A registering device registers a particular instance when a potential at a specific circuit node of the output stage is outside a potential range defined by the first and second supply potentials.

Abstract: A transistor cell includes a first stage comprising a first transistor that is coupled to a RC filter arrangement. A second stage has a second transistor that is coupled to the first stage. The linearity of the transistor cell is improved by shifting the DC bias point so that the first stage is biased at a high quiescent current while the second stage is biased at a low quiescent current.

Abstract: A semiconductor device includes an input terminal, a first aging device whose source is connected to the input terminal to turn on at ?1 and turn off at ?2 (>?1), a second aging device whose source is connected to the input terminal, whose gate is connected to the drain of the first aging device, and whose drain is connected to the gate of the first aging device to turn on at ?3 and turn off at ?4 (>?3), a first switch whose one terminal is connected to the drain of the first aging device to turn off when the second aging device is on, a second switch whose one terminal is connected to the drain of the second aging device to turn off when the first aging device is on, and an output terminal connected to the other terminals of the first and second switch elements.

Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.

Abstract: An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl), a power supply terminal (VSS), an output terminal (OUT) for providing the driving signal (U0) that is coupled to the second main terminal, and a sensing resistor (Rm) coupled between the power supply terminal (VSS) and the first main terminal. The output driver (DRV) further has means for temporarily disabling the coupling between the control terminal and the control signal (Vcntrl) during a peak voltage across the sensing resistor (Rm). The means may have a circuit that has a unidirectional current behavior, such as a diode (D), in series with the control terminal of the transistor (T).

Abstract: A circuit includes a transistor having a source, drain, a gate, and an electrode structure. A source terminal is coupled to the source. A drain terminal coupled to the drain. Terminals are coupled to the gate and to the electrode structure. A switch is coupled to the source, the gate terminal and the electrode terminal to selectively couple one of the gate and electrode structure to the source. In further embodiments, a second switch is used to selectively couple a resistor between the gate and the source. A method is used to control the switches to keep the transistor in an off state or allow it to switch to an on state.

Abstract: A driving device 10 of an IGBT 1 comprises a high potential side switch device group having a plurality of switch devices M1 and M1?, one of ends of each switch device being connected to a high potential side; a low potential side switch device group having a plurality of switch devices M2 and M2?, one of ends of each switch device being connected to a low potential side; an drive type selective input terminal 10b to which a drive type selection signal corresponding to drive type of the IGBT 1 connected to the driving device 10 is inputted; a direct drive type control unit 23 and an indirect drive type control unit 24 generating a control signal controlling complementarily the high potential side switch device group and the low potential side switch device group corresponding to the drive type of the IGBT 1; and a selector 25 selecting the control signal controlling the high potential side switch device group and the low potential side switch device group corresponding to an inputted drive type selection sign

Abstract: A power insulated gate field effect transistor has main cells (2) controlled by a main cell insulated gate and sense cells (4) controlled by a sense cell insulated gate. A sample and hold circuit (10,50) is arranged to operate in a plurality of states including at least one sample state and a hold state to sense the current flowing through the sense cells (4) when in the at least one sample state but not in the hold state. The sample states may be used in a feedback loop to control a drive amplifier (20) driving the gates of the main and sense cells (2,4) and/or to mirror the current in the sense cells (4) on a measurement output terminal (58).

Abstract: A radiation tolerant high-power DC/DC converter is disclosed. The converter does not incorporate radiation-hardened parts, but instead uses p-channel FET switches that have a negative gate threshold voltage. With exposure to radiation, the gate threshold voltage decreases, becoming more negative. Thus, the gate is still controllable.

Abstract: A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An active pull up configuration for data bus lines unaffected by integral pull up resistors within subsystems. The present application generally relates to digital systems comprising a plurality of power supply levels and data buses. More particularly, this invention relates to digital system comprising subsystems connected by common buses that require automatic charging of certain buses or lines.

Abstract: This invention relates to a resonant gate drive circuit for a power switching device, such as a MOSFET, that uses a center-tapped transformer to increase the driving gate voltage approximately twice as high as the supply voltage. The gate capacitance of the power switching device is charged and discharged by a constant current source, which increases the switching transition speed of the power switch. The circuit is suitable for driving a pair of low side switches with 50% duty cycle or less, such as in a variable frequency resonant converter, push-pull converter, or the like.

Abstract: An active load including a current source, a first resistive element, and a switch. The current source is configured to provide a bias current and the first resistive element is configured to receive the bias current and provide a bias voltage. The switch has an input and an output and is configured to receive a drive voltage at the input, receive the bias voltage between the input and the output, provide an output voltage at the output that is sufficiently different than the drive voltage to maintain headroom, and provide an inductive impedance that enhances circuit bandwidth.

Abstract: A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor.

Abstract: On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.

Abstract: A power semiconductor device is described with a plurality of cells divided into power cells (14) and sense cells (16). A plurality of groups (30, 32) of sense cells (16) are provided. The device allows for compensation of effects caused at the edges of the groups of sense cells (16).

Abstract: A switch control circuit includes a N-channel MOSFET, a first bleeder unit, a P-channel MOSFET and a second bleeder unit. The N-channel MOSFET has a first input terminal, a first output terminal and a first control terminal. The first output terminal is connected to ground. The first bleeder unit has a voltage-dividing function to the voltage from an input and output interface of a computer. The first bleeder unit is connected with the first control terminal and the first output terminal of the N-channel MOSFET. The P-channel MOSFET has a second input terminal, a second output terminal and a second control terminal. The second output terminal is connected to the working voltage terminal of the external hard disk. The second bleeder unit is connected between the external power supply and the first input terminal of the N-channel MOSFET. The P-channel MOSFET is connected with the first bleeder unit.

Abstract: A switching device for bi-directionally equalizing charge between energy accumulators, particularly between capacitive energy accumulators in a motor vehicle electric system, includes: an integrated starter generator; a first connection coupled to the integrated starter generator; a second connection coupled to an energy source; a controllable transfer gate having a first load current-conducting path connected between the first and second connection, and a controllable switching controller having a second load current-conducting path connected between the first and second connection in parallel to the first load current-conducting path. There is also provided a motor vehicle electric system with such a switching device, and the implementation and use of a switching controller in a transfer gate for such a switching device.

Abstract: An open drain driver (7) selectively switches a MOSFET switch (MN1) which is passively held in the conducting state into the non-conducting state. The MOSFET switch (MN1) switches an AC analogue input signal on a main input terminal (3) to a main output terminal (4) and the gate of the MOSFET switch (MN1) is AC coupled by a capacitor (C1) to the drain thereof. The open drain driver (7) comprises a first MOSFET (MN2) and a second MOSFET (MN3) through which the gate of the MOSFET switch (MN1) is pulled to ground (Vss). The gate of the first MOSFET (MN2) is coupled to the supply voltage (VDD) for maintaining the first MOSFET (MN2) in the open state. A control signal is applied to the gate of the second MOSFET (MN3) for selectively operating the open drain driver (7) in the conducting state for operating the MOSFET switch (MN1) in the non-conducting state.

Abstract: A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter.

Abstract: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.

Abstract: A challenge in outputting a voltage near the midpoint potential in a semiconductor switch which operates based on a low voltage power supply is to avoid a decrease in operation speed and a deterioration in accuracy of the output voltage which would be caused due to an increase in ON-resistance or occurrence of current leakage. Thus, a structure including a gray level generation circuit, an analog switch circuit and a backgate voltage control circuit is provided wherein the backgate voltage of each of an N-channel MOS transistor and a P-channel MOS transistor of the analog switch circuit to which the voltage of the gray level generation circuit is input is supplied from the backgate voltage control circuit which has an equal structure as that of the gray level generation circuit.

Abstract: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit.

Abstract: A control circuit for P-type power transistor. The P-type power transistor includes a gate coupled between an input voltage and an output voltage. A first switch is coupled between a first voltage and the gate. A current source provides a first current, and is coupled to a second voltage. A second switch is coupled between the first switch, the gate and the current source. The voltage level of the gate is determined according to the first current when the first switch is turned off and the second switch is turned on.

Abstract: A control voltage for a synchronous rectifying transistor is generated with the desired anticipation time. The anticipation time is continuously controlled with a closed-loop technique by comparing it with the duration of a reference pulse. The resulting error signal is processed and provides the necessary correction to the MOSFET gate signal to equalize the actual anticipation time to the duration of the reference pulse.

Abstract: An integrated semiconductor circuit is provided with a connection node, which is provided for decoupling electric signals, and with a plurality of electric signal lines, which are formed to provide in-circuit signals, particularly test signals, to the connection node. An in-circuit release device, which can be switched between a release state to release the signal line and a blocking state to block the signal line, is looped in the signal lines. The release device has switching means, which are formed in such a way that the blocking state for the signal line is assured irrespective of a signal or test signal electric potential applied to the signal line. The release device furthermore, has control means, which are provided for controlling the switching means. The control means can be formed in such a way that a cross-current-free release of the specific signal line is assured.

Abstract: The present invention provides a driving circuit. It includes a plurality of current mirrors to generate a first charge current and a second charge current in response to a reference current. A switch circuit generates a driving signal in response to an input signal. A driving switch is coupled between the first charge current and the switch circuit. Once the driving switch is turned on and the level of the input signal is in high level, the switch circuit generates the driving signal, the level of the driving signal-being in high level, in response to the first charge current and the second charge current. A detection circuit generates a control signal to turn on/off the driving switch. The detection circuit turns off the driving switch to disable the first charge current after a period of delay time when the level of the driving signal is in high level.

Abstract: An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the second transistor. The drain of the first transistor is thus connected to the supply voltage. A first current mirror generates a current sense output. A second current mirror generates an internal current to detect an over current fault condition. The transistors in the current mirrors are connected like the switch transistors. A high voltage operational amplifier and a transistor are used as feedback to insure that the voltage at the output of the current mirrors matches the voltage at the output of the switch. This ensures that the current mirrors generate scaled versions of the current flowing through the switch.

Abstract: The invention relates to a gate control device 10 of a power semiconductor component 11 of the IGBT type. A ramp generator circuit 20 delivers a reference gate voltage at its output. A stage for the current amplification of the said reference voltage delivers a gate current to the IGBT component, this amplification stage comprising an ignition circuit 30 and a rapid extinction circuit 40. A slow extinction circuit 50 is connected between the gate G of the IGBT component and the output of the generator circuit. A circuit 60 for the detection of a collector-emitter voltage of the component is connected to a feedback circuit 70 delivering a feedback signal 71 that acts on the rapid extinction circuit 40 and on the output 22 of the generator circuit.

Abstract: High-performance low-power isolated bootstrapped gate drive apparatus and methods are disclosed for driving high-side and floating transistors. The gate drivers use edge-triggered capacitive-coupled inputs. The gate drivers may include detection and delay circuitry to facilitate zero-voltage-switching of the high side or floating transistor and providing more robust rejection of false triggering. A capacitively coupled differential input edge triggered gate driver provides exceptional immunity to false triggering. The gate drivers may be used in transformer coupled drive circuits using transformers that need only support coupled pulses wide enough to be recognized as an edge by the input circuit.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A technique for extending the size of a power transistor beyond one integrated circuit is disclosed. An example apparatus includes a first integrated circuit chip having a first switch, which includes first, second and third terminals. The first integrated circuit chip further includes a first driver circuit having an input and an output. The first integrated circuit chip also has a first control circuit coupled to output a first control signal. A second integrated circuit chip is included, which has a second switch including first, second and third terminals. The second integrated circuit chip also includes a second driver circuit having an input and an output. The second and third terminals of the first switch are coupled to the second and third terminals, respectively, of the second switch. The first driver circuit input and the second driver circuit input are coupled to receive the first control signal.

Abstract: An exemplary driving circuit (20) includes gate lines (201) that are parallel to each other and that each extend along a first direction; first data lines (202) that are parallel to each other and that each extend along a second direction substantially orthogonal to the first direction; thin film transistors (203) provided in the vicinity of intersections of the gate lines and the data lines; a gate driving circuit (210) connected to the gate lines; a data driving circuit (220) connected to the data lines; an access circuit (230) configured for accessing data signals outputted by the data driving circuit; and an output control circuit (240) configured for receiving the data signals accessed by the access circuit and making the time period in which the data signals are applied to the first data lines in accord with the time period during which the thin film transistors are switched on.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: To provide a highly reliable inverter apparatus which discriminates long-cycle noise generated by the isolated signal transmission element from short-cycle dv/dt noise and induction noise. A low pass filter, band pass filter, and a switching means are provided between the input section of the gate drive circuit of the voltage-drive type power semiconductor switching element and the isolated signal transmission means that transmits the output of the control circuit; and an abnormal signal discriminating circuit is also provided which turns on and off the switching means according to the output of the band pass filter thereby eliminating long-cycle noise derived from the isolated signal transmission element, short-cycle dv/dt noise, and induction noise; and also outputs alarm signals.

Abstract: Circuitry and methodology for controlling a FET or another transistor device provided to supply power to a circuit board insertable into a live backplane to provide inrush current slew rate control. The FET control circuit is responsive to an input signal variable in a preset manner to produce a FET control signal for controlling the FET so as to form an output signal corresponding to the input signal. The control circuit is configured to prevent the uncontrollable step in the output from being produced when the FET control signal reaches a level sufficient to control the FET. In one embodiment, a comparator is provided for comparing the FET control signal with a reference value that may correspond to a current for charging a control terminal of the FET to prevent the input signal from changing until the FET control signal exceeds the reference value.

Abstract: Analog bidirectional switches (20) comprising a first (1) and a second (2) transistor function badly in case of the signal voltage at an input or an output of the switch (20) exceeding the supply voltage used for operating the switch (20). By providing the switch (20) with a circuit (21), a second control signal (“f”) destined for the second transistor (2) is no longer generated by solely inverting a first control signal (“e”) destined for the first tranistor (1), but is generated in response to the first control signal (“e”) and by taking into account the in/output signal (“z”) at an in/output of the switch (20). The circuit (21) comprises a generator (22) for generating the second control signal (“f”) having either a fixed value or a value of the in/output signal (“z”), and comprises a detector (23) for supplying the in/output signal (“z”) to the generator (22). A further circuit (24) comprises a further generator for generating a backgate signal (“bg”) destined for the second transistor (2).

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: A gate driver for a power switch, comprising a gate drive circuit coupled to the gate of the power switch for at least one of turning on and turning off the power switch; a gate voltage control circuit in the gate drive circuit for controlling a voltage applied to the gate of the power switch during at least one of turning on and turning off the power switch; and a signal supplied to the gate voltage control circuit indicative of a voltage rate of change per unit time to be applied in at least one of turning on and turning off the power switch.

Abstract: A circuit for preventing shoot-through in a high side switching transistor coupled in series with a low side switching transistor across a supply voltage, the circuit comprising a voltage reference circuit having an output providing a reference voltage which is negative with respect to the supply voltage provided to the high side switching transistor, the reference voltage being applied to the control electrode of the high side switching transistor when the high side switching transistor is off and the source of the high side switching transistor exceeds the reference voltage and the low side switching transistor is on.

Abstract: A semiconductor device controller includes a current supply control unit for controlling a conduction state of a semiconductor device connected to a load in response to a control signal to supply current to the load, a current level judging unit for comparing one or more switching judgment values set in an area smaller than an overcurrent judgment value with current detected by a current detecting unit to carry out a current level judgment and a time constant changing unit for changing the circuit time constant of the input signal processing circuit in accordance with a judgment result by the current level judging unit.

Abstract: Embodiments of isolated gate driver circuits are disclosed for driving high- and low-side switching devices for half- and full-bridge power converter topology. Disclosed circuits provide sufficient dead-time, operate over a wide range of duty cycles, and require a single power supply (Vcc). Typical applications for such circuits include cold cathode fluorescent lamp (CCFL) inverters that are powered by a high voltage DC rail.

Abstract: A control output signal is supplied to a gate electrode of an insulated gate transistor from a control signal output terminal of a control device, however, with regard to the insulated gate transistor, a control output signal is also influenced when that transistor is short-circuited, and a signal waveform different from that in a normal operating state occurs. The short-circuit is detected by monitoring the control output signal of the insulated gate transistor, and in case of the short-circuit, the short-circuit protection of the insulated gate transistor is performed by forcing the control device to stop that control output signal.