With Sensing Amplifier Patents (Class 327/51)
  • Patent number: 9117547
    Abstract: Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventor: John E. Barth, Jr.
  • Patent number: 9077323
    Abstract: Integrated circuits having analog-to-digital converters are provided. Analog-to-digital converters may contain latched comparators. A latched comparator may include inputs configured to receive a differential input voltage signal, a differential reference voltage signal, and a clock signal. The comparator may include a preamplifier, a latching circuit, a level shifter, and a flip-flop coupled in series. The preamplifier may include large input transistors for minimizing offset, stacked tail transistors, and diode-connected load transistors for minimizing kickback noise. The preamplifier may be used to generate amplified voltage signals. The latching circuit may include a first pair of cross-coupled pull-down transistors, a second pair of cross-coupled pull-up transistors, and precharge transistors.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 7, 2015
    Assignee: Altera Corporation
    Inventors: Ali Atesoglu, Weiqi Ding
  • Patent number: 8994406
    Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: March 31, 2015
    Assignee: Nanyang Technological University
    Inventors: Joseph Sylvester Chang, Bah Hwee Gwee, Kwen Siong Chong
  • Patent number: 8988959
    Abstract: A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit associated with the base inverter circuit and configured to employ the previous logic-level voltage to decouple one of the logic-high and logic-low voltage sources from one of the inputs and thereby shift a trip voltage of the base inverter circuit toward the input voltage.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 24, 2015
    Assignee: LSI Corporation
    Inventor: Rajiv Roy
  • Patent number: 8941412
    Abstract: A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Robert H. Dennard
  • Patent number: 8928356
    Abstract: In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: January 6, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Paul Raymond Andrys, Michael Lynn Gerard, Terrence John Shie
  • Patent number: 8854083
    Abstract: A sensing amplifier using capacitive coupling and a dynamic reference voltage, where the sensing amplifier circuit includes a bit line, configured to receive charging and discharging signals; a sensing amplifier, connected to the bit line and configured to receive the bit line and a reference voltage for comparison and configured to enlarge the voltage difference between a high point and a low point; and a reference voltage generator, connected to the sensing amplifier to generate the reference voltage required for the sensing amplifier to compare. The sensing amplifier effectively enhances sensing margin of the sensing amplifier circuit; and in addition, to accelerate the access speed, the sensing amplifier can easily determine the correct stored data and further quickly solve the problems of high-speed storing the data by the storage units.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: October 7, 2014
    Assignee: National Tsing Hua University
    Inventors: Jui-Jen Wu, Tun-Fei Chien, Meng-Fan Chang, Yu-Der Chih
  • Patent number: 8779800
    Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 15, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yin Jae Lee
  • Patent number: 8779748
    Abstract: An error amplification circuit includes an integrated circuit and a phase compensation capacitor. The integrated circuit includes an error amplifier to amplify a difference between a predetermined reference voltage and an input feedback voltage for output; a current generator circuit to generate a bias current for supply to the error amplifier; a phase compensation resistor; a bias-current control terminal; and a phase compensation terminal connected to an output terminal of the error amplifier via the phase compensation resistor. The phase compensation capacitor is connected to the phase compensation terminal, the phase compensation capacitor being provided outside the integrated circuit.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: July 15, 2014
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Gotoh
  • Publication number: 20140163386
    Abstract: A circuit and method for long term electrocardiogram (ECG) monitoring is implemented with the goal of reducing power consumption, battery size, and consequently device size. In one embodiment, the integrated circuit includes an amplifier cell having a plurality of input terminals and an output terminal; a QRS amplifier cell in communication with the output of the amplifier cell; a baseline amplifier cell in communication with the output of the amplifier cell; a comparator cell having a first input terminal in communication with the output terminal of the QRS amplifier cell; and a VDC cell having an input in communication with the output of the baseline amplifier cell and an output in communication with the second input terminal of the comparator cell, wherein the comparator cell generates an output pulse in response to the output signal from the amplifier cell and the output signal from the baseline amplifier cell.
    Type: Application
    Filed: March 13, 2013
    Publication date: June 12, 2014
    Applicant: Massachusetts Institute of Technology
    Inventors: David Da He, Charles G. Sodini
  • Patent number: 8749273
    Abstract: In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: June 10, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Paul Raymond Andrys, Michael Lynn Gerard, Terrence John Shie
  • Patent number: 8742796
    Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: June 3, 2014
    Assignee: Nvidia Corporation
    Inventors: William Dally, Jonah Alben
  • Patent number: 8710867
    Abstract: An auto-mute control circuit is disclosed. The auto-mute control circuit includes an analog amplifier, a detecting circuit and a direct-current (DC) level adjusting circuit. The analog amplifier receives an input signal and outputs a sensing voltage signal accordingly. The detecting circuit compares a common-mode voltage received with the sensing voltage signal received and outputs a comparison signal accordingly. The DC adjusting circuit receives the comparison signal and outputs an Up-Down digital signal, a fine tune digital signal and a rough tune digital signal, so that a sensing DC level is equal to the common-mode voltage.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 29, 2014
    Assignee: Anpec Electronics Corporation
    Inventor: Ming-Huang Chang
  • Patent number: 8710871
    Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Patent number: 8705304
    Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Seong-Hoon Lee, Onegyun Na, Jongtae Kwak
  • Patent number: 8692580
    Abstract: An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ming Hung, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Patent number: 8680891
    Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: March 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Xuhao Huang, Xiaohong Quan
  • Patent number: 8659321
    Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: February 25, 2014
    Inventors: Yuko Watanabe, Yoshiro Riho, Hiromasa Noda, Yoji Idei, Kosuke Goto
  • Patent number: 8653865
    Abstract: A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: February 18, 2014
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Kikuo Utsuno
  • Patent number: 8648623
    Abstract: A single stage current sense amplifier is described that generates a differential output that is proportional to a current through a sense resistor. The voltage across the sense resistor is Vsense. The current sense amplifier includes a differential transconductance amplifier having high impedance input terminals. An on-chip RC filter filters transients in the Vsense signal. A feedback circuit for each leg of the amplifier causes a pair of input transistors to conduct a fixed constant current irrespective of Vsense, which stabilizes the transconductance. A gain control resistor (Re) is coupled across terminals of the pair of input transistors and has Vsense across it. The current through the gain control resistor is therefore Vsensex1/Re. A level shifting circuit coupled to each of the input transistors lowers a common mode voltage at an output of the amplifier. Chopper circuits at the input and output cancel any offset voltages.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: February 11, 2014
    Inventors: Hengsheng Liu, Edson Wayne Porter, Gregory Jon Manlove
  • Patent number: 8643405
    Abstract: A multi-stage passive capture adapter (PCA) circuit is configured to sense and recover digital signals present on a high-speed serial bus for capture and analysis in external test equipment. A first stage of the PCA circuit includes a differentiator that functions as a high impedance probe that contacts the serial bus to capture an original input signal waveform of the high-speed digital signals. The signal waveform is fed to a dual-slope comparator/driver that includes a plurality of high-speed comparators and drivers. The second stage includes a differential receiver/shaper that converts logic levels of differential receiver outputs to input signals that set and reset a signal restorer whose output signals are fed to a driver of a driver/shaper. The output of the driver is then fed to a shaper network configured to substantially match an output signal of driver/shaper to the input signal waveform sensed from the high-speed serial bus.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: February 4, 2014
    Assignee: MCCI Corporation
    Inventors: Terrill M. Moore, Roy F. Flacco
  • Patent number: 8618839
    Abstract: Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: December 31, 2013
    Assignee: International Business Machines Corporation
    Inventors: Howard H. Chi, Haitao O. Dai, Kai D. Feng, Donald J. Papae
  • Patent number: 8604838
    Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 10, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Robert F. Payne
  • Patent number: 8598506
    Abstract: An apparatus according to an embodiment of the present invention includes a conversion unit configured to generate electric charge, a first amplification unit configured to amplify a signal corresponding to an amount of the electric charge and output a first amplified signal, a second amplification unit configured to amplify the first amplified signal and output a second amplified signal, a current source shared by the first amplification unit and the second amplification unit, and a selection unit configured to bring the first amplification unit and the second amplification unit into an inactive state. The current source is shared by the first amplification unit and the second amplification unit. The number of current sources is therefore reduced. This leads to the reduction in power consumption.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: December 3, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Kato, Yukihiro Kuroda
  • Patent number: 8593875
    Abstract: A row driver is configured to activate a row line responsive to a signal having one of multiple possible values. A column driver is configured to activate a column line responsive to a signal having one of multiple possible values. The row and column drivers comprise sets of sense amps and decoders. One of a plurality of lines is operably connected to and input/output line responsive to the active row line and column line. The use of sense amps in the row and column drivers enables this flow control circuit to operate with low power consumption and allows the flow control circuit to act as a register.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: November 26, 2013
    Inventor: Benjamin J. Cooper
  • Patent number: 8581631
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: November 12, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Publication number: 20130294185
    Abstract: A sense amplifier circuit includes an enable signal generation unit configured to generate an enable signal when a change in a voltage level of input signals is sensed; a sink unit configured to provide a sense voltage in response to the enable signal; and a sense unit configured to generate an output signal in response to the sense voltage and the input signals.
    Type: Application
    Filed: September 5, 2012
    Publication date: November 7, 2013
    Applicant: SK HYNIX INC.
    Inventor: Hyung Soo KIM
  • Patent number: 8559240
    Abstract: A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Pyo Hong, Doo-Young Kim
  • Patent number: 8536898
    Abstract: A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: September 17, 2013
    Inventors: David James Rennie, Manoj Sachdev
  • Patent number: 8536899
    Abstract: Embodiments of a calibration circuit for a current source which may include a first control switch, a second control switch, and a capacitor. In embodiments, the first control switch may be operable to couple the capacitor to the current source and the second control switch may be operable to couple the capacitor to a reference current source to enable the capacitor to be charged or discharged according to a first control signal provided to the first control switch and a second control signal provided to the second control switch. In embodiments, the calibration circuit may be included in a digital-to-analog (DAC) converter.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 17, 2013
    Assignee: Intel Corporation
    Inventors: Cho-Ying Lu, Chun Lee, Jad B. Rizk
  • Patent number: 8476933
    Abstract: A receiver circuit of a semiconductor apparatus includes a first sense amplifier, a level restriction unit, and a second sense amplifier. The first sense amplifier amplifies an input signal in response to a clock signal and generates a first signal with a voltage swing between a first level and a second level. The level restriction unit receives the first signal and generates a correction signal with a voltage swing between the first level and a third level. The second sense amplifier amplifies the correction signal in response to the clock signal and generates a second signal with the voltage swing between the first level and the second level.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 2, 2013
    Assignee: SK Hynix Inc.
    Inventor: Sang Yeon Byeon
  • Publication number: 20130147520
    Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: Texas Instruments Incorporated
    Inventor: Robert F. Payne
  • Patent number: 8462572
    Abstract: An ultra low power sense amplifier circuit for amplifying a low swing input signal to a full swing output signal is disclosed. In one aspect, the amplifier circuit includes a first amplifier stage for pre-amplifying the input signal to an intermediate signal on its internal nodes, a second amplifier stage for amplifying the intermediate signal to the output signal, and a control circuit for sequentially activating the first and second amplifier. The first amplifier has a capacitor for limiting energy consumption and two upsized PMOS transistors without NMOS transistors.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: June 11, 2013
    Assignees: Stichting IMEC Nederland, Katholieke Universiteit Leuven
    Inventors: Vibhu Sharma, Stefan Cosemans, Wim Dehaene, Francky Catthoor, Maryam Ashouei, Jos Huisken
  • Publication number: 20130141139
    Abstract: Electronic interface and method for reading a capacitive sensor that includes one input capacitor (30) or several input capacitors, in which the capacitive sensor is excited with a two-level voltage (Vlow, Vhigh) and read by a charge-sense amplifier whose output is sampled in four successive instants. An evaluation unit (333) is arranged to compute two difference values (V12, V34) between two pairs of samples corresponding to different voltage levels and to combine said difference values into an output value (V_out_raw) proportional to the charge transferred to the input of the charge-sense amplifier and an error value (error_bit) sensitive to a time derivative of a noise current din/dt.
    Type: Application
    Filed: November 27, 2012
    Publication date: June 6, 2013
    Applicant: Advanced Silicon SA
    Inventor: Advanced Silicon SA
  • Patent number: 8456197
    Abstract: A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 4, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Prashant Dubey, Navneet Gupta, Shailesh Kumar Pathak, Kaushik Saha, Gagandeep Singh Sachdev
  • Patent number: 8446308
    Abstract: A system and method for processing an analog signal output by a sensor. The system and method converting, using at least one analog-to-digital converter (ADC), the analog output signal to a digital signal, the digital signal including a plurality of samples at a predetermined resolution, detecting whether a trigger condition is met by analyzing the digital signal, detecting an event based on trigger information from the detecting whether a trigger condition is met, generating event information having time information included therein when the event is detected, defining one or more time windows based on the time information included in the event information, performing decimation on the digital signal based on the defined one or more time windows to generate a decimated signal, and outputting the decimated signal.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 21, 2013
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventors: Kent Burr, Gin-Chung Wang, John S. Jedrzejewski, Gregory J. Mann
  • Patent number: 8445832
    Abstract: An optical communication device which can be operated at high speed is provided. For example, the optical communication device includes: a pre-amplifier circuit PREAMP1 amplifying a current signal Iin from a photodiode PD, and converting an amplified signal into a voltage signal; and an operating-point controller circuit VTCTL1 controlling an operation of the PREAMP1. The PREAMP1 includes a negative feedback path formed by a feedback resistance Rf1, and includes: a level-shift circuit LS1 level-shifting in accordance with an operating-point control signal Vcon; and an amplifier circuit AMP1 connected to a subsequent stage of the LS1 and performing an amplifying operation with a high gain. The VTCTL1 includes a replica circuit configured by the same circuit and circuit parameter as those of the AMP1 and electrically connected between the input and the output, and generates the Vcon so that an output DC level of this replica circuit is matched with an input DC level of the AMP1.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: May 21, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takemoto, Hiroki Yamashita, Tatsuya Saito
  • Patent number: 8362807
    Abstract: A sense amplifier having compensation circuitry is described. The compensation circuitry includes at least one pair of compensation transistors. When compensation is desired, one or a combination of the bulk of the at least one pair of compensation transistors is provided with one or a combination of compensation voltages.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bharath Upputuri, Shreekanth Sampigethaya
  • Patent number: 8354863
    Abstract: A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: January 15, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yin Jae Lee
  • Patent number: 8345498
    Abstract: A sense amplifier includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor form cross coupled sensing pairs. The third PMOS and the fourth PMOS transistors serve as compensation transistors. The third NMOS and the fourth NMOS transistors serve as sensing enabling transistors.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sergiy Romanovskyy, Muhammad Nummer
  • Patent number: 8330498
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 8310853
    Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
  • Patent number: 8283950
    Abstract: Embodiments of delay lines may include a plurality of delay stages coupled to each other in series from a first stage to a last stage. Each delay stage may include an input transistor receiving a signal being delayed by the delay line. The delay line may include a compensating circuit configured to compensate for a change in a transconductance of the input transistor resulting from various factors. One such compensating circuit may be configured to provide a bias signal at an output node having a magnitude that is a function of a transconductance of a transistor in the compensating circuit. The bias signal may be used by each of the delay stages to maintain the gain of the respective delay stage substantially constant, such as a gain of substantially unity, despite changes in a transconductance of the respective input transistor in each of the delay stages.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Willey
  • Patent number: 8269546
    Abstract: A modulator drive circuit provides a modulator drive signal, representative of a data waveform, to modulate an optical signal for transport across a network infrastructure. The modulator drive circuit includes a broadband Bias-T circuit insensitive to the frequency range of the data waveform. The Bias-T circuit provides for an adjustable bias level to maintain proper operation of a modulator used to modulate the optical signal. One or more modulator drive circuits may be provided on a single substrate.
    Type: Grant
    Filed: September 27, 2009
    Date of Patent: September 18, 2012
    Assignee: Infinera Corporation
    Inventor: Babak Behnia
  • Patent number: 8199858
    Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Kenichi Shimizu
  • Patent number: 8195990
    Abstract: In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: June 5, 2012
    Assignee: Oracle America, Inc.
    Inventors: Ronald Ho, Ashok V. Krishnamoorthy, John E. Cunningham, Robert J. Drost
  • Patent number: 8183906
    Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Roland Thewes, Ralf Brederlow
  • Patent number: 8164362
    Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Morteza Cyrus Afghahi, Esin Terzioglu
  • Patent number: 8164363
    Abstract: An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependent. If the input data is at the first input data value, the first node is set and held at a first storage value after a first delay, and the second node is set and held at a second storage value after a second delay, and if the input data is at a second input data value, the first node is set and held at a third storage value after a third delay, and the second node is set and held at a fourth storage value, after a fourth delay. This internal-path dependent difference in delay enables ASAFF to achieve zero setup time.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: April 24, 2012
    Assignee: Marvell International Ltd.
    Inventor: Jason Su
  • Patent number: 8143920
    Abstract: A system includes a current sensor to receive an input signal based on a sense current provided to load circuitry. The current sensor is configurable to generate an output signal from the input signal based, at least in part, on one or more configurable characteristics of the current sensor. The system also includes a processing element to compare the output signal from the current sensor to one or more programmable parameters. The processing element is configurable to direct a current controller to regulate the sense current provided to the load circuitry according to the comparison, and is further configurable to set a configurable parameter associated with the current sense amplifier.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 27, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Derwin Mattos