Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A sense amplifier (10) has a pair of cross-coupled latches (12, 14, 16, 18) connected between a first voltage supply (V.sub.DD) and the sources of two transistors (20, 22). The gates of the two transistors receive a voltage differential to be sensed. The drains of the two transistors are coupled to a second voltage supply (V.sub.SS) through an enabling transistor (24). The resulting sense amplifier is fast, small, and relatively simple to construct.

Abstract: A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.

Abstract: A sense circuit has input and output terminals coupled through resistances to two fixed potentials. The input potential is amplified and inverted to control the gate of a field-effect transistor coupled between the input and output terminals. Alternatively, a sense circuit has first and second input terminals, and first and second output terminals. The first input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the second input and output terminals. The second input terminal is connected to the gate of a depletion-mode field-effect transistor coupled between the first input and output terminals. The depletion-mode field-effect transistors may be replaced by negative-resistance circuits. These sense circuits can obtain large voltage outputs from small current inputs.

Abstract: A differential latch sense amplifier for memories has (a) a first differential input circuit for detecting and shifting the voltage levels of the first and second input signals and coupled to first and second sense nodes, (b) a cross-coupled latch for providing gain to the first and second sense nodes, (c) a precharge circuit for precharging and equalizing the first and second sense nodes, (d) a first tristatable output driver for providing a first feedback, for outputting the voltage of the first sense node to a first output node, and for receiving data, (e) a second tristatable output driver for providing a second feedback, for outputting the voltage of the second sense node to a second output node, and for receiving data, and (f) a first feedback circuit for increasing the voltage gain and decreasing the sense output response time at the first and second sense nodes and for being controlled by the first and second tristatable output drivers.

Abstract: A dual stage adaptive peak detect circuit includes a fast peak detector that detects the trends in the magnitude of the incoming signal and an adaptable peak detector that accurately follows the peak of the signal. A difference circuit detects the voltage difference between the outputs of the fast peak detector and the adaptable peak detector. A voltage-to-current converter feeds back the current-converted difference voltage to the adaptable peak detector to adjust its peak detection charge current. The dual stage adaptive peak detector of the present invention is thus capable of accurately following the peak of an incoming signal with varying amplitudes.

Abstract: A self-contained, bi-polar high-side current sense amplifier which detects the magnitude and polarity of current flowing from one device to another, is disclosed. The amplifier has a symmetric architecture having two inputs and two outputs. One output is active for positive input signals corresponding to current flow in one direction, and the other output is active for negative input signals corresponding to current flow in an opposite direction. A symmetric current mirror in the amplifier provides the OR'ing function required to provide only one output at a time. The amplifier also utilizes aluminum sense and gain resistors, which allows cancellation of resistor temperature coefficients.

Abstract: A single-ended sense amplifier circuit for sensing the state of a bitline in a read-only memory. The sense amplifier includes an output circuit having an input and an output, the output for indicating a state of the bitline in response to a bitline voltage level. A precharge circuit is coupled to the input for charging the input to a first voltage level when the input is decoupled from the bitline. A discharge circuit is coupled between the bitline and the input. In one embodiment, the discharge circuit includes a field effect transistor coupled as a cascode device for coupling and decoupling the input to the bitline. The discharge circuit couples the input to the bitline when the discharge voltage level exceeds a threshold voltage level of the discharge circuit.

Abstract: A sense amplifier for sensing data from a pair of complementary bit lines. A bistable circuit is coupled to the bit lines through a pair of transistors. During the beginning of a sensing cycle, the transistors conduct allowing the bistable circuit to begin sensing the data on the lines. However, before the sense amplifier reaches one of its two stable states, the pair transistors cease conducting and isolate the bistable circuit from the bit lines. In this manner, the load associated with the bit lines is removed from the bistable circuit allowing it to more quickly sense data.

Abstract: A data sensing circuit for a semiconductor memory device having complementary bit lines, including a PMOS sense amplifier connected between the complementary bit lines, an NMOS sense amplifier connected between the complementary bit lines, a bit line equalization and precharge circuit connected between the complementary bit lines, a sense amplifier equalization and precharge circuit connected between sensing control nodes of the PMOS and NMOS sense amplifiers, a plurality of first capacitors, a plurality of second capacitors, a plurality of first fuses connected between the sensing control node of the PMOS sense amplifier and respective ones of the first capacitors, a plurality of second fuses connected between the sensing control node of the NMOS sense amplifier and respective ones of the second capacitors.

Abstract: A sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programable logic device (PLD). Array cells signals which are all normally received by the sense amplifier in a single product term input are instead connected to the sense amplifier in smaller groups of sub-product terms. Each smaller group of sub-product terms is then connected through a transistor cascode amplifier in the sense amplifier to form the single product term enabling a reduction of capacitance and an increase of output speed of the sense amplifier.

Abstract: An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Abstract: A method and circuit is provided for reading a memory array which utilizes multiple clocking signals during one read cycle to enable a dynamic sense amplifier to read data from the memory array. A dynamic sense amplifier is connected to an input line, a complementary input line, and a latch. A first equilibrating signal is input into the sense amplifier, followed thereafter by a first clocking signal. The first clocking signal enables the sense amplifier to read data on the input line and complementary input line. While the sense amplifier reads the data, the sense amplifier is isolated from the input and complementary input lines. Based upon the data read by the sense amplifier, an output state is provided for the latch. After reading the data, the sense amplifier is reconnected to the input and complementary input lines.

Abstract: A semiconductor memory device which includes, in a first embodiment, a first PMOS transistor having a source electrode coupled to a signal transport line, a second PMOS transistor having a source electrode coupled to an inverted signal transport line, a drain electrode coupled to a gate electrode of the first PMOS transistor, and a gate electrode coupled to a drain electrode of the first PMOS transistor, a first current limiter connected between the drain electrode of the first PMOS transistor and a reference potential, a second current limiter connected between the drain electrode of the second PMOS transistor and the reference potential, a first constant current source connected between a supply voltage and the source electrode of the first PMOS transistor, and, a second constant current source connected between the supply voltage and the source electrode of the second PMOS transistor.

Abstract: A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a second disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

Abstract: A logic circuit includes a differential amplifier circuit to which a first input signal and a second input signal both of which are complementary are to be supplied, having a circuit for outputting a first output signal and a second output signal both of which are complementary, the first and second output signals depending on a difference between the first and second input signals, an output terminal, and a switching circuit for, based on a first switching signal and a second switching signal which are complementary, performing a switching operation so that either the first output signal or the second output signal is selected as a signal supplied to the output terminal, wherein the signal supplied to the output terminal is a result of an logical operation of the first input signal and the first switching signal. A current sense amplifier may be substituted for the differential amplifier.

Abstract: A device is provided for detecting the content of cells of a memory, and for minimizing the read access time of a high-capacity EPROM memory in which cells are organized as a set of bit rows. A comparator including a differential amplifier compares a reference current from a reference column with a read current invoked in a cell of a bit row. The reference current and a read current flow through a resistive reference element and a resistive read element respectively. These resistive elements are connected, at one end, to a supply voltage source and, at the other end, to the non-inverting input and the inverting input respectively of the differential amplifier. The differential amplifier delivers as output a detection signal. In a preloading period the output of the differential amplifier is connected to its inverting input.

Abstract: A sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). Array cells signals which are all normally received by the sense amplifier in a single product term input are instead connected to the sense amplifier in smaller groups of sub-product terms. Each smaller group of sub-product terms is then connected through a transistor cascode amplifier in the sense amplifier to form the single product term enabling a reduction of capacitance and an increase of output speed of the sense amplifier.

Abstract: A high speed self-resetting, edge-triggered CMOS (SRCMOS) receiver and parallel L1/L2 latch combination are provided which may be used to receive and latch data from a single-ended input of static random access memory (SRAM) or a dynamic random access memory (DRAM). The invention comprises a true/compliment generator circuit (TCG) for generating a data and its compliment from a single-ended input, a reset circuit for automatically resetting the TCG independent of the system clock, and a parallel L1/L2 latch for storing the data for further processing. The L1/L2 latch preferably has scan-in and scan-out ports useful for testing and diagnostic purposes.

Abstract: A high-speed sense amplifier for a memory device with at least one memory cell, comprising true and complementary bit lines connected to the memory cell, a differential amplification circuit for inputting true and complementary bit data through the true and complementary bit lines, amplifying the inputted true and complementary bit data and transferring the amplified true and complementary bit data to true and complementary data bus lines, respectively, a first feedback loop for feeding the amplified true bit data on the true data bus line back to the memory cell through the true bit line, and a second feedback loop for feeding the amplified complementary bit data on the complementary data bus line back to the memory cell through the complementary bit line. According to the invention, the high-speed sense amplifier can sense and amplify the data on the true and complementary bit lines at a high speed. Therefore, an access speed of the memory device can be enhanced.

Abstract: A level shift amplifier has first to n th inverters connected in series, with each positive voltage terminal of the first to n th inverter is connected to the first source line. Each negative voltage terminal of the first to (n-2)th inverter is connected to output of the second next inverter, respectively. The negative voltage terminal of the (n-1)th inverter is connected to a part of the output of the n th inverter, and the negative voltage terminal of the n th inverter is connected to the second source line. n pieces of feedback elements are connected between the input and output of each inverter. When a feedback element is established so that the gain of each inverter can be maximized, a self-bias amplifier circuit is composed. All inverters are driven by the self-bias voltage. The fine amplitude signals input to the first inverter become the output voltage of full amplitude between the first and second source lines in the n-th inverter.

Abstract: A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Abstract: In a memory unit having a sense amplifier for reading data, the dependence of the memory cell current detection level of the sense amplifier on the power source voltage is restrained. A memory-unit sense amplifier includes a bias circuit (20, 21, 22) for generating an output which mitigates fluctuations in the power source voltage VDD; and a detection result output section (10, 15) which outputs a memory cell current detection result obtained for the purpose of obtaining the value of memory cell data and which has a Pch (P-channel transistor), to the gate of which the output of the bias circuit (20, 21, 22) is connected, whereby fluctuations in the source/gate voltage of the Pch 10 are mitigated so as to restrain the dependence of the memory cell current detection level on the power source voltage.

Abstract: A low-power, high-speed sense amplifier for a memory device with at least one memory cell, comprising a voltage shifter for inputting voltages from data bus and data bus bar lines connected respectively to bit and bit bar lines connected to the memory cell and, in response to a sense amplifier enable signal, decreasing the inputted voltages and shifting the decreased voltages, a current sense amplification circuit responsive to the sense amplifier enable signal for sensing current of an output voltage from the voltage shifter to increase a gain thereof, and a voltage sense amplification circuit for sensing a difference between the output voltage from the voltage shifter and an output voltage from the current sense amplification circuit.

Abstract: A memory cell containing a ferroelectric capacitor the memory state of which is sensed by cycling the potential across the capacitor from zero, through an upper electric field point and back to zero. If the cell was residing in the upper permanent remnant polarization point, a low change in charge flow occurs and if the cell was residing in the lower permanent remnant polarization point, a low (near zero) change in charge flow occurs. This change in charge flow from a near zero value to a large amount allows a very accurate reference capacitor to be used for the comparison or sensing process.

Abstract: A single ended sense amplifier that not only preserves the high speed feature of the ordinary .vertline.V.sub.TP .vertline., the threshold voltage of a PMOS transistor, but also eliminates the current leakage problem of conventional designs. The single-ended sense amplifier uses seven transistors and one phase clock instead of eleven transistors and two phase clocks as used in the prior art.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

Abstract: A semiconductor memory device according to the present invention includes a first and second bit lines; a word line; a memory cell electrically connected to the first and second bit lines and the word line; a first current sense amplifier for reducing a potential level of a current flowing in the first and second bit lines and including diode-connected first and second P-type transistors, third and fourth N-type transistors series-connected to the first and second P-type transistors respectively and a fifth N-type transistor connected to the third and fourth N-type transistors, the first P-type transistor having a control electrode electrically connected to a control electrode of the fourth N-type transistor and the second P-type transistor having a control electrode electrically connected to a control electrode of the third N-type transistor; and a second sense amplifier electrically connected to an output of the first current sense amplifier, for amplifying the amplitude of a potential applied between the f

Abstract: A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A data reading circuit comprising a first data line to which a first current signal having a first current value is supplied, a second data line to which a second current signal having a second current value is supplied, a current-voltage converter circuit connected between the first and second nodes for applying a first voltage potential difference, which corresponds to the difference between the first and second current values, between the first and the second nodes, a first node, a second node, a level shifting circuit connected between the first and second nodes and the third and fourth nodes for applying a second voltage potential difference, which is substantially equal to the first voltage potential difference in response to the same, between the third and fourth nodes and a feedback circuit connected between the first and second nodes and the third and fourth nodes for applying a third voltage potential difference, which is larger than the first voltage potential difference, between the first and seco

Abstract: A semiconductor device has a plurality of internal circuits capable of having two conditions of an active state and a precharge state in the internal circuits. The device comprises signal generation element for generating a first signal which causes said internal circuits to be initialized until satisfying a predetermined condition from a time when the power is supplied; and state set element which is connected to an external apparatus through an interface which is supplied an external state signal, and for setting a precharge state of the internal circuits by outputting an internal state signal corresponding to the external state signal in response to a supply of the first signal from the signal generation element.

Abstract: A sense amplifier for sensing the impedance between two terminals includes an amplification stage whose input is connected to one of the terminals. The input is connected to a power supply voltage VCC through two transistors in parallel. One transistor provides a high speed by providing a large current when the voltage on the input is low. Moreover, to increase speed and save power, that transistor turns off when the amplification stage input voltage is slightly above the amplification stage trip voltage. The other transistor provides a small current to pull the amplification stage input up almost to VCC to reduce the amplification stage power consumption. The small current does not interfere significantly with the pull-down speed. One of the amplification stage power terminals is connected to ground through current limiting transistors to reduce the amplification stage power consumption when the amplification stage input voltage is at its low value which is slightly below the trip voltage.

Abstract: A read circuit is comprised of a circuit for reading out a data signal from one selected among a plurality of arrayed semiconductor memory cells by using a cascode type sense amplifier, in which the drop of the power supply voltage level and the level shift of the bit lines are properly set to allow the cascode type sense amplifier to operate at a low voltage. The bit lines are clamped to a low voltage level obtained by lowering the power supply voltage level and then the voltage level of the bit lines is shifted by one-stage wired-OR logic circuit in order to assure the stable operation of the cascode type sense amplifier.

Abstract: A semiconductor memory device of the present invention includes a sense amplifier for converting an electrical current flowing through a sense node between a load and a current limiting circuit into an electrical voltage and for outputting the produced electrical voltage. The sense amplifier is constituted by plural stage amplifiers each of which may be shorted across it input and output terminals. The amplifiers are set to the amplifying state, stage by stage, starting at the amplifier closest to the node, for overcoming problems concerned with noise superposition or an output delay caused by bit line overcharging. In a preferred embodiment, MOS transistors for electrical discharging or precharging are provided in the bit line or the sense node for speeding up the operation.

Abstract: A sensing circuit for a floating gate memory device is disclosed. The sensing circuit has a first voltage amplifier which generates a first output voltage, and a current amplifier which receives the first output voltage and generates a first output current in response thereto. The first voltage amplifier has a control transistor which generates a first output voltage in response to the memory device being in one state and a second output voltage in response to the memory device being in another state. The circuit also comprises a dummy cell, a second voltage amplifier connected thereto for generating a second output voltage. A second current amplifier receives the second output voltage and generates a second output current in response thereto. A comparator receives the first and second output currents, compares them, and generates an output indicative of the state of the memory device.

Abstract: Reduced manufacturing costs and wafer size, lower power consumption, and increased operating speed are achieved in memory circuits by providing a novel sense amplifier design that is most sensitive to voltages variations around the source voltage (V.sub.dd). The sense amplifier includes two inverters that are regeneratively cross-coupled through a circuit that is controlled by a system clock. The inverters are powered from the bit lines that couple the sense amplifier to a memory cell. Novel applications of the sense amplifier in memory circuits also are described.

Abstract: A data output circuit of a semiconductor memory device matches an equalizing level of voltages at data lines in a pair with a logic threshold voltage of data output buffers. The data output circuit having an equalizing transistor connected between first and second nodes connected to the outputs of a sense amplifier, includes a threshold voltage control circuit disposed between the sense amplifier and the data output buffers for allowing a threshold voltage of the data output buffers to match with the equalizing level of the voltages at the first and second nodes. The threshold voltage control circuit has the same structure and characteristics as that of the output buffers, so as to ensure that the logic threshold voltage of the data output buffers matches with the equalizing level of the voltages at the first and second nodes.

Abstract: It is an object of the present invention to provide an amplifier circuit for amplifying the voltage amplitude of a small amplitude signal to the CMOS level which operates at a high speed with low power dissipation while assuring high gain. PMOS FETs M.sub.11, M.sub.16 for pulling up the output are of the source-driving type and receive signals V.sub.IN1, V.sub.IN1i, respectively, and NMOS FETs M.sub.12, M.sub.17 for pulling down the output are of the gate-driving type and receive level shifted signals V.sub.IN2, V.sub.IN2i, respectively. In the circuit of the present invention, constant voltages for reference are set by diodes D.sub.13, D.sub.14, and bipolar transistors are connected as transistors for driving an output portion of the amplifier circuit.

Abstract: The invention relates to memories made in integrated circuit form and, particularly, to high capacity memories that need to have fast access time. The invention provides for carrying out a reading in two stages: precharging and then reading. A precharging is done, at an intermediate value, between the high logic level and the low logic level, of the data output pads at which the information elements read in the memory appear. A circuit to memorize the logic state on the pad and a threshold inverter enable this result to be obtained.

Abstract: A memory system comprising a memory array having at least two pairs of data lines, first and second data lines corresponding to columns in the memory array. The memory array also includes two level shifter circuits, a first shifter circuit connected to the first lines and a second level shifter circuit connected to the second data lines, wherein the level shifter circuits produce output signals and may be enabled and disabled. A selection signal is used to selectively enable and disable the level shifter circuits, wherein one pair of data lines may be selected. An amplification circuit is connected to the level shifters for amplifying the output signals from the level shifter circuits, and a logic circuit is used to generate logic output signals in response to the amplified output signals from the amplification circuit.

Abstract: The semiconductor memory device according to this invention includes a memory cell array which comprises plural memory cells arranged in row and column direction in the form of an array, plural bit line pairs for connecting these memory cells in the unit of a column and word lines for connecting these memory cells in the unit of a row, sense amplifiers which are respectively connected to each of the bit line pairs at one end thereof and which amplify the potential difference between the bit lines of each pair in response to activation signals, and transfer gate means which divide said plural bit lines respectively into at least two portions corresponding to control signals, the sense amplifiers for the bit line pairs which belong to the nth columns (n is an odd numbered integer) thereof being arranged on one end of the bit line pairs and on the other end thereof for the those which belong to the (n+1)th columns.

Abstract: A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

Abstract: A dynamic random access memory is formed with two power supply meshes extending throughout a memory array region in which are formed memory cells and sense amplifier circuits, thereby enabling sense amplifier drive circuits to be distributed throughout that memory array region, with each sense amplifier drive circuit being connected to the nearest points on the two supply meshes. A substantially improved value of read access time, or increased total memory capacity, can thereby be achieved by comparison with a DRAM in which the sense amplifier drive circuits are provided only at the periphery of a memory array region.

Abstract: A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.

Abstract: There is provided an improved amplifier circuit responsive to two complementary input signals VI, /VI for providing an amplified output signal VO. In the amplifier circuit, a PMOS transistor and an NMOS transistor alternatingly rendered conductive in response to the input signal VI are connected in series between a power supply potential Vcc and a ground potential. When the input signal VI at a high level is applied, transistor is turned on, while transistor is turned off. Since feedthrough current flowing from the power supply potential towards the ground potential is prevented, the power consumption and operation speed can be improved.

Abstract: A signal amplitude distribution analyzer measures the amplitude probability density function of electrical signals, and in particular, the amplitude probability distribution of noise signals. Such measurements may be used to determine the "Gaussianicity" of noise signals, that is, a measurement of how closely the amplitude distribution of noise signals corresponds to theoretical values derived from the Gaussian probability distribution density function. This theoretical density function represents the relative percentage of time that a noise signal is at a given amplitude. The invention gives an approximation of this function by measuring the amount of time a noise signal is between a window of two adjustable voltage levels. This is accomplished by producing an output voltage proportional to the amount of time a noise signal amplitude falls within the window of values defined by the two adjustable voltage levels.