Abstract: A circuit and method for generating an evaluation signal used to turn OFF one or more sense amplifiers. The sense amplifiers may be configured to present a first and second output in response to (i) an input signal and (ii) an enable signal. A detect circuit may be configured to present a detect signal in response to the first and second outputs. A control circuit may be configured to present the enable signal in response to (i) the detect signal and (ii) a wordline signal.

Abstract: A P-type MOSFET transistor as a current source and an N-type MOSFET transistor are connected in series between a power supply and one end of a bit line that is also connected to a memory cell with the other end thereof. The gate electrode of the P-type MOSFET transistor and that of the N-type MOSFET transistor are then biased by a current capability setting circuit in such a manner that a current capability of the P-type MOSFET transistor is smaller than a current capability of a memory cell and a current capability of the N-type MOSFET transistor is larger than the current capability of the P-type MOSFET transistor.

Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A sense amplifier that includes a sensing circuit, a first feedback circuit, and an output buffer. The first feedback circuit is coupled to an output of the sensing circuit and is configured in a feedback arrangement with the output buffer. The output of the sensing circuit provides an output signal having a first slew rate as the output signal transitions from a first logic state to a second logic state. The first feedback circuit may increase the slew rate of the output signal. The sense amplifier may also include a second feedback circuit coupled to the output of the sensing circuit and configured in a feedback arrangement with the output buffer. The second feedback circuit may increase a second slew rate of the output signal as the output signal transitions from the second logic state to the first logic state. The sense amplifier may be a current sense amplifier that may be used to sense the amount of current flowing through a nonvolatile memory circuit.

Abstract: There are provided a semiconductor device, in which one electrode of each capacitor is connected to multiple input terminals and the other electrodes of the capacitors are commonly connected to a sense amplifier, and which has an analog signal processing circuit arranged between at least one of the multiple input terminals for inputting signals to the capacitors and the capacitors, and a unit for resetting the commonly connected electrode sides of the capacitors, a signal processing system having a plurality of semiconductor devices each identical to the semiconductor device and performing signal processing, and a calculation method using the semiconductor device, whereby arithmetic operations of analog signals can be easily attained and high-speed processing and low consumption power can be achieved with a small circuit scale.

Abstract: The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3.0 volts, the two NFET transistors result in a voltage drop of 2.0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1.0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free.

Abstract: A current-measuring circuit is provided which is designed to measure the current flowing through an electric load and a switching transistor. The current-measuring circuit includes a current-measuring device. The current-measuring device includes a current-measuring transistor and a voltage control circuit. The current-measuring transistor is disposed in parallel to the switching transistor and allows the current to flow therethrough that is proportional to the current flowing through the electric load and the switching transistor and that is used to measure the current flowing through the switching transistor and the electric load. The voltage control circuit controls a potential difference across the current-measuring transistor so as to match a potential difference across the switching transistor, thereby achieving the proportion of the current flowing through the current-measuring transistor to the current flowing through the switching transistor and the electric load.

Abstract: A sense amplifier enable signal generating circuit of a semiconductor memory device includes: a sense amplifier enable signal generating section for receiving an input signal externally applied, and generating a sense amplifier enable signal; a delay section for delaying the sense amplifier enable signal generated from the sense amplifier enable signal generating section; a detecting section for detecting the variation of a power supply voltage in accordance with a control signal externally applied, and generating a detection signal for the variation; a transfer section for transferring the delayed sense amplifier enable signal of the delay section in accordance with the detection signal generated from the detecting means; and an output section for receiving the sense amplifier enable signal generated from the sense amplifier enable signal generating means and the delayed sense amplifier enable signal of the delay section, and generating an output signal having a constant pulse width.

Abstract: A circuit and method are disclosed herein which convert signal values on first and second complementary outputs of a second sense amplifier to a single ended data signal for transmission on a read write drive (RWD) line. The circuit includes first and second followers coupled to the first and second complementary outputs, an inverter coupled to an output of the first follower, and a signal driver responsive to an output of the inverter and the second follower to drive signal levels on said RWD line between a first level representing a first data state and a second level representing a second data state.

Abstract: An amplifier circuit of the present invention comprises first and second signal lines transferred data from a memory cell, first and second nodes, a latch circuit coupled between the first and second nodes, a first MOS transistor coupled between the first signal line and the first node, and a second MOS transistor coupled between the second signal line and the second node.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: The circuit for controlling a sense amplifier according to the present invention can operate plurality of sense amplifiers groups selectively by controlling a bi-directional address signal for transferring data to the output buffer, an output buffer control signal for controlling the type of the data to be outputted into 8 byte, 16 byte etc., a sense amplifier enable signal for enabling the sense amplifier, and an erasure enable signal, therefore, the present invention can minimize a number of the sense amplifier groups, thereby reducing the power consumption and implementing a low power device.

Abstract: A single-ended sense amplifier pre-charges the data output line of a bank of memory cells or register file to approximately the switch point of an inverter that is part of a buffer, in preparation for the next data read cycle. The amplifier includes a stack of six transistors connected in series between a supply voltage and ground. The memory output is connected to the stack mid-point, to a latch input and to a buffer input. The most recent binary logic level read from memory passes through the latch. The latch and stack are then clocked, and the three-transistor portion of the stack turned on pulls the voltage on the stack mid-point to approximately one-half the supply voltage, which is the buffer inverter switch point. The stack is then turned off, and the stack mid-point floats at that voltage value in preparation for the next read cycle. As such, the common data line needs only slew a relatively small amount of voltage during the next read cycle.

Abstract: An amplifier 300 includes a differential pair of transistors 307a, 307b. A third transistor 306 controls current through transistors 307a, 307b of the differential pair in response to a stepped control signal.

Abstract: A sensing circuit for sensing the multiple states of a selected memory cell of a floating gate memory device is disclosed. The sensing circuit has a first voltage amplifier which generates a first output voltage, and a plurality of current amplifiers which receive the first output voltage and generate a plurality of first output currents in response thereto. The circuit also comprises a dummy cell, a second voltage amplifier connected thereto for generating a second output voltage. A second current amplifier receives the second output voltage and generates a plurality of second output currents in response thereto. Each of a plurality of inverters receives one of the first and one of the second output currents, and generates an output. The output of the plurality of invertors are supplied to a decoder to generate a decoded signal representative of the plurality of states of the selected memory cell.

Abstract: The present invention discloses a precharge circuit for preventing undesired output pulses caused by the current sensing circuit of the flash memory devices. The access time of the read-cycle also can be decreased after the undesired output pulses are completely removed. Basically, the circuit disclosed by the invention encompasses the current mirror and the cell array as conventionally; a control circuit, a voltage detector and a precharge circuit to remove the undesired output pulses. The control circuit couples with the current mirror, the voltage detector, and the precharge circuit. The current mirror is used to generate output waveform. The precharge circuit couples with the cell array with a bit line, and pre-charges the voltage level of the bit line to a predetermined expected value. The control circuit controls the precharge circuit to precharge the bit line when the read-cycle starts. Whole the current sensing circuit keeps disable until the voltage level of the bit line rises to an expected value.

Abstract: A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

Abstract: A current sense circuit (100) for providing an output signal (Iout) representative of a current signal (Id) flowing through a FET output device (101) comprises a first transistor (102) for providing an image current signal (I.sub.m) which is substantially proportional to the current signal flowing through the FET output device (101) until the drain-source voltage signal of the FET output device (101) is less than a predetermined voltage and a second transistor (104) coupled to a control electrode of the first transistor (102) and for coupling to the gate electrode of the FET output device (101). The first (102) and second (104) transistors are matched and have the same threshold voltages as that of the FET output device (101). The second transistor (104) provides a correction current signal (I.sub.c) when the drain-source voltage signal of the FET output device (101) is less than the predetermined voltage.

Abstract: An improved differential source follower with negligible input/output mismatch over a wide range of input signal magnitudes. A pair of FETs and current sources provides bias current control for each differential output that cancels the inherent body-source voltage variation of the source followers which acts to attenuate the unity gain output signal.

Abstract: In a sense amplifier including an amplifier circuit for amplifying a difference in potential between data lines, an amplifier circuit activating circuit for receiving a sense start signal to activate the amplifier circuit and receiving a sense end signal to deactivate said amplifier circuit, a first sense detecting circuit for determining whether or not the amplifier circuit is activated in accordance with a first output voltage thereof and generating a first sense detection signal, a second sense detecting circuit for determining whether or not the amplifier circuit is activated in accordance with a second output voltage thereof and generating a second sense detection signal, and a sense end signal generating circuit for receiving at least one of the first and second sense detection signals and generating the sense end signal when a predetermined time has passed after at least one of the first and second sense detection signals is received, a masking circuit is connected between the first and second sense de

Abstract: The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.

Abstract: In a sense amplifier circuit, a CMOS inverter is connected to a power supply voltage and inverts and amplifies a voltage on a digit line connected to a selected memory cell of a memory cell section to generate a gate control signal. The first transistor is connected to the digit line and controls current flowing through the digit line in response to the gate control signal. A data of the selected memory cell is outputted from an output of the first transistor. A stabilizing section stabilizes an operation of the CMOS inverter such that a same operation of the CMOS inverter can be performed independent from change of the power supply voltage.

Abstract: A monolithic integrated sensor circuit is disclosed comprising a sensor system for generating an electronic sensor signal; a supply unit for the sensor system; an amplifying stage for amplifying the sensor signal; a plurality of inverting devices in the signal path of the amplifying stage which reverse the polarity of the sensor signal at equal time intervals, the time intervals and inversion of the sensor signal being controlled by a clock signal source; and an averaging combiner stage whose input receives an amplified sensor signal and whose output has a reference polarity which is controlled by means of the inverting devices in such a way as to be always the same regardless of the switching state in the signal path. The monolithic integrated sensor circuit of the present invention minimizes the offset error.

Abstract: The data bus interface apparatus (243) which interfaces between one of a plurality of peripheral units (111) and a data bus (109). The data bus interface driver (243) is capable of biasing data to the voltage level of the data bus (109), accepting data signals (233) having different amplitudes and is immune to differences in ground voltage potentials caused by induced noise and differing environmental conditions. The data bus interface driver (243) is capable of data transition rates in excess of 1 MHz and has low EMI and RFI emissions.

Abstract: A self timed precharge sense amplifier for allowing high speed reading of a memory cell of a memory array. The self timed precharge sense amplifier uses a precharge device for generating an output voltage which is used to ramp up a voltage level of a column of the memory array where the memory cell is located. State control circuitry is coupled to the precharge device for activating and deactivating the precharge device. A sense amplifier is coupled to the precharge device and to the state control circuitry for monitoring the output voltage of the precharge device and for signalling the state control circuitry to deactivate the precharge device when the output voltage has reached a threshold voltage level set by the sense amplifier which is a minimum amount of voltage required to properly read the memory cell.

Abstract: A sense amplifier with improved compensation for clock skew effects is provided and includes a sense amplifier enabling mechanism for receiving first and second control signals. The sense amplifier further includes a first logic mechanism for providing the first control signal to a first input of the sense amplifier enabling mechanism, and a second logic mechanism for providing the second control signal to a second input of the sense amplifier enabling mechanism, wherein the first and second logic mechanisms reduce speed degradation by minimizing skew between the first and second control signals. In a method aspect, a method for reducing speed degradation in a sense amplifier includes providing a pull down device, and coupling the pull down device to first and second signal paths, the first signal path propagating a first clock signal and the second signal path propagating a second clock signal, for reducing speed degradation resulting from skew between the first and second clock signals.

Abstract: A single ended bit line sensor includes a single ended bit line input, a sensor output, an inverting amplifier, a non-inverting amplifier and a differential amplifier. The inverting amplifier is coupled to the single ended bit line input and has a first voltage output. The noninverting amplifier is coupled to the single ended bit line input and has a second voltage output. The differential amplifier has first and second amplifier inputs coupled to the first and second voltage outputs, respectively, and has an amplifier output coupled to the sensor output.

Abstract: A sensor device includes a voltage-to-pulse-number converter having a timing controller. When power is supplied to the converter from a power circuit through a power line, a timer circuit inhibits itself from performing a control operation until operations of a sensor and an amplifier become stable. After a predetermined period of time has passed, the inhibition of the controls is canceled. Then, an analog-to-digital (A-D) conversion of an output of the amplifier by the A-D converter is performed. Subsequently, a counter counts down from a value obtained from the A-D conversion. When the output of the counter becomes 0, the operation of the counter is stopped. Clock signals used for the operation of the counter are input to the pulse output circuit which is enabled only when the counter operates. Thereby, the timing controller outputs to an event counter a pulse signal having a number of pulses proportional to an output of the sensor. The sensor device obtains high precision data.

Abstract: A line amplifier for static RAM memory in CMOS technology comprises first and second branches formed by a first plurality of transistors (TP.sub.1, TN.sub.1, TN.sub.2) and a second plurality of transistors (TP.sub.2, TN.sub.3, TN.sub.2), respectively. The branches are connected in series between the power supply (Vdd) and reference voltage (Vss). A positive feedback is produced by direct connection through internal nodes, and an evaluation switching transistor makes it possible to equalize the values of the voltages on the internal nodes at equilibrium. Under read control (CL), the transistor (TN.sub.2) makes it possible to amplify the preliminary difference between voltage levels due to a transition of the bit signal (D) and complemented bit signal (D) applied to the internal nodes. A precharge transistor (TN.sub.4) is common to the first and second branches and thus allows an increase in switching speed.

Abstract: A sense amplifier of a semiconductor memory device which increases a voltage difference between a bit line and a dummy line is disclosed. The sense amplifier includes: a sense amplifying unit which pre-charges voltages of a dummy line connected to a dummy cell and of a bit line connected to a memory cell by a first equalizing signal, and which senses and amplifies data from the memory cell by inputting the voltages of the dummy line and the bit line by a sense amplifier enable signal; and a voltage variable unit which adjusts the voltages of the dummy line and the bit line by a second equalizing signal, said voltage variable unit having a first voltage variable part which adjusts the voltage of the dummy line by the second equalizing signal and a second voltage variable part which adjusts the voltage of the bit line by the second equalizing signal.

Abstract: The present invention provides a sense amplifier in a semiconductor device, comprising a detector for enabling the sense amplifier in response to the output thereof and disabling the sense amplifier in response to the increase of the output thereof, whereby the detecting means disables the sense amplifier when the output voltage from the sense amplifier increases up to a predetermined voltage level. The sense amplifier prevent data error from being generated and decrease power consumption by using the outputs thereof when the outputs thereof increases to a constant level.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: A signal generator produces enable signals for bitline sense amplifiers in a semiconductor device. The signal generator includes a first driving element for producing a first enable signal at a first output line in response to first and second control signals, a second driving element for producing a second enable signal at a second output line in response to inverted signals of the first and second control signals, and an equalizing element connected between the first output line and the second output line for equalizing the first and second output lines in response to a third control signal. A control signal generating element generates the first, second, and third control signals, and inverted signals thereof, in response to predetermined input signals. The DC current generated from an output driver and the charging and discharging current of output loading can be reduced, to thereby reduce power consumption.

Abstract: A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

Abstract: A sense amplifier senses a small voltage differential across true and complementary digit lines in a dynamic random access memory (DRAM) integrated circuit. The sensed voltage is further separated and amplified into full logic levels. Activating the P-sense amplifier before the N-sense amplifier speeds sensing. The P-sense amplifier control signal is capacitively coupled to each of the true and complementary digit lines. The P-sense amplifier further increases the more positive digit line to the power supply voltage V.sub.cc. The other digit line is at a voltage more positive than its equilibration voltage, speeding conduction of a subsequently activated N-sense amplifier, particularly for low values of V.sub.cc, in which the threshold voltages of the NFETs in the N-sense amplifier are close to the equilibration voltage. Capacitor elements need not be added to the sense amplifier layout.

Abstract: A circuit for a low voltage sense amplifier obtains a faster test time in designing a circuit because a conventional sense amplifier adopting voltage 3.3V can be applied to a semiconductor memory device requiring a potential of less than 1.0V, and prevents current leakage at a low threshold voltage by providing source voltage to a sense amplifier of a selected memory cell array in an active mode as well as in a standby mode.

Abstract: An improved single ended dynamic sense amplifier circuit for sensing the state of a bitline in a read only memory is disclosed which includes a threshold control circuit coupled to a noise margin circuit and a discharge circuit. A sense node couples the discharge circuit to a precharge circuit and an output circuit. The threshold control circuit maintains a bias on the discharge circuit such that during the precharge phase of operation, the discharge circuit is shut off and then conditionally turned off and on. The inclusion of the threshold control circuit in the disclosed single ended dynamic sense amplifier circuit provides for fully functional operation at supply voltages of close to 1.0 volt.

Abstract: Precharge circuits precharge plural pairs of bit lines to a specified potential when no word line is selected (during standby). Pull-down transistors are turned ON when the corresponding word lines are not selected so as to connect the corresponding word lines to a common power source line, which is connected to the ground. In a path connecting the above common power source line to the ground is disposed an impedance changing means for changing the impedance of the path between a value during standby and another value during operation during which any word line is selected so that the value during standby is set higher than the value during operation. Consequently, during standby, a leakage current (standby current) resulting from a short circuit between a bit line and a word line is reduced.

Abstract: A programmable logic device (PLD) is presented having an improved sense amplifier. The sense amplifier comprises a cascode-connected pair of transistors coupled between a sense amplifier output and a virtual ground. According to several embodiments, a clipping transistor and a current-channeling transistor can be provided with the sense amplifier to improve its operation. Further, additional current source and current sink transistors can also be added to the sense amplifier design. The clipping transistor helps ensure that any positive-going noise spikes do not deleteriously effect accurate readings of the true value on the input bit line. The current-channeling transistor helps prevent collapse of the bit line caused by significant conductivity of cells connected to the bit line. The combination of clipping and current-channeling provide a relatively narrow voltage range of the bit line voltage, resulting in fast recovery and high speed sensing thereof.

Abstract: An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines.

Abstract: In a semiconductor memory device, a row decoder is connected to a plurality of word lines to select one of the plurality of word lines in response to a row address. A word line driving section drives, in response to a row address strobe signal, the selected word line to a first potential higher by a predetermined potential than a predetermined second potential, for a read or write operation to a selected memory cell connected to the selected word line and a selected pair of bit lines. The second potential is higher than a power supply higher side potential. A sense amplifier activating section issues sense amplifier activating signals for the write operation to the selected memory cell in response to a sense control signal such that a data having a potential higher than the power supply higher side potential can be written or rewritten in the selected memory cell.

Abstract: A signal transmission circuit suitable for a memory device includes a signal generating section for generating a data signal from a power source, a pair of signal transmission lines for transferring the data signal by transferring signal charge associated by the data signal, an amplifying section for amplifying the data signal transferred by the signal transmission lines, and a precharge section for precharging the output of the signal generating section, the pair of signal transmission lines and the output of the amplifying section to a median potential level between the potential levels of the power source. The precharge section provides power saving as well as a larger noise margin.

Abstract: A pull-down circuit in a sense amplifier, such a sense amplifier in a memory integrated circuit, includes a pull-down transistor having a drain coupled to a common node, a gate, and a source coupled to ground. An inverter provides a gate control signal to the gate of the pull-down transistor. A choke transistor has a drain coupled to a power terminal of the inverter, a gate, and source coupled to the power supply voltage. A regressive drive bias circuit is coupled to the gate of the choke transistor and provides a relatively low voltage to the gate of the choke transistor at relatively low power supply voltages resulting in a relatively large gate-to-source voltage on the choke transistor and provides a relatively high voltage to the gate of the choke transistor at relatively high power supply voltages resulting in a relatively small gate-to-source voltage on the choke transistor.

Abstract: A memory cell comprising a storage cell and a comparison circuit. The storage cell has a second node and a third node. The comparison circuit is coupled to the storage cell and comprises a first plurality of transistors coupled in series to a first input and a second plurality of transistors coupled in series to a second input and coupled to the first plurality of transistors by a first node and by a source voltage node. A match line coupled to the first node indicates a miss when values on the first and second inputs are different than values stored in the storage cell.

Abstract: A amplifier coupled to first and second power supply lines includes a first pair of cross-coupled transistors connected to the first power supply line and a pair of output terminals, and a second pair of cross-coupled transistors connected to the second power supply line. The amplifier includes a reset circuit which is provided between the first and second pairs of cross-coupled transistors and shortcircuits the pair of output terminals in response to a pair of predetermined control signals. The amplifier includes a pair of input transistors connected to the second pair of cross-coupled transistors, and a pair of non-linear elements which are provided between the first and second pairs of cross-coupled transistors.

Abstract: A semiconductor memory device includes a memory cell, a word line, a bit line pair having a first bit line and a second bit line complementary to the first bit line, a p type well, first and second source lines, a source line precharge circuit for precharging the first and second source lines, a sense amplifier connected between the first and second bit lines, driven by the first and second source lines and including first and second n channel MOS transistors formed in the p type well and third and fourth p channel MOS transistors, a first sense amplifier enable transistor connected between a power supply potential node and the first source line, a second sense amplifier enable transistor connected between a ground potential node and the second source line, and a switching circuit connected between the first source line and the p type well, and turning on in response to a control signal when the sense amplifier is active.

Abstract: A multi-channel readout chip is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge amplifiers with self trigger and calibration capabilities to provide timing information with better than 20 nanosecond precision. The trigger threshold can be adjusted to provide energy discrimination. The chip has a sparse readout function in which only the channels which have received signals greater than a preselected threshold value are readout, thus providing fast data acquisition capabilities.

Abstract: P channel MOS transistors P11 and P12 have their gates cross-connected to their drains. P channel MOS transistors P13 and P14 each having its gate and its drain diode-connected to each other are respectively connected in parallel to transistors P11 and P12. N channel MOS transistors N15 and N16 drive transistors P11 to P14 with current values corresponding to input signals IN and /IN. If transistors P11-P14 have the same gate length, transistors P11 and P12 have the same gate width, and transistors P13 and P14 have the same gate width, the DC amplification factor of an internal differential amplifying circuit 1100 of a first stage can be set to a desired value by the ratio of a gate width of P13 to a gate width of P11. Internal outputs from nodes to which the drains of P11 and P12 are respectively connected are input to an internal differential amplifying circuit 1200 of the following stage.

Abstract: A sense amplifier comprising a data refresh amplifier for supplying voltages to true and complementary bit lines in response to a first control signal to amplify true and complementary data on the true and complementary bit lines, respectively, a first transistor for amplifying current of the true data on the true bit line in response to a second control signal and transferring the amplified true data to a true input/output line, a second transistor for amplifying current of the complementary data on the complementary bit line in response to the second control signal and transferring the amplified complementary data to a complementary input/output line, a first switch for selectively forming a current path between the true input/output line and the true bit line, and a second switch for selectively forming a current path between the complementary input/output line and the complementary bit line.

Abstract: A semiconductor integrated circuit device includes a voltage drop circuit for generating a dropped voltage from a power supply voltage externally supplied to a power supply line, and a plurality of circuits respectively connected to the voltage drop circuit and driven by the dropped voltage. A switching unit, which is connected to at least one of the circuits, connects the power supply line to the above one of the circuits in synchronism with operation of the above one of the circuits. The above one of the circuits is driven by currents from both the voltage drop unit and the power supply line in synchronism with the operation thereof.