Abstract: A device according to the invention includes memory cells and a current sense amplifier. It also includes a feedback circuit to adjust a gain of the current sense amplifier. The gain is adjusted depending on relative delays of data stored in different ones of the memory cells to be read on the current sense amplifier.

Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.

Abstract: A method and apparatus for mitigating the hysteresis effect in a sensing circuit used in the evaluation of a property of a system under test. A state monitor circuit is included for detecting the sensing circuit's state upon evaluating the system's property, e.g., a data out signal level. A feedback control generator is provided for generating a control signal operable to transition the sensing circuit's state to a balanced state, wherein the control signal's logic state is capable of being modified substantially immediately upon completion of the evaluation operation.

Abstract: The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset.

Abstract: A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: New sensors and different embodiments of multi-channel integrated circuit are provided. The new high energy and spatial resolution sensors use both solid state and scintillator detectors. Each channel of the readout chip employs low noise charge sensitive preamplifier(s) at its input followed by other circuitry. The different embodiments of the sensors and the integrated circuit are designed to produce high energy and/or spatial resolution two-dimensional and three-dimensional imaging for widely different applications. Some of these applications may require fast data acquisition, some others may need ultra high energy resolution, and a separate portion may require very high contrast. The embodiments described herein addresses all these issues and also other issues that may be useful in two and three dimensional medical and industrial imaging.

Abstract: A sense amplifier circuit for sensing data fed to its data input terminal and operating on the data according to a pre-charge signal, a latch signal and a sense amplifier enable signal. The sense amplifier circuit includes a pre-charge sense circuit that receives data from a data input terminal and outputs a first output value as well as a latching circuit that receives the first output value and outputs a second output value within a preset period. The pre-charge sense circuit further includes a first circuit and a second circuit. The first circuit is capable of pre-charging the data input terminal to a preset potential level. The second circuit produces a first output value according to the input data. In addition, the first circuit and the second circuit are connected in parallel between a voltage source and a data input terminal.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.

Abstract: The semiconductor integrated circuit includes a first transistor which flows a current from a high voltage source to a first node, a second transistor which flows a current from the first node to a low voltage source. Furthermore, a first inverter receives an input signal and drives the first node based on this input signal, and a second inverter drives a second node based on a voltage of the first node.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: A sense amplifier (40) uses a body shorting device (60) to selectively electrically short circuit the bodies of two transistors (44, 48) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifier's outputs.

Abstract: An integrated semiconductor circuit is described and has a semiconductor memory configuration embedded in a semiconductor chip and an interface circuit. The interface circuit is set up for the connection and transfer of data and control signals between the semiconductor memory configuration and a circuit periphery surrounding the memory configuration. The interface circuit is configured as a standard interface for all types of integrated semiconductor circuits with an embedded semiconductor memory configuration for the largest bit width that can be realized in the semiconductor memory configuration. A switch configuration is provided which switches off bits of the standard interface that are unused for smaller bit widths.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A semiconductor memory device capable of preventing coupling noise being generated between adjacent bit lines in different columns. The device comprises first and second columns, wherein each column comprises a pair of bit lines, and wherein the first and second columns are adjacent, first and second sense amplifiers, each being connected to the bit lines of the first or second column, for sensing and amplifying a voltage difference between the bit lines of the first or second column, and a control circuit for controlling the first and second sense amplifiers. When the voltages of adjacent bit lines of the first and second columns transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifiers to concurrently amplify the voltages of the adjacent bit lines.

Abstract: A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.

Abstract: A sense amplifier drive circuit has a sense amplifier amplifying data carried on a bit line and a bit line bar, a sense amplifier drive unit selectively applying an overdrive voltage or an internal power supply voltage to the sense amplifier, and a control signal generator combining a sense amplifier enable bar signal and a refresh enable signal, and generating control signals to control the sense amplifier drive unit. With the construction, an overdrive voltage is not supplied to the bit line and bit line bar during a refresh operation, and current consumption inevitably occurring during the refresh operation is much reduced.

Abstract: A method and apparatus for sensing logic signals is described. A single-ended sense amplifier may include a differential input with a data input transistor and a dummy input transistor. A controlled offset in the size of the data input transistor and the dummy input transistor may increase noise immunity and other performance attributes. A dummy complimentary path may include a partial set of complimentary transistors to a data set of transistors.

Abstract: A new current sense circuit is achieved. The circuit comprises, first, an output transistor having gate, source, and drain. The drain is coupled to a load, the source is coupled to a power rail, the gate is coupled to a control voltage such that the output transistor conducts an output current. Second, a sense transistor has gate, source, and drain. The source is coupled to the power rail and the gate is coupled to the control voltage. A sensing factor comprises the output transistor size divided by the sense transistor size. Third, a means of equalizing the sense transistor drain-to-source voltage and the output transistor drain-to-source voltage is used such that the sense transistor drain current comprises the output current divided by the sensing factor. Finally, a current controlled oscillator is included. The current controlled oscillator has input and output. The input comprises the sense transistor drain current.

Abstract: A selection circuit is provided for first and second latch circuits which operate in response to first and second operation timing signals, respectively. By the selection circuit, a first operation of transmitting a signal corresponding to a first output signal of the first latch circuit to a third output terminal, and a second operation of transmitting a second output signal in place of the first output signal to the third output terminal when the first output is different from the second output signal of the second latch circuit are performed. The second operation timing signal is generated behind the first operation timing signal, and the operation period of the second latch circuit is shortened as necessary in the first operation.

Abstract: Complementary data line driver circuits conserve power by evaluating data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. These devices and circuits include first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair against new data to be provided to the data line pair. Based on the comparison and determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data in two steps. The first of the two steps includes transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair, preferably for a duration sufficient to substantially equilibrate voltages on the first and second data lines.

Abstract: A method and apparatus for mitigating the hysteresis effect in a sensing circuit used in the evaluation of a property of a system under test. A state monitor circuit is included for detecting the sensing circuit's state upon evaluating the system's property, e.g., a data out signal level. A feedback control generator is provided for generating a control signal operable to transition the sensing circuit's state to a balanced state, wherein the control signal's logic state is capable of being modified substantially immediately upon completion of the evaluation operation.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of signal values applied to the N inputs. The comparator includes a first comparison circuit, such as a sense amplifier, having inputs for receiving a subset of the N signal values, such as a pair of the inputs. The comparator also includes a first multiplexer having a select signal input coupled to an output of the first comparison circuit, and inputs coupled to the subset of the N signal values. The comparator further includes N-2 additional comparison circuits and N-2 additional multiplexers, with the N-2 additional multiplexers coupled to corresponding ones of the N-2 additional comparison circuits. The comparison circuits and multiplexers are arranged to select a particular one of the N signal values, e.g.

Abstract: A bit line sense amplifier is provided. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers, which are arranged outside the plurality of first sense amplifiers, for pulling down the bit line or the complementary bit line to a first voltage level. The bit line sense amplifier further includes a second sense amplifier block with a plurality of second sense amplifiers and second drivers for pulling up the bit line or the complementary bit line to a second voltage level. By arranging the drivers outside the bit sense amplifiers, effects caused by variation in critical dimensions (CDs) of gates are minimized and the entire area of the bit line sense amplifier is reduced.

Abstract: An apparatus and method for processing a data input signal with a single ended sense amplifier. The single ended sense amplifier includes a transmission gate circuit and a control circuit coupled between a feedback inverter circuit and an output signal that is fed back to the feedback inverter circuit. An inverter circuit is coupled between an enable signal and the transmission gate and control circuits. During pre-charge operation, the input to the feedback inverter circuit is driven to a first state. The feedback inverter correspondingly drives the input signal to a sensing inverter to a state that is complementary to the input to the feedback inverter circuit, thereby assisting the pre-charge mode and substantially reducing time delay due to the input signal contending with the feedback inverter circuit. One advantage of the present invention is that sense amplifiers can be sized for faster sensing than would other-wise be feasible due to the excessive contention during the pre-charge mode.

Abstract: A fuse circuit according to the present invention includes fuse elements each connected to first and second nodes, a sense circuit for sensing a difference of currents flowing through the fuse elements, and an amplifier circuit for amplifying voltages of the first and second nodes with rail-to-rail voltages, respectively. By this configuration, the resistor difference of the fuse elements is sensed by a current difference, thus whether a fuse element is programmed is exactly sensed regardless of capacitive parasitic loading of the respective nodes.

Abstract: A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: A current mirror sense amplifier, with a two-stage current mirror, a first transistor, and a second transistor. The first transistor and the second transistor each have first and second connection terminals. The current mirror has a current input terminal and a current output terminal. The first transistor has a gate electrically connected to a pre-charge voltage. The first connection terminal of the first transistor is electrically connected to a reference voltage. The second transistor has a gate electrically connected to a reference signal. The first connection terminal of the second transistor is electrically connected to the reference voltage. The second connection terminals are connected to the current output terminal in parallel.

Abstract: A sense-amplifying circuit 10 which comprises a pair of inverters (TP0, TN0, TP1 and TN1), wherein an output of each inverter is connected to an input of the other inverter, drains of sensing transistors TN2 and TN3 are respectively connected to each source of the pair of inverters in series, the gates of both sensing transistors TN2 and TN3 are connected to differential input signal lines 12 and 14, and the sources of both sensing transistors TN2 and TN3 are connected through a common node with a transistor TN4, which works not only as a constant current source but also as an operation switch for the sense-amplifying circuit.

Abstract: A method and apparatus for mitigating the history effect in silicon-on-insulator (SOI)-based circuitry, e.g., data interface circuitry operable as a single-ended off-chip signal receiver in a VLSI component such as a microprocessor. A sense amplifier (sense amp) latch circuit arrangement includes a sense amp operable to sense data and a latch operable to hold the sensed data. When data is available, the sense amp generates a pair of complementary data signals responsive to a control signal used for alternating the sense amp's operation between an evaluation phase and an equilibration (i.e., pre-charge) phase. A feedback circuit portion is operable to modify the control signal's logic state within a clock phase associated with one of the two complementary clocks provided to the interface circuitry. Since the equilibration phase is entered combinationally off the evaluation phase, both evaluation and equilibration can be triggered from the same clock edge.

Abstract: A signal amplification circuit according to the present invention includes a current comparison part for generating a voltage in accordance with the difference between the reference current and the memory cell current at the first node and an output level setting part for generating an output signal,at the second node. The output level setting part has the first transistor for supplying a constant current in accordance with the control voltage from the power supply node to the second node and the second transistor for allowing the current in accordance with the voltage of the node to flow from the second node to the ground node. The current which flows through the second transistor is designed to be in balance with the constant current under the condition where the reference current and the memory cell current are in balance.

Abstract: A sense amplifier circuit including a current difference amplification circuit and a voltage difference amplification circuit, and a precharge circuit for precharging digit lines, are provided between the digit lines. A memory cell including one transistor and one capacitor is connected to the digit line. The voltage difference amplification circuit includes an n-channel flip flop and a p-channel flip flop, and is provided with nodes. The nodes are connected to the digit lines via a sense amplifier connection circuit.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a sense amp connected to a plurality of bit lines with bit line transistors. Each of the bit line transistors may be connected to a sense amp enable transistor so that together, the coupling and sense amp enable transistors connect the sense amp to a power supply voltage.

Abstract: A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: A stabilized direct sensing memory architecture which provides Process, Voltage and Temperature (PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal superimposed on a bitline precharge voltage. A mimic bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.

Abstract: A sense amplifier (10) is disclosed comprising: a connecting node (12) connectable to a plurality of logic cells (13) for reading the logic states thereof; at least one output (16, 18, 20); circuitry (14) for transferring the read logic states from the connecting node (12) to the at least one output; and a circuit (50) dynamically operative to limit the voltage at the connecting node (12) substantially to a predetermined voltage. In one embodiment, the circuit (50) includes a pass transistor (46) coupled between the connecting node (12) and the transferring circuit (14) and operative to conduct the logic states read from the logic cells to the transferring circuit; and a capacitive divider circuit (54, 56) coupled to a voltage source (Vdd) for producing at a node (52) thereof the predetermined voltage as a fraction of the voltage of the source, the node (52) being coupled to the pass transistor (46) to limit the voltage at the connecting node (12) substantially to the predetermined voltage.

Abstract: A sense amplifier drive circuit has a sense amplifier amplifying data carried on a bit line and a bit line bar, a sense amplifier drive unit selectively applying an overdrive voltage or an internal power supply voltage to the sense amplifier, and a control signal generator combining a sense amplifier enable bar signal and a refresh enable signal, and generating control signals to control the sense amplifier drive unit. With the construction, an overdrive voltage is not supplied to the bit line and bit line bar during a refresh operation, and current consumption inevitably occurring during the refresh operation is much reduced.

Abstract: A sense amplifier circuit includes a first voltage-controlled current source to supply current proportional to a first bias voltage to a reference node and a second voltage-controlled current source to supply current proportional to a second bias voltage to a sensing node. The first and second bias voltages are internally generated in response to an externally applied sense amp control signal. A current mirror circuit is also provided for the sense amplifier circuit. The current mirror circuit commonly deliver current proportional to the voltage level of the reference node to the reference and sensing nodes. A differential amplifier amplifies a difference voltage between reference and sensing nodes.

Abstract: In an integrated circuit, a data link relies on low swing differential signals. A push-pull driver circuit and a receiver circuit are both clocked from a common on-chip clock. A driver circuit includes an H-bridge of NMOS transistors and a line-to-line precharge circuit which reduces the power requirements of the circuit. A clocked repeater within the link may itself comprise a clocked receiver and an H-bridge driver with line-to-line precharge.