Abstract: A semiconductor device includes a monitor voltage transfer unit and a voltage generating unit. The monitor voltage transfer unit selects one of a plurality of internal voltages including a cell plate voltage in accordance with a test mode to output it to a voltage monitor pad or outputs an external voltage supplied from the voltage monitor pad as a first pre cell plate voltage. The voltage generating unit generates the cell plate voltage using any one of the first pre cell plate voltage and a second pre cell plate voltage generated within itself in accordance with the test mode. The semiconductor device can generate a pre cell plate voltage at the desired level.

Abstract: The present invention discloses an electronic device and related method for performing a compensation operation on an electronic element, wherein the electronic device includes: a control module, for outputting a control signal according to an input signal; a driver module, coupled to the control module and the electronic element, for providing a driving current to the electronic element according to the control signal; a sensor module, for outputting at least a sensor signal according to a variation of an operation environment; a compensation control module, coupled to the sensor module, for outputting at least a compensation control signal according to the at least a sensor signal and the input signal; and a compensation driver module, coupled to the electronic element and the compensation control module, for providing at least a compensation driving current to the electronic element according to the at least a compensation control signal.

Abstract: A method is provided for improving the performance of a circuit containing a three-terminal device. In the operation of a circuit containing three-terminal device 10, the influence of the Early effect pertaining to the three-terminal device of a FET is reduced. In order to reduce the influence, control unit 30 is set for reducing the Early effect component caused by a three-terminal device. As a result, by controlling the potential of the second terminal (such as drain) of the device as a response to a first signal pertaining to the input signal received by the first terminal (such as gate) of the device, it is possible for the potential difference between the second terminal (drain) and the third terminal (such as source) of the device to be essentially constant.

Abstract: Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal.

Abstract: The objective of the present invention is to present a buffer circuit by which a load can be driven at a high speed while restraining an increase in power consumption. A current input to npn transistor Q1 via node N1 is detected by current detection circuit 1. At bias control circuit 2, base voltage of npn transistor Q2 is regulated in such a manner that the current of npn transistor Q2 decreases in accordance with an increase in said detected current, and the current of npn transistor Q2 increases in accordance with a decrease in the detected current. As a result, because transient current which can flow to the load can be increased, even when load capacitor CL has a large capacitance or when the frequency is high, the output voltage can quickly follow a change in the input voltage, so that distortion of the output voltage waveform can be restrained.

Abstract: A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed.

Abstract: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at a reference point may be determined based on the applied reference voltage, and a maximum and/or minimum voltage may be determined based on the internal voltage. A plurality of output transistor devices may be controlled based on either the maximum voltage or minimum voltage. The reference voltage may be modified based on controlling the plurality of output transistor devices. By turning ON and OFF the output transistor devices, a much wider operating range is facilitated.

Abstract: A CMOS reference current source comprises two circuit branches connected in parallel between supply terminals. The first circuit branch includes a series connection of a bias current source (MP1) and a first MOS transistor (MN1) of a first conductivity type. The second circuit branch includes a series connection of a diode-connected MOS transistor (MP2) of a second conductivity type, a second MOS transistor (MN2) of the first conductivity type and a third MOS transistor (MN3) of the first conductivity type. The first MOS transistor (MN 1) of the first conductivity type has its gate connected to the drain of the third MOS transistor (MN3) of the first conductivity type. The second MOS transistor (MN2) of the first conductivity type has its gate connected to the drain of the first MOS transistor (MN1) of the first conductivity type. The third MOS transistor (MN3) the first conductivity type has its gate connected to a bias source (MN4).

Abstract: A disclosed self regulating biasing circuit (SRBC) includes an unregulated node that couples to an unregulated power supply that produces a supply voltage. An impedance element of the SRBC carries an unregulated current having a nominal component and a variance component between an unregulated node and a regulated node. A detection circuit connected between the unregulated node and a third node detects a variance component of a supply voltage and generates a detection current based on the variance component. A compensation circuit connected to the third node draws a compensation current, based on the detection current, from the regulated node. The SRBC is designed wherein the compensation current is approximately equal to the variance component of the unregulated current. The regulated node may be connected to a control terminal of a transistor to be biased.

Abstract: In one embodiment, a voltage reference circuit is configured to use two differentially coupled transistors to form a delta Vbe for the voltage reference circuit.

Abstract: A band-gap reference voltage generator is provided that is capable of being used at low voltage simultaneously with adjusting a reference voltage.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: A circuit for generating a reference voltage at an output node comprises a first branch, a second branch, and a main current source. The first branch is electrically connected between a first terminal and a second terminal of the circuit, and comprises at least one first semiconductor device. Each first semiconductor device comprises a first node and a second node. The second branch is electrically connected between the first terminal and the second terminal of the circuit, and comprises at least one second semiconductor device and a branch current source. Each second semiconductor device comprises a first node and a second node. The branch current source is serially connected to the second transistor. The main current source is electrically connected to one of the first terminal and the second terminal of the circuit. The output node is in the first branch or the second branch.

Abstract: A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: The present invention provides a current control apparatus applied to a transistor. The transistor has a control terminal, a first terminal, and a second terminal. The current control apparatus includes a current control module, a first current mirror module, a second current mirror module, a current subtractor, and a current adjusting module. The current control apparatus provided by the present invention can be applied to a bipolar junction transistor (BJT) to prevent temperature measurement errors from occurring when using a dual current mode temperature measurement method to measure the temperature of the BJT.

Abstract: A high voltage generator includes a charge pump configured to output a pumping voltage in accordance with a first clock signal and a second clock signal having a level opposed to a level of the first clock signal; a first regulator configured to stabilize the pumping voltage to a voltage having constant level, thereby outputting a first regulation voltage; and a second regulator configured to convert the first regulation voltage into a voltage having constant level, thereby outputting a second regulation voltage. Here, the first regulator increases the pumping voltage by n number so that the first regulation voltage reaches a first level, and the second regulator increases the first regulation voltage by m number so the second regulation voltage reaches a second level smaller than the first level.

Abstract: In some embodiments, regulator circuits are provided.

Abstract: Provided is a discharge circuit. The discharge circuit for discharging two positive and negative high voltages after an erase operation of a non-volatile memory includes: a negative high voltage side discharge unit flowing constant current from a supply voltage to a negative high voltage node of the non-volatile memory to discharge the negative high voltage node; and a positive high voltage side discharge unit flowing constant current from a positive high voltage node of the non-volatile memory to a ground voltage to discharge the positive high voltage node, the positive high voltage side discharge unit simultaneously operating with the negative high voltage side discharge unit, wherein values of the constant currents flowing from the positive and negative high voltage side discharge units are approximately equal.

Abstract: This is a disclosure of a power supply circuit for wall-mounted electronic switches. The disclosed invention is about a power supply circuit for driving circuit inside the wall-mounted electronic switches, which can supply sufficient current demanded by these switch circuits. Recently the functions of wall-mounted electronic switches are being diversified from lamp switching to security, watch, remote control, room temperature control, etc. and the amount of current required inside the switch circuits is increased up to tens of mA. This requires a competitive power supply circuit that can supply a high current. In addition, a space-saving characteristic is also required because the space of a wall-mounted switch is narrow. The invented power supply circuit for electronic switches saves space, supplies a high current, and enhances competitiveness in price and quality, and consequently it makes a considerable contribution to the competitiveness of wall-mounted electronic switches.

Abstract: A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Abstract: A CPU core voltage supply circuit includes a reference voltage generator, a differential operation amplifier, a power element, a feedback circuit and a first capacitor. The reference voltage generator outputs a first reference voltage. The differential operation amplifier has a positive input end, a negative input end and an output end. The positive input end is connected to the reference voltage generator for receiving the first reference voltage. The power element has a receiving terminal and a current output terminal. The receiving terminal is connected to the output end of the differential operation amplifier. The feedback circuit is connected to the current output terminal and outputs a feedback voltage to the negative input end of the differential operation amplifier. The first capacitor has an end connected to the current output terminal of the power element and the other end receiving a first voltage, thereby providing a CPU core voltage.

Abstract: Bias current generation circuits and systems are disclosed. In one embodiment, a bias current generation system comprises a current generation circuit generating a first current based on a first voltage and an external resistor, a current mirror forwarding a second current proportional to the first current, and one or more bias current generation circuits with each circuit generating a bias current based on a second voltage over a resistance of a transistor device, where the transistor device is maintained in a triode region using a third voltage associated with the second current and where the resistance of the transistor device shares characteristics of a resistance of the external resistor.

Abstract: According to an embodiment of the invention, a method and apparatus for DC voltage conversion are described. According to one embodiment, a voltage converter comprises a current mirror, the current mirror being coupled with a power source; a first transistor device coupled with a bias generator to receive a bias voltage; a second transistor device coupled between the current mirror and the first transistor device; and an output transistor device, a gate of the output transistor device being coupled with a gate of the second transistor device and to the current mirror.

Abstract: A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.

Abstract: Provided is a load fluctuation compensation circuit, including a first delay circuitry section that delays a clock signal supplied thereto by a delay amount that fluctuates by a prescribed first fluctuation amount in relation to a unit fluctuation amount of a power supply voltage supplied to a performance circuit; a second delay circuitry section that is disposed in parallel with the first delay circuitry section and that delays the clock signal supplied thereto by a delay amount that fluctuates by a second fluctuation amount, which is greater than the first fluctuation amount, in relation to the unit fluctuation amount of the power supply voltage supplied to the performance circuit; a load circuit that is connected to a common power supply wiring in parallel with the performance circuit; and a phase detecting section that detects a phase difference between the clock signal output by the first delay circuitry section and the clock signal output by the second delay circuitry section and that controls an amount

Abstract: A power-up circuit for reducing a variation in triggering voltage in a semiconductor integrated circuit is described. The power-up circuit includes a pull-up resistor unit that is connected to a power voltage source. A pull-up resistance adjusting unit varies the resistance value of the pull-up resistor unit. The power-up circuit also includes a pull-down resistor unit that is connected between the pull-up resistor unit and a ground. Finally, the power-up circuit includes a detector connected to a common node of the pull-up resistor unit and the pull-down resistor unit.

Abstract: A memory voltage control circuit includes two slots, a control circuit, a voltage conversion circuit, and a switch circuit. The two slots are able to efficiently process different memory types. The control circuit receives memory identification signals from the two slots. The control circuit administers the output voltage of the voltage conversion circuit according to the memory identification signals. The memory identification signals determine whether the switch circuit is to be turned on or off. This will control whether the output voltage of the voltage conversion circuit will go to the first or the second slot.

Abstract: An output circuit includes a constant current circuit that generates and supplies a constant current to an output terminal of the output circuit. Based on the constant current, the output circuit converts an input signal to an output signal having a voltage within a voltage range specified by upper and lower clamp voltages. The output signal is feedback to the constant current circuit. The constant current circuit changes the amount of the constant current in accordance with the output signal in such a manner that the constant current increases with an increase in the output signal and becomes zero when the output signal decreases to or below a threshold voltage. Thus, the upper clamp voltage is made as close to a power supply voltage as possible and the lower clamp voltage is made as close to a ground voltage as possible.

Abstract: A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal.

Abstract: A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

Abstract: In an embodiment, a circuit is disclosed that includes a current mirror including a first transistor pair and a second transistor pair. The first transistor pair includes a first transistor and a second transistor. The second transistor pair includes cascode transistors. The circuit also includes an operational amplifier having an output coupled to both the first transistor and the second transistor.

Abstract: Systems and methods for current management for digital logic devices are provided. In one embodiment, a method of current management for a digital logic circuit comprises drawing power to drive a digital logic integrated circuit; determining a priori information about an impending current need of the digital logic integrated circuit; and controlling a bypass current in parallel with the digital logic integrated circuit based on the a priori information, wherein the bypass current is controlled to reduce discontinuities in the current supplied by a power supply.

Abstract: A leakage current compensated multiplex driver system includes a multichannel mux having a predetermined leakage current at the switched side of each channel and a leakage current compensation circuit associated with the switched side of each channel for providing a compensation current matched to the predetermined leakage current.

Abstract: Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

Abstract: A semiconductor device is disclosed which can perform a stable data inputting operation by overdriving a terminal supplying an internal voltage used as a drive voltage for a write driver such that the internal voltage is maintained in a predetermined range irrespective of a continuous write operation. The semiconductor device includes an internal voltage generator which generates an internal voltage corresponding to a predetermined reference voltage, and outputs the generated internal voltage to an internal voltage supply terminal, an overdriver which overdrives the internal voltage supply terminal for a predetermined period of time in response to an enable state of a control signal, the control signal being enabled in a write operation, and a write driver which is enabled in response to the control signal, to drive data transferred via a global data bus line using a voltage supplied from the internal voltage supply terminal, and to output the driven data to a local data bus line.

Abstract: Disclosed are a power supply circuit for an oscillator of a semiconductor memory device and a voltage pumping device using the same. In the power supply circuit, a voltage divider divides a voltage between an external power supply and ground. A driver is controlled by a signal of the voltage divided by the voltage divider. The driver supplies an internal power supply voltage. A capacitor is coupled between the driver and the ground. As the level of an external power supply voltage is increased, a relatively low voltage is supplied to the oscillator to increase a cycle length of an output pulse signal of the oscillator. Therefore, an excessive increase in the internal power supply voltage due to over-pumping can be avoided and noise occurrence and electric current consumption can be reduced.

Abstract: One embodiment of the invention includes a current mirror system. The system comprises a master circuit configured to conduct a first current in response to an activation state of an activation signal. The system also comprises a slave circuit configured to generate at least one second additional current in response to the activation state of the activation signal. Each of the at least one additional current can be proportional to the first current. The system further comprises a current path circuit that is configured as a substantial copy of the master circuit, the current path circuit being configured to conduct the first current in response to a deactivation state of the activation signal.

Abstract: A slew rate control circuit in output driver of switching circuit to prevent power ground undershoot is introduced. The gate capacitance of lower power transistor is first fast discharged to ensure the operation of the output signal. The gate capacitance of lower power transistor is then slowly discharged to limit OUT SLEW RATE. The gate capacitance of lower power transistor is further slowly discharged when the power ground level is below common ground. With above controlling, the gate voltage slew rate of lower power transistor is reduced when the lower power transistor is almost fully turned OFF. Therefore, undershoot at the power ground is avoided. Similar slew rate control circuit can also be derived in output driver of switching circuit to prevent PVCC overshoot.

Abstract: An embodiment of the present invention is directed to a method of matching currents to a known ratio including generating a control signal from a control circuit, which includes a value that defines a configuration. The method also includes receiving the control signal at a switching circuit, detecting whether the value of the control signal has changed, and, provided the value has changed, switching a plurality of transistors from a first configuration to a second configuration. The first configuration produces a first current in a first circuit and a second circuit, and the second configuration produces a second current in a first circuit and a second circuit. The ratio of the first current and the second current are the aforementioned known ratio.

Abstract: The invention provides an apparatus for adjusting a working frequency of a VRD by detecting temperature. The apparatus includes a temperature control module, a load module and a controller. The temperature control module is used for detecting a temperature of a CPU, and judging an output load state of the VRD according to the detected temperature of the CPU, so as to output a control signal according the output load state. The load module is connected to the VRD, and is used for providing an external resistance to the VRD. The controller is respectively coupled to the load module and the temperature control module, and is used for receiving the control signal and adjusting a resistance of the load module according to the received control signal, so as to adjust a working frequency of the VRD. A power consumption of the VRD may be reduced based on the present invention.

Abstract: An efficient logic chip operating power supply having digital circuits in a multi-chip package is provided. A multi-chip package semiconductor device fabricated in common with a driver chip having analog circuits and a logic chip having digital circuits, a logic chip power supply circuit is provided in which a driver chip creates a logic chip power supply dedicated for the logic chip. The logic chip has internal logic circuitry operating by receiving a power supply from the logic chip power supply circuit via power input terminals.

Abstract: There is provided with a gate drive circuit including: a first switching element connected at one end to a power terminal; a second switching element connected at one end to the other end of the first switching element and connected at the other end to a reference terminal; a gate voltage output terminal which supplies a voltage at a node between the first switching element and the second switching element to a drive switching element as an output gate voltage; a gate voltage monitoring circuit which monitors the output gate voltage; an overcurrent detection circuit which monitors a current through the drive switching element; and a control circuit which generates a control voltage for controlling impedance of the second switching element based on an on/off signal for indicating that the drive switching element should be turned on/off, a gate voltage monitoring signal and an overcurrent monitoring signal.

Abstract: A switching control circuit, controlling a transistor, of a voltage generating circuit generating an output voltage of a target level from an input voltage applied to the transistor, comprising: an error amplifier circuit outputting an error voltage obtained by amplifying an error between a voltage according to the output voltage and a first reference voltage; a first comparison circuit comparing the error voltage with a second reference voltage to output a first control voltage; a second comparison circuit comparing the error voltage with a third reference voltage to output first and second voltages a charging and discharging circuit for charging and discharging a capacitor based on the first and second voltages; a third comparison circuit comparing a charged voltage of the capacitor with a fourth reference voltage; and a control circuit outputting a second control voltage for turning off the transistor according to a result of the third comparison circuit.

Abstract: The present invention discloses a voltage level generating device. The voltage level generating device includes: a reference voltage generating module, a first circuit module, a second circuit module, and a switch module. The voltage level generating device disclosed in the present invention only requires a buffer, a voltage regulator, and a arithmetic logic unit (ALU) to attain the same function of the conventional common voltage level generating device, and thus the circuit layout area can be reduced so as to decrease the cost of the integrated circuit (IC). In addition, the voltage level generating device disclosed in the present invention also can select different output of voltage level in order to reduce the power consumption of a display device.

Abstract: A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference voltages to be refreshed during a standby mode of operation.

Abstract: An apparatus for generating a reference voltage in a semiconductor memory apparatus according includes: a first voltage generating unit configured to generate a voltage proportional to temperature; a second voltage generating unit configured to generate a voltage inversely proportional to temperature; and a reference voltage generating unit including a first adjusting unit connected with the first voltage generating unit and a second adjusting unit connected with the second voltage generating unit, configured to select the first adjusting unit or the second adjusting unit according to a difference between a reference voltage obtained by the first voltage generating unit and the second voltage generating unit and a target voltage, and adjust the reference voltage thereby outputting a constant reference voltage regardless of a variation in temperature.

Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.

Abstract: A power supply includes a first switch to establish a first path to charge an output of the power supply by a voltage source, a second switch to establish a second path to discharge the output, and a third switch connected between the output and a capacitor. When to discharge the output, the third switch is turned on before the second switch turns on, to transfer a portion of energy on the output to the capacitor. When to charge the output, the third switch is turned on before the first switch turns on, to transfer a portion of the energy on the capacitor to the output.

Abstract: An electronic apparatus implemented with capacitance coupling effect compensating capability is disclosed. The apparatus includes a first substrate, a common electrode, a second substrate, a coupling catch structure and a compensating circuit. The common electrode is disposed on the first substrate. The coupling catch structure is disposed on the second substrate and configured to receive a first common voltage and output a coupling catch voltage composed of a DC voltage component and a non-DC voltage component. The compensating circuit is configured to receive the coupling catch voltage and a second common voltage, and output an active common voltage applied to the common electrode. The present invention also includes a capacitance coupling effect compensating method.