Abstract: A semiconductor device is capable of generating an internal voltage having a voltage level that is dependent on an external power supply voltage. The semiconductor device includes an internal voltage generation unit configured to generate a plurality of internal voltages having different voltage levels by using an external power supply voltage, a voltage level detection unit configured to detect a voltage level of the external power supply voltage, and a selection unit configured to selectively output one of the internal voltages in response to a detection result of the voltage level detection unit.

Abstract: A system that includes: multiple transistors that comprise a first transistor that is maintained in a weak inversion state; wherein sources of the multiple transistors are coupled to a low current source; wherein drains of the multiple transistors are coupled to a voltage supply source; a first amplifier that has a positive input, negative input and an output; wherein the positive input receives an input voltage; wherein the negative input is coupled to a source of the first transistor; wherein the output is coupled to a gate of the first transistor and to a multiplication and subtracting circuit; a multiplication and subtraction circuit that is coupled to the first amplifier and outputs an output signal that equals a difference between the input voltage and a product of a current reduction variable and a voltage reduction signal; wherein the voltage reduction signal is associated with a current reduction factor; wherein the output signal is provided to a second transistor that is maintained in weak inversion

Abstract: A circuit arrangement is described for selectively generating an analog current output value or an analog voltage output value as a function of an analog input value. Optionally, the analog current output value or the analog voltage output value may also be a function of an input base value or a signed input correction value. The circuit arrangement includes a current control unit, a voltage control unit, a current output source is triggered by the current control unit, and a voltage output source triggered by the voltage control unit. The current output source and voltage output source of the circuit arrangement may be triggered in parallel and are connected in series on the output side.

Abstract: An amplifying circuit receives an output from a comparator. The output is provided to each gate of first, second and third transistors. First and second resistors are connected in series. The first and second resistors and a first diode are connected to a drain of the first transistor. Second diodes are connected in parallel. The second diodes are connected to one end of a third resistor. The other end of the third resistor is connected to a drain of the second transistor. Fourth and fifth resistors are connected in series. One end of the fourth resistor is connected to the drain of the second transistor. The comparator receives first and second feedback voltages respectively obtained from a connection node between the first and second resistors and a connection node between the fourth and fifth resistors. A drain of the third transistor outputs a reference voltage.

Abstract: An internal voltage generating circuit is capable of controlling an amount of charge pumping according to an external power supply voltage. The internal voltage generating circuit includes a periodic signal generating unit configured to control generation of periodic signals according to a level of an external power supply voltage, and a pumping unit driven according to the periodic signals generated by the periodic signal generating unit.

Abstract: An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit.

Abstract: A disclosed invention is an internal power supply circuit, which generates an internal power supply from a first power supply. The circuit comprises a first internal step-down power supply generation unit, which generates a first internal step-down power supply from the first power supply; a normal second internal step-down power supply generation unit, which generates a second internal step-down power supply from the first internal step-down power supply in the normal operating state, and which, at the time of power supply startup, begins operation to generate the second internal step-down power supply at a first timing at which a voltage of the first internal step-down power supply reaches a prescribed reference level; and, a startup power supply load unit, which begins to consume, before the first time, current from the first internal step-down power supply.

Abstract: There is provided a reference voltage generating circuit generating a reference voltage to be applied to a current-to-voltage converting circuit in order to compensate for an offset voltage of the current-to-voltage converting circuit converting an input current into a voltage and outputting the voltage, the reference voltage generating circuit including: a sampling conversion circuit having the same circuit characteristics as the current-to-voltage converting circuit and adding a predetermined offset to the reference voltage to generate an output voltage; and a comparator controlling the reference voltage so that the output voltage of the sampling conversion circuit is equal to a predetermined voltage, wherein the reference voltage is applied as an input to the sampling conversion circuit.

Abstract: A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate.

Abstract: An internal voltage generating circuit capable of controlling a swing width of a detection signal in a semiconductor memory apparatus is provided. The internal voltage generating circuit of a semiconductor memory apparatus includes an internal voltage level detecting unit configured to compare an internal voltage with a target voltage and then generate a detection signal, and an internal voltage level control unit configured to control the internal voltage based on a voltage level of the detection signal, wherein the internal voltage level detecting unit is configured to control a swing width of the detection signal based on a voltage difference between the internal voltage and the target voltage.

Abstract: Systems and methods for bit stuffing pulse width modulation are provided. Example embodiments of the systems and methods of bit stuffing pulse width modulation disclosed herein may allow for a significant reduction in the size of the bootstrap capacitor while giving up only a small percentage of output drive, and reduce die space. Included in such systems and methods is the ability to digitally detect inactivity on the PMW signals for a class D power amplifier, and to digitally insert small charge pulses at a fairly low repetition rate relative to the normal switching frequency. The low repetition rate may preserve the maximum output power while still allowing enough charge to transfer to the bootstrap capacitor.

Abstract: There is provided an internal voltage generation circuit generating an internal voltage used for a semiconductor memory device. The internal voltage generation circuit includes a current mirror type internal voltage detector generating a comparison voltage and comparing the comparison voltage with a reference voltage to output the comparison result as a detection signal, and a charge pump outputting the internal voltage and controlling the level of the internal voltage by the detection signal. The current mirror type internal voltage detector generates a comparison voltage whose level is determined in accordance with the output of the current mirror having a variable current source in which current varies in accordance the output internal voltage.

Abstract: A power generator system and apparatus that uses a frequency synthesizer in conjunction with an oscillator to lock both frequency of a drive signal with a reference signal. The oscillator center frequency is different from the nominal generator frequency, and as a consequence a variety of reference frequencies may be supported. By using a frequency synthesizer, the oscillator frequency can be locked onto a frequency that is a ratio of the reference frequency. Then, the frequency synthesizer may generate a drive signal that is closely matched to the reference frequency.

Abstract: Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

Abstract: A signal delaying system is provided, including a delay locked loop circuit and a voltage providing circuit. The delay locked loop circuit delays an input signal to generate a delayed signal. The voltage providing circuit provides a control voltage to the delay locked loop circuit for determining a delay time of the delay locked loop circuit when the delay locked loop circuit operates in a first mode; and providing a stand-by voltage to the delay locked loop circuit when the delay locked loop circuit operates in a second mode, wherein the voltage providing circuit further adjusts the stand-by voltage to make the stand-by voltage substantially equal to the control voltage.

Abstract: A circuit and a method for extending the lifetime of a semiconductor chip. The circuit including a voltage reference generator, a voltage switch, a threshold voltage regulator device and a threshold voltage monitor device tunes an automatic internal power supply. The voltage reference generator provides one or more reference voltage levels that are transmitted to the voltage switch. The threshold voltage monitor device monitors the threshold voltage of the device, triggering the voltage switch to select a reference level for use as a voltage reference for the regulator when the threshold voltage of the monitored device exceeds a predetermined value. The regulator then converts the external power supply to an internal supply and holds it at the predetermined reference level.

Abstract: A method of masking a current requirement of an electronic circuit (100) is provided, wherein the method comprises determining a current level required by the electronic circuit (100) and a corresponding point in time said current level is required by the electronic circuit (100), choosing a current level corresponding to a current level which is equal or higher than the determined current level, and switching a current level supplied to/consumed by the electronic circuit (100) to the chosen current level at a time instant deviating from the determined point in time.

Abstract: A bias voltage generation circuit is provided which includes a voltage-to-current translation circuit configured to generate a first current that is positively related to a first voltage. A current mirror circuit is configured to generate a first bias voltage that is negatively related to the first current. The current mirror circuit also generates a second current that is positively related to the first current. Also employed is a current-to-voltage translation circuit configured to generate a second bias voltage that is positively related to the second current.

Abstract: Circuits and methods for providing a temperature insensitive reference current are disclosed. A voltage source is received having a temperature coefficient. A first resistive element having a positive temperature coefficient and a second resistive element having a negative temperature coefficient are series coupled to form a resistor ladder. The reference current is generated by coupling the voltage source across the resistor ladder. The temperature coefficients of the first and second resistive elements are chosen to cancel the temperature coefficient of the voltage source. In another embodiment a temperature compensated voltage source is coupled to a resistor ladder of a first resistive element and a second resistive element, and the first resistive element has a positive temperature coefficient and the second resistive element has a negative coefficient; these cancel to form a temperature insensitive reference current.

Abstract: A bandgap voltage reference circuit includes an operational amplifier, a first transistor, a second transistor, a third transistor, a first resistor, a second resistor, a first diode, a second diode, and a divider. The first transistor, the second transistor, and the third transistor form current mirrors. The reference current of the current mirrors is generated according to the first diode, the second diode, and the first resistor. The reference voltage of the voltage reference circuit is output from the first end of the second resistor. The divider is coupled to the second end of the second resistor so that the reference voltage of the voltage reference circuit can be reduced.

Abstract: An object of the present invention is to eliminate fluctuation in the value of the constant current I even if there is characteristic fluctuation in field effect transistors and at the same time, to improve the power consumption.

Abstract: A voltage generating apparatus is disclosed. The voltage generating apparatus includes a first N-type transistor and an enhancement MOSFET transistor. The first N-type transistor has a first drain/source coupled to a first voltage, a second drain/source generating a first output voltage, and a gate coupled to a second voltage. The enhancement MOSFET transistor has a first drain/source coupled to the second drain/source of the first N-type transistor, and a second drain/source and a gate coupled to a second voltage. The first N-type transistor is a depletion metal oxide semiconductor field effect transistor (MOSFET).

Abstract: A current mirror circuit 10 is formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN1, MN3 and nMOS transistors MN2, MN4 are formed to have a current ratio of 1:m. Two currents output from the current mirror circuit 10 are each distributed to two. The distributed currents flowing in the nMOS transistors MN2, MN4 are added and are then allowed to flow into one resistor R2. Hence, for the resistor R2, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

Abstract: A low-voltage band-gap reference voltage bias circuit is provided. In the low-voltage band-gap reference voltage bias circuit, a proportional-to-absolute temperature (PTAT) current is copied to two nodes, respectively, to generate a first voltage having a negative slope with respect to temperature variation, and a second voltage having a positive slope with respect to temperature variation, and first and second elements having high impedances are serially connected to each other between the two nodes, such that the sum of the negative slope of the first voltage and the positive slope of the second voltage is zero and an average voltage between the two nodes is extracted to output the extracted result as a reference voltage. Accordingly, a stable reference voltage of 1V or lower regardless of a power supply voltage and temperature variation can be supplied.

Abstract: An integrated circuit includes a storage component, a voltage stabilizer circuit with an input configured to receive an input voltage and an output configured to provide an output voltage, and a load. The load is coupled to the output of the voltage stabilizer circuit. The integrated circuit is operable in a first and second operating state. In the first operating state, the storage component receives an input voltage and in the second operating state the input voltage is provided to the input of the voltage stabilizer circuit.

Abstract: A power supply voltage control apparatus capable of freely setting a clock period setting margin according to a system clock frequency, and capable of converging power supply voltage to minimum power supply voltage where normal operation is possible in a short period of time without errors in operation of internal circuits in response to changes in the system clock frequency is provided. Power supply voltage control apparatus is provided with a first frequency-divider that frequency-divides the system clock at a first frequency-diving ratio, a second frequency-divider that frequency-divides an output of a voltage control oscillator at a second frequency-dividing ratio, a phase comparator/frequency comparator that carries out a phase comparison/frequency comparison on the respective output signals of the first and second frequency-dividers, and a controller.

Abstract: In a current switch, a bias generation circuit electrically connected to a high voltage power supply generates a bias current. The bias current is mirrored by a current mirror containing a first plurality of transistors to a first one of a second plurality of transistors. The first one of the second plurality of transistors amplifies the mirrored bias current and transmits the amplified bias current to a second one of the second plurality of transistors. The second one of the second plurality of transistors sinks the amplified bias current into a node shared by an internal reference voltage, thereby putting the node in a first logic state. A third one of the second plurality of transistors receives the amplified bias current from the second one of the second plurality of transistors and sinks the amplified bias current into a node shared by a gate of a high voltage p-type transistor, thereby putting the node in the first logic state.

Abstract: A functional molecular element having a structure in which the contact resistance at the interface between a constituting molecule and an electrode can be reduced, the functional molecular element having a specific conductivity, a process for producing the same, and a functional molecular device, are provided. A ?-electron conjugated molecule 1, which is one species of linear tetrapyrrole having a substantially disk-shaped central skeleton moiety 2 and a flexible side chain moiety 3 composed of an alkyl group, is dissolved in 4-pentyl-4?-cyanobiphenyl or tetrahydrofuran, and the concentration is adjusted to an appropriate level. This solution is applied to electrodes 5 and 6, and the solvent is evaporated, whereby an array structure 4 of the ?-electron conjugated molecules 1 is self-organizingly formed.

Abstract: A compensation circuit for reducing power consumption in at least one digital circuit includes a first sample circuit connected to a first supply voltage, a second sample circuit connected to a second supply voltage, and a controller connected to the first and second sample circuits. The first and second sample circuits are substantially functionally equivalent to one another but optimized for different regions of operation within a specified range of PVT conditions. The controller is operative to receive respective output signals from the first and second sample circuits, to monitor a functionality of the second sample circuit relative to the first sample circuit, and to adjust a level of the second supply voltage to ensure correct operation of the second sample circuit throughout the specified range of PVT conditions. The digital circuit is operative from the second supply voltage.

Abstract: The present invention includes: a main voltage detection unit for detecting a voltage applied between main electrodes of an electrical power switching element; a control current source for injecting a current into a gate electrode of the electrical power switching element in accordance with the voltage detected by the main voltage detection unit; a main current detection unit for detecting a main current flowing between the main electrodes of the electrical power switching element; and an adjustment unit for adjusting a current of the control power source in accordance with the main current detected by the main current detection unit.

Abstract: A detection circuit includes a current source with no temperature coefficient; a current generation circuit that generates a VBE proportional reference current from the current source with no temperature coefficient; a current mirror circuit that returns an output current of the current generation circuit; a reference voltage generation circuit that generates a VBE proportional voltage with a negative temperature coefficient on the basis of the current returned by the current mirror circuit so that the VBE proportional voltage is used as a reference voltage of a comparator; and a full-wave rectifying means, having a differential pair and a rectifier circuit, using the current source with no temperature coefficient, having an alternating current signal supplied as an input signal, for generating a direct current voltage with a negative coefficient on the basis of a voltage obtained by full-wave rectifying the alternating current signal, and for using the generated voltage as a comparative voltage of the compar

Abstract: A power supply voltage containing a noise component is supplied to each pixel at the time of sampling of a reset level of a signal read out from each pixel, and a power supply voltage in which the noise component is suppressed is supplied to each pixel at the time of sampling of a read level of the signal read out from each pixel.

Abstract: A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2N (N=integer) where a reference resistance is indicated by R with the Ns being different from each other; and transistors corresponding to the respective resistance elements, the transistors being controlled by a binary code, and the BCS has a structure obtained by connecting in parallel first structures each constituted by serially connecting a resistance element and the corresponding transistor, and the TCS includes resistance bodies each obtained by connecting in parallel resistance elements with a resistance substantially equal to any of the resistance elements in the BCS; and transistors corresponding to the resistance bodies, controlled by a thermometer code, and the TCS has a structure obtained by connecting in parallel second structures each constituted by serially connecting one of the resistance bodies and the corresponding transistor.

Abstract: Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value;

Abstract: A semiconductor circuit including a bias circuit (1) generating a signal reflecting a current driving capability of a transistor; an analog/digital converter circuit (2) converting the signal from an analog format into a digital format; and a signal processing circuit (3) partially controlled in an operating state or a non-operating state according to the signal converted by the analog/digital converter circuit as a control signal, is provided.

Abstract: A simple voltage detection circuit has few circuit elements, but provides a voltage output that is substantially temperature insensitive. The voltage detection circuit includes a diode-connected transistor, a cascode-connected transistor, as well as first and second resistors coupled between ground and a ramped power supply voltage. The diode-connected transistor exhibits a negative temperature coefficient. The on resistance of the cascode-connected transistor increases with temperature and thus the voltage dropped across the cascode-connected transistor also increases with temperature. By correctly sizing the cascode-connected device, the negative and positive temperature coefficients of the diode-connected and cascode-connected devices can be substantially cancelled out.

Abstract: A current generator arrangement for use, e.g., in 1-10V interfaces for lighting systems, includes at least one transistor (Q3) having a base-emitter junction wherein the voltage drop across the base-emitter junction defines the intensity of the output current and wherein the base-emitter junction is exposed to temperature drift. A resistive network (Req2) is coupled to the transistor (Q3), whereby the intensity of the output current is a function of both the voltage drop across the base-emitter junction of the transistor (Q3) and the resistance value of the resistive network (Req2). The resistive network (Req2) includes at least one resistor element (NTC3; NTC4) whose resistance value varies with temperature to keep constant the intensity of the output current irrespective of any temperature drift in the voltage drop across the base-emitter junction of the transistor (Q3).

Abstract: Various examples of internal voltage generation circuit are provided. In one example, the internal voltage generation circuit includes a level control signal generator for generating a level control signal in response to a power down mode signal, which is activated synchronously with a clock enable signal, and a precharge flag signal, which is enabled when a precharge operation, is performed, and an internal voltage generator for generating an internal voltage in response to the level control signal and outputting it to an output node.

Abstract: A measurement device independent of an integrated circuit including a transistor is disclosed. A current supply provides a first current and a second current. A switching unit transmits the first or the second current to the transistor. A current detection unit generates a first voltage and a second voltage according to a first base current of the transistor and the first current and generates a third voltage and a fourth voltage according to a second base current of the transistor and the second current. A voltage processing unit processes the first and the second voltages to generate a first differential value and processes the third and the fourth voltages to generate a second difference value. A calculation unit divides the second differential value by the first differential value to obtain a current ratio and adjusts at least one of the first and the second currents according to the current ratio.

Abstract: A reference voltage generator includes a first field effect transistor with n-type heavily doped gate structure and a second field effect transistor with p-type heavily doped gate structure. The first transistor is configured to have a gate and a substrate gate connected to ground, one terminal connected to a voltage supply, and another terminal connected to an output node. The second transistor is configured to have a gate and one terminal connected to the output node, and a substrate gate and another terminal connected to ground. The output node outputs a given reference voltage when voltage is supplied from the voltage supply. A voltage regulator that generates a constant voltage based on a given reference voltage incorporates the reference voltage generator.

Abstract: According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

Abstract: A device for providing a substantially constant current includes first and second current mirrors. The first current mirror receives a first amount of a first bias current and provides an output current based on the first amount of the first bias current, the first bias current being based on a fixed voltage. The second current mirror receives a second bias current and a second amount of the first bias current, the second bias current being based on a variable voltage. The second bias current and the second amount of the first bias current vary directly with variations in the variable voltage, and the first amount of the first bias current varies inversely with variations in the variable voltage. The output current remains substantially constant based on the variations in first amount of the first bias current, which counteract effects on the output current by variations in the second voltage.

Abstract: An internal voltage generation circuit for a semiconductor device and method therefor includes a voltage generator configured to generate voltages with different levels by using an external voltage. A code storing unit is configured to store a selection code to select an internal voltage out of the plurality of voltages. A decoding unit selects the internal voltage from among the plurality of voltages in response to the selection code in a normal mode, and selects the internal voltage out of the plurality of voltages in response to a test selection code set in a test mode. The interval voltage selected in the normal mode is used as an initial value that is a reference of the selection in the test mode.

Abstract: A power control device for an electronic device for enhancing power stability when the electronic device is powered on including a high-pass filtering unit for performing a filtering process on an input signal for generating an output signal, and a control unit coupled to the high-pass filtering unit and a first voltage generator of the electronic device for outputting the output signal to the first voltage generator according to the voltage level of the output signal.

Abstract: The purpose of the present invention is to decrease a leak current of a voltage supply circuit using a MOS transistor. This voltage supply circuit comprises an n-channel MOS transistor having a low threshold voltage, the drain of which is connected to the power supply voltage, and a p-channel MOS transistor, the source of which is connected to the source of the n-channel MOS transistor and which supplies a voltage vii from the drain to a load circuit. Since a voltage V gs=1 V is applied to the gate-sources of the p-channel MOS transistor when said circuit is on standby, the p-channel MOS transistor operates in a larger cut-off region than an ordinary cut-off region.

Abstract: An apparatus includes a voltage converter for supplying voltage to an electrical load. The voltage converter is electrically connected at an output to a terminal of a series circuit. The voltage converter includes mechanisms for connecting the electrical load and a current sink. The voltage supplied by the voltage converter is dependent on an input voltage and on a present multiplication factor. The apparatus also includes a first comparator, a second comparator, and selection logic.

Abstract: A source driver includes an amplifier, and the amplifier includes an input stage, an output stage, a first current source, a second current source, a third current source, and a switch module. The first current source is utilized to provide a first bias current to the input stage, the second current source is utilized to provide a second bias current to the output stage, and the third current source is utilized to provide a third bias current. The switch module is utilized for selectively connecting the third current source to the input stage or the output stage.

Abstract: A semiconductor memory device having a driver configured to sequentially perform over-driving and normal driving operations is presented. The semiconductor memory device includes a driver that outputs a drive signal, that over-drives the drive signal with an over-drive voltage having a voltage level higher than a normal drive voltage, and then subsequently normally drives the drive signal with the normal drive voltage. The semiconductor memory device also includes a drive voltage adjuster that detects a level of the over-drive voltage and compensates for a change in the voltage level of the normal drive voltage in response to the detected level of the over-drive voltage.

Abstract: An internal voltage generator of a semiconductor device consumes relatively small amount of driving current and generates a stable internal voltage with relatively small voltage level variation. The semiconductor device includes an oscillator configured to generate an oscillation signal in response to an input signal, wherein the oscillation signal oscillates with a first period and oscillates with a second period longer than the first period during a predetermined latter section, and an internal circuit configured to perform a predetermined operation in response to the oscillation signal.

Abstract: A user-programmable bi-directional, constant current generator circuit allows external programming of either a positive (+) or a negative (?) polarity output current, for injection into one of two locations of the PWM controller circuit of a DC-DC voltage converter. The parameters of the DC-DC converter's offset voltage will depend upon the connection of a single programming pin to one of two programming resistors. The programming resistors are respectively referenced to different supply rail voltages (VCC and VSS). The polarity of the offset additionally depends upon where, within the PWM-controlled DC-DC converter, the programmed constant current is injected.