Abstract: A method, system, and computer program product for improving the performance of a digital circuit are provided in the illustrative embodiments. A real frequency of operation of the digital circuit is adjusted using a control loop in the digital circuit, the adjusting the real frequency being responsive to a change in an operating condition of the digital circuit. A measurement of a current drawn by the digital circuit is received from a voltage regulator supplying electrical power to the digital circuit. An over-current target current value is received. A voltage output from the voltage regulator to the digital circuit is adjusted such that the current drawn by the digital circuit does not exceed the over-current target current value.

Abstract: An impendence tuning apparatus is disclosed. The impendence tuning apparatus includes an operation amplifier, a reference resistor, a tuned resistor, a switching module, a current generator, a current detector and a controller. A first input terminal of the operation amplifier receives a basic voltage and the second terminal of the operation amplifier coupled to a first end. The switching module receives a control and coupled the first end to the tuned resistor or the reference resistor accordingly for generating a tuned current or a reference current separately. The current generator receives and mirrors the reference current or the tuned current to generate a first current and a second current. The current detector receives the first and the second currents and outputs current values the first and the second currents to the controller. The controller tunes an impendence of the tuned resistor according to the first and the second currents.

Abstract: A constant-voltage circuit includes: first and second field-effect transistors; a first node connected to the drains of the first and second field-effect transistors; a second node connected to the gates of the first and second field-effect transistors; a bipolar transistor whose collector is connected to the second node; a resistor connected to the source of the second field-effect transistor and the collector of the bipolar transistor; and a bias circuit that is connected to the source of the second field-effect transistor and supplies a bias voltage to the base of the bipolar transistor, wherein a power supply is connected to the first node and a constant voltage is outputted from the source of the first field-effect transistor.

Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

Abstract: An integrated circuit device has a primary voltage regulator and an ultra-low power secondary voltage regulator. The ultra-low power secondary voltage regulator supplies voltage to certain circuits used for providing data retention and dynamic operation, e.g., a real time clock and calendar (RTCC) when the integrated circuit device is in a low power sleep mode. The primary voltage regulator provides power to these same certain circuits when the integrated circuit is in an operational mode.

Abstract: According to one embodiment, a semiconductor device provided with an input terminal and a resistor circuit is presented. The resistor circuit is provided with first and second transistors, a first resistor, a capacitor and a capacitor. A drain of the first transistor is connected to the input terminal. One end of the first resistor is connected to a gate of the first transistor. A drain of the second transistor is connected to a source of the first transistor. A gate of the second transistor is connected to the other end of the first resistor. A source of the second transistor is connected to a power supply of a source side. The capacitor is connected between the drain and the gate of the first transistor. The voltage supply circuit is connected to the other end of the first resistor and the gate of the second transistor.

Abstract: Power supply is facilitated. In accordance with one or more embodiments, a power regulator circuit includes first and second regulators and a controller for controlling operation of the power regulator circuit in standby and normal operational modes. The first and second regulators respectively provide regulated power at main and standby power levels, the standby power level being lower than the main power level. For the standby mode, the controller operates the second regulator for supplying power to an integrated circuit at the standby power level. For transitioning to the normal mode, the controller turns the first regulator on while continuing to operate the second regulator for supplying power to the integrated circuit during a start-up period. After a start-up period (e.g., when the first regulator is up to full power), the controller operates the first regulator for supplying power for operating the processor in a high-frequency mode.

Abstract: To provide an internal power supply circuit that supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply wiring, the internal power supply circuit includes a plurality of power supply units connected in common to the internal power supply wiring and an internal-power-supply control circuit that selects either activation or deactivation with regard to at least a part of the power supply units.

Abstract: A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal.

Abstract: A current reference circuit includes a proportional-to-absolute temperature (PTAT) current generator, a band-gap reference circuit and a current replication circuit. The PTAT generator generates a PTAT current. The band-gap reference circuit generates a reference voltage based on the PTAT current and generates a second current by cancelling a first current from the PTAT current. The first current has a zero temperature coefficient and the second current has a positive temperature coefficient. The current replication circuit replicates the first current based on the PTAT current and the second current.

Abstract: A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.

Abstract: An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.

Abstract: Various embodiments of a semiconductor apparatus are disclosed. In one exemplary embodiment, the semiconductor apparatus may include an internal voltage generation unit configured to generate an internal voltage having a voltage level corresponding to a code value of a voltage control code, a voltage comparison unit configured to compare a voltage level of a target voltage with a voltage level of the internal voltage, and a voltage control code generation unit configured to adjust the code value of the voltage control code based on the comparison result of the voltage comparison unit.

Abstract: A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input.

Abstract: A circuit for generating a reference voltage includes a first transistor configured to receive a reference system voltage, the first transistor configured as a current source, the first transistor configured to provide a current independent of the system voltage, a plurality of diode devices configured to receive the current provided by the first transistor, and a second transistor associated with the plurality of diode devices, the second transistor configured to compensate for process variations in the first transistor, such that the plurality of diode devices provides a reference voltage that is at least partially compensated for the process variations.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: A reference voltage generation circuit includes a driving control unit configured to output an enable signal during a first time period in response to a power-on reset (POR) signal, a reference voltage generation unit configured to have an initial operation determined in response to the enable signal and to output a reference voltage maintained at a constant voltage level after the first time period, and a reference voltage control unit configured to fix the voltage level of the reference voltage to a first voltage upon a voltage level of the reference voltage being increased to at least a set voltage level.

Abstract: A high voltage current source and a voltage expander implemented in a low voltage semiconductor process. The voltage expander extends the operating voltage range of a stack of transistors to multiple times a supply voltage Vdd at the output node of the stack without exceeding the breakdown voltage of any of the transistors in the stack. The voltage expander uses a diode and a voltage divider to detect the output node voltage changes and generates a plurality of voltages that control the gate voltages for the stack of transistors. A high voltage wide swing current source utilizes a transistor to set the output current and the voltage expander to extend the output voltage range of the current setting transistor. An additional transistor and another current source ensure that the output current is constant throughout the entire output voltage range between about 0V and multiple times the supply voltage Vdd.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.

Abstract: Provided herein are circuits and methods to generate a voltage proportional to absolute temperature (VPTAT) and/or a bandgap voltage output (VGO) with low 1/f noise. A first base-emitter voltage branch is used to produce a first base-emitter voltage (VBE1). A second base-emitter voltage branch is used to produce a second base-emitter voltage (VBE2). The circuit also includes a first current preconditioning branch and/or a second current preconditioning branch. The VPTAT is produced based on VBE1 and VBE2. A CTAT branch can be used to generate a voltage complimentary to absolute temperature (VCTAT), which can be added to VPTAT to produce VGO. Which transistors are in the first base-emitter voltage branch, the second base-emitter voltage branch, the first current preconditioning branch, the second current pre-conditioning branch, and the CTAT branch changes over time.

Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.

Abstract: A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A system corrected programmable integrated circuit is applied to a power supply and includes a comparator unit, a digital output unit and a programming unit. The comparator unit includes an external feedback voltage input end and a reference voltage input end for inputting a feedback voltage and a reference voltage respectively, such that when the feedback voltage equals the reference voltage, the comparator unit transmits a control signal to the digital output unit. When receiving the control signal, the digital output unit stops outputting the reference voltage and the current reference voltage is recorded as a programming voltage for outputting to the programming unit. When receiving the programming voltage, the programming unit programs the programming voltage and transmits the voltage to the reference voltage input end. Accordingly, the present invention automatically detects and compensates a system error to reduce external element, yet still achieving a qualified range of product specification.

Abstract: The present invention provides a reference power supply circuit which does not require trimming and prevents occurrence of deadlock of a band gap reference circuit. An RFID tag chip related to the present invention has a reference power supply including a switch for switching between a band gap reference circuit and a Vth difference reference circuit. A reference potential in band gap reference of the band gap reference circuit and an output of the Vth difference reference circuit are compared by a comparator, and a transistor operating as a switch is controlled, thereby making the reference potential in band gap reference rise, hastening startup of the band gap reference circuit, and preventing occurrence of deadlock in the band gap reference circuit.

Abstract: A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal.

Abstract: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.

Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Abstract: An example circuit includes a regulator circuit coupled to first and second nodes. A capacitance circuit and a slew rate control circuit are coupled between the first and second nodes. The regulator circuit is coupled to charge a capacitance of the capacitance circuit with a charge current. The slew rate control circuit is coupled to control a change in voltage over change in time between the first and second nodes during a power up mode of the circuit. The slew rate control circuit further includes a switch and a resistor. The slew rate control circuit is coupled to switch the switch in response to a voltage between the first and second nodes. A voltage drop across the resistor is limited to a base-emitter voltage drop of a transistor coupled between the first and second nodes to set the change in voltage over change in time.

Abstract: A semiconductor device includes a voltage regulator. The device includes an operational amplifier configured to compare an input voltage with a feedback voltage and output an output voltage, an up-resistor connected between an output of the operational amplifier and a first node, a down-resistor connected between a second node and a ground voltage terminal, and a switching unit including a fuse box connected between a third node outputting the feedback voltage and a fourth node having a variable resistance value, and configured to connect the first node with the fourth node and the second node with the third node, or connect the first node with the third node and the second node with the fourth node.

Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.

Abstract: A system including a first transistor, a first capacitor and a circuit. The first transistor has a first control input and is configured to regulate an output voltage. The first capacitor is coupled at one end to the first control input and at another end to a circuit reference. The circuit is configured to provide a first voltage to the first control input, where the first voltage includes an offset voltage that is referenced to the output voltage and adjusted to compensate for variations in the first transistor.

Abstract: A reference voltage generation circuit for generating a reference voltage that can adaptively depend on temperature and process includes: a comparator, having a process, temperature and voltage (PVT) insensitive reference as a first input, and a feedback of the output as a second input, for generating a voltage reference output; a first resistor, coupled to the output of the operational amplifier; a second and a third variable resistor coupled in parallel, and coupled between the first resistor and ground; and a transistor, coupled between the third variable resistor and ground.

Abstract: A High Definition Multimedia Interface (HDMI) cable carries high speed encoded data, which are transmitted differentially over data channels, along with a clock. A Mobile High-Definition Link (MHL) cable carries high speed data which are multiplexed to achieve smaller connectors with fewer pins. A MHL-to-HDMI cable is proposed, which includes an embedded MHL to HDMI adapter device for demultiplexing the received MHL-formatted signal and outputting an HDMI-formatted signal. The embedded circuit is powered by a combination of power sources, the power being harvested from the high-speed HDMI signals themselves, including a startup circuit harvesting power from a low speed HDMI signal when power from the high-speed HDMI signals is not available.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A voltage reducing circuit includes an internal power supply section configured to reduce an external power supply voltage supplied from an external power supply to an internal power supply voltage which is lower than the external power supply voltage based on a reference voltage. A first current control section is configured to control a current flowing through the internal power supply section when the internal power supply voltage is lower than a setting voltage. A second current control section is configured to control the current flowing through the internal power supply section when the internal power supply voltage exceeds the setting voltage.

Abstract: A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

Abstract: A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage.

Abstract: An internal voltage generating circuit is provided. The internal voltage generating circuit of a semiconductor device includes a control signal generating circuit for generating a control signal according to a number of data bits, a comparator for comparing a reference voltage to an internal voltage to generate a driving signal when the control signal is inactivated, a driving signal control circuit for inactivating the driving signal when the control signal is activated, and an internal voltage driving circuit for receiving an external power voltage and generating the internal voltage in response to the driving signal. Therefore, an internal voltage can be turned to a reference voltage level or to an external power voltage level according to the number of data input and/or output bits of a semiconductor device, and even when the number of data input and/or output bits is increased, a data access speed can be improved.

Abstract: An internal voltage control circuit includes active drivers, a control unit, and a time interval adjustment unit. The active drivers are configured to receive a common internal voltage. The control unit is configured to control respective enable operations of the active drivers. The time interval adjustment unit is configured to respectively supply enable signals, generated by the control unit, to the active drivers at respective predetermined time intervals.

Abstract: An output driver circuit having an input stage and an output stage, wherein the output stage and the input stage are configured to function as (1) a low-frequency voltage follower and (2) a high-frequency feedback loop for the output driver circuit. In operation, the low-frequency follower and the high-frequency feedback loop may precisely regulate the output voltage of the output driver circuit when large load transients occur. A compact charge pump may be used to supply additional voltage required to operate a current mirror of the output driver circuit.

Abstract: A composite device system including: a first device including a nonvolatile memory; and a second device configured to supply a power to the first device, the second device including: a power supply circuit configured to stabilize a first power supplied from an external part into a second power lower than the first power, and to supply the second power to the first device; a communication circuit configured to receive control data from the first device; and a switch configured to switch between on and off based on the control data, and to supply the first power to the first device when the switch is on, wherein the second device receives the control data from the first device by the communication circuit when data is written into the nonvolatile memory so that the switch is turned on and the first power is supplied to the first device.

Abstract: A voltage adjusting circuit includes a voltage regulator module (VRM), a control chip, a connection device, and a number of first resistors. The VRM includes an input receiving a first voltage from a motherboard, and an output connected to a liquid crystal display (LCD). A number of sense terminals of the control chip are connected to the LCD to sense current of the LCD. A driven terminal of the control chip is connected to a control terminal of the VRM to output corresponding driven signals to control the VRM to output corresponding voltage to the LCD. A first terminal of each first resistor is connected to a corresponding sense terminal of the control chip. A second terminal of each first resistor is grounded. The connection device is configured to cut off or connect the first resistor from or to the corresponding sense terminal of the control chip.

Abstract: A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal.

Abstract: A semiconductor integrated circuit includes a first ground voltage pad, a second ground voltage pad, an internal voltage generation unit, and a division unit. The first ground voltage pad is configured to receive a first ground voltage. The second ground voltage pad is configured to receive a second ground voltage. The internal voltage generation unit includes a comparison unit configured to compare a reference voltage with a feedback voltage by using the first ground voltage, and a driving unit configured to drive an internal voltage terminal in response to an output signal of the comparison unit. The division unit is coupled between the internal voltage terminal and the second ground voltage pad, and configured to divide a voltage of the internal voltage pad and generate the feedback voltage supplied to the internal voltage generation unit.

Abstract: A DC motor is provided. The DC motor prevents rush or overload of current in the DC motor during and/or after power input irregularities to the DC motor. A control circuit of the DC motor is configured to control current provided to the DC motor. When power irregularities in the power input to the DC motor are detected by the control circuit, the control circuit stops generating PWM (Pulse Width Modulated) signals and stops the current provided to the DC motor. After the stoppage of PWM signals, the control circuit can perform a soft-start of the PWM signals when the power irregularities are no longer detected. The soft starting of the PWM signals generates gradual increase in current to the DC motor, thus, preventing sudden rush of current that cause malfunction of the DC motor.

Abstract: A semiconductor integrated circuit includes a selector to selectively output and supply to a monitoring target voltage terminal one of a power supply voltage from an outside of the semiconductor integrated circuit and a predetermined reference voltage depending on an adjusting mode signal, a voltage monitoring circuit to monitor a voltage fluctuation at the monitoring target voltage terminal and converting the voltage fluctuation that is monitored into a control signal, and an input and output circuit to output the control signal to the outside.

Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Abstract: A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.