Abstract: A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.

Abstract: A power switch for an integrated circuit provides a stepped profile supply potential. A supply potential generation block generates the stepped profile output supply to control the ramp rate of the output in order to prevent a false trigger of electrostatic discharge at the pads of the integrated circuit.

Abstract: According to one embodiment, a system and method for operating an Integrated Circuit (IC) includes inputting power to the IC in bursts, sensing an IC temperature using a temperature sensor, operating the IC by controlling the power to be outputted by the IC during the burst in dependence on the sensed IC temperature compared to a reference IC temperature using a controller, wherein the IC temperature is obtained at a predetermined moment prior to a start of the burst, and the IC is operated by setting an allowable power to be outputted by the IC prior to the start of the burst.

Abstract: A semiconductor integrated circuit can include a reference voltage pad that can be configured to receive an external reference voltage and supply the external reference voltage to the inside of the semiconductor integrated circuit, an internal reference voltage generator that can be configured to generate an internal reference voltage by voltage dividing, a selector that can be configured to select and output one of the external reference voltage and the internal reference voltage in response to a selection signal, and a voltage trimming block that can be configured to regulate the level of the output voltage from the selector in response to trimming signals and outputs the level-regulated voltage as a reference voltage.

Abstract: A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.

Abstract: A mix mode wide range divider is provided for dividing a first signal by a second signal to generate an output signal. A third signal is generated depending on the resistance of a first adjustable resistor, and a fourth signal is generated according to the third signal and a target value determined by the second signal, to adjust the resistance of the first adjustable resistor and the resistance of a second adjustable resistor. The resistance of the first adjustable resistor is so adjusted to make the third signal equal to the target value, and the resistance of the second adjustable resistor is so adjusted to maintain a ratio of the resistance of the second adjustable resistor to the resistance of the first adjustable resistor. The output signal is generated depending on the first signal and the resistance of the second adjustable resistor.

Abstract: An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits.

Abstract: According to an example embodiment, an apparatus for controlling a power supply voltage for an integrated circuit may be provided, which may include a plurality of different types of process region detection circuits, each process region detection circuit configured to identify a respective process region of a plurality of process regions. The apparatus may also include a voltage selection circuit configured to determine a highest voltage among the voltages associated with the identified process regions and to select a power supply voltage for the integrated circuit that is equal to the highest voltage, one or more functional test circuits configured to perform a functional test using the selected power supply voltage, and a voltage adjuster circuit configured to increase the selected power supply voltage if the functional test fails.

Abstract: A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value.

Abstract: A system for providing a desired power to a load. The system includes: a current detection module configured to generate a current signal based on a current flowing through the load; a voltage detection module configured to generate a voltage signal based on a voltage across the load; a multiplier module configured to generate an output signal based on an analog multiplication of i) the current signal and ii) the voltage signal; a comparing module configured to perform a comparison of the output signal to a power reference signal, wherein the power reference signal is based on the desired power; and a voltage source configured to control the voltage across the load based on the comparison of the output signal to the power reference signal.

Abstract: An internal voltage supplying device. A reference voltage generator generates a first feedback voltage having a predetermined voltage ratio with respect to a core voltage. An adjusting mechanism adjusts the voltage ratio, and a voltage generator supplies a high voltage having a level higher than a level of the core voltage by the level of a threshold voltage or higher and maintains the level of the high voltage in accordance with the first feedback voltage.

Abstract: A voltage supply apparatus includes a power noise sensing unit, a voltage selecting unit, a first power voltage supply unit and a second power voltage supply unit. The power noise sensing unit senses noise from first and second powers and outputs a power noise sensing signal. The voltage selecting unit outputs first and second driving signals in response to a voltage-supply-enable-signal and the power noise sensing signal. The first power voltage supply unit applies a voltage of the first power in response to the first and second driving signals. The second power voltage supply unit applies a voltage of the second power in response to the first and second driving signals.

Abstract: A circuit and method for generating body bias voltage for an integrated circuit is disclosed. The circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: Sharp fluctuations of an internal voltage when an internal voltage generating circuit is activated or inactivated are prevented. The internal voltage generating circuit to supply the internal voltage generated from an external voltage to an internal power supply line, a control circuit to control an operation of the internal voltage generating circuit, and a voltage detection circuit to detect a level of a first voltage are included. When, for example, the internal voltage generating circuit is activated, the control circuit stepwise increases supply ability of the internal voltage at a first speed and when the internal voltage generating circuit is inactivated, the control circuit stepwise reduces the supply ability of the internal voltage at a second speed that is different from the first speed. Accordingly, wild fluctuations of the internal voltage when the internal voltage generating circuit is activated/inactivated can optimally be prevented for each case.

Abstract: A system for generating a tunable DC slope includes: a first stage, supplied with an external voltage, for receiving a process, voltage and temperature (PVT) insensitive reference voltage and generating a voltage independent current; a second stage, coupled to the first stage and supplied with the external voltage, for generating a voltage dependent current and summing the voltage dependent current and the voltage independent current to generate a sloped voltage; and a third stage, coupled to the second stage and supplied with the external voltage, for amplifying the sloped voltage, and tapping the resultant sloped voltage at a desired point for generating the output DC slope.

Abstract: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.

Abstract: A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a first power supply terminal coupled the second power supply terminal of the first circuit, a second power supply terminal, and an input/output. The third circuit has a first power supply terminal coupled the second power supply terminal of the second circuit, a second power supply terminal, and an input/output. The first capacitor has a first terminal coupled to the input/output of the first circuit and a second terminal coupled to the input/output of the second circuit. The second capacitor has a first terminal coupled to the second terminal of the first capacitor and a second terminal coupled to the input/output of the third circuit.

Abstract: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.

Abstract: A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode.

Abstract: An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block.

Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator; and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.

Abstract: Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply circuit that produces a regulated-output voltage based on an output-control signal generated by a resistive voltage divider. The circuit includes a PVT detector configured to generate an interface control signal and an interface circuit (i) connected to PVT detector and to the resistive voltage divider and (ii) configured to adjust its resistance in response to the interface control signal. Adjusting the resistance of the interface circuit causes the voltage of the output-control signal to be adjusted, thus causing the power supply circuit to adjust the regulated output voltage.

Abstract: A voltage generating circuit generates a voltage for driving an ultrasonic oscillator, and includes a multi-stage connected power supply circuit without a transformer.

Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

Abstract: A switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: An object of the invention is to reduce the power consumption of a semiconductor device that requires a plurality of reference potentials and a method of driving the semiconductor device. Disclosed is a semiconductor device having a potential divider circuit in which a potential supplied to a power supply line is resistively divided by resistors connected in series to the power supply line so that a desired potential is output through a switch transistor electrically connected to the power supply line. A drain terminal of the switch transistor is electrically connected to a gate terminal of a transistor provided in a circuit on the output side (or to one terminal of a capacitor) to form a node. The switch transistor has an off current low enough to hold the desired voltage in the node even when the potential is no more supplied to the power supply line.

Abstract: As provided herein, in some embodiments, power consumption and/or chip area is reduced by bias circuits configured to provide bias conditions for more than one active circuit, thereby reducing the number of bias circuits in a design. Shared bias circuits may reduce the aggregate amount of on-chip area utilized by bias circuitry and may also reduce the total power consumption of a chip. Additionally and/or alternatively, bias circuits disclosed herein are configured to provide outputs that are less susceptible to changes in the voltage supply level. In particular, in some embodiments, bias circuits are configured to provide relatively constant bias conditions despite changes in the voltage supply level. A bias circuit arrangement with an output substantially decoupled from changes in the voltage supply level may provide a more stable operating point in an active circuit.

Abstract: According to an embodiment, a semiconductor device includes a functional circuit, an electric current measurement circuit and a control circuit. The functional circuit operates with a supplied electric power. The electric current measurement circuit is configured to measure an electric current based on the electric power. The control circuit is configured to control an operation of the functional circuit in accordance with operation information about the functional circuit and the measured electric current.

Abstract: A low noise current source includes first and second voltage input terminals. The current source further includes an amplifying device having an input terminal and an output terminal, where the output terminal is coupled to the second voltage input terminal via a load. The current source also includes a bias circuit coupled between the first voltage input terminal, the second voltage input terminal, and the input terminal. The current source additionally includes a first bypass circuit coupled between the first voltage input terminal and the input terminal, where the first bypass circuit configured to provide a substantially high electrical resistance and substantially no electrical impedance between the first voltage input terminal and the input terminal.

Abstract: The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally controlled so as to individually adjust power supply for each of said at least two electrically isolated circuit regions (10) based on the at least one monitored working parameter. Thereby, a fast and simple control functionality with low area overhead can be provided.

Abstract: A current control circuit in accordance an exemplary aspect of the present invention includes a first transistor that controls a current flowing to a load, a first resistor through which a current flows according to a current flowing through the first transistor, a control signal generation circuit that generates a control signal used to control the first transistor based on a comparison voltage and a predetermined reference voltage, the comparison voltage being determined based on a resistance value of the first resistor and a current flowing through the first resistor, and a reference voltage generation circuit that generates the reference voltage, the reference voltage generation circuit including a constant current source and a second resistor connected in series with the constant current source.

Abstract: A semiconductor circuit includes a voltage regulator and a buffer transistor. The voltage regulator converts an input voltage input to an input terminal thereof into an output voltage output to an output terminal thereof. The buffer transistor is an n-channel depletion-mode metal-oxide semiconductor field effect transistor, disposed between the power supply terminal and the voltage regulator with a gate terminal thereof connected to the power supply terminal, a drain terminal thereof connected to the power supply terminal, and a source terminal thereof connected to the input terminal of the voltage regulator.

Abstract: An apparatus and method for supplying power to circuits of an integrated circuit (IC) from the wasted power in low-swing high-speed differential line drivers used in the IC, is disclosed. In a high speed line driver the load resistors of the driver are connected to a power supply, either the local power supply or the receiver power supply. DC power for the driver is supplied through these resistors. A large portion of this power, supplied from the power supply is wasted in the DC set-up circuit of the differential line driver. It is proposed to use this wasted power to power selected circuits of an IC. The use of this wasted power from the drivers for powering the circuits reduces the overall power dissipation of the system.

Abstract: A grounding switch is described which operates properly even in the presence of negative voltages on a signal line. The grounding switch uses isolated field effect transistors that have their substrates tied to different voltages. The isolated field effect transistor has a gate voltage and substrate voltage which can be pulled down to a negative voltage when the signal line has a negative voltage allowing the switch to remain open even with a negative voltage.

Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage.

Abstract: An internal voltage generation circuit includes a first enable signal generator configured to delay an active signal to generate a first enable signal, a comparison signal generator configured to compare the internal voltage with an internal reference voltage to generate a comparison signal, a pulse signal generator configured to receive the first enable signal and to generate a pulse signal, a transmission device configured to buffer and transfer the comparison signal as a pull-down signal, and a drive device configured to drive the driving signal to the first level in response to the pull-down signal.

Abstract: A biasing device can supply a bias voltage to bias-able element by coupling a bias circuit to the bias-able element, coupling a state adjusting device to the biasing circuit, configuring the state adjusting device to 1) increase an initial biasing voltage by a first amount when an intermediate voltage threshold exceeds a voltage drop across the bias-able element and 2) increment the increased initial bias voltage by a second amount, where the second amount is a fraction of the first amount, until the voltage drop across the bias-able element substantially equals a predetermined bias voltage. The bias circuit of the biasing device can include a variable resistance, which is controlled by the state adjusting device and configured to vary the biasing voltage, in series with the bias-able element.

Abstract: A voltage regulator is provided having high accuracy, low PSRR, and no headroom limitation. Generally, the regulator includes: an operational amplifier (OPAMP) having a non-inverting input coupled to a reference voltage; an output source follower coupled to and controlled by an output of the OPAMP, the output source follower including a drain coupled to a voltage source and a source coupled to an output-node of the regulator; a replica source follower coupled to and controlled by the OPAMP, the replica source follower including a drain coupled to the voltage source and a source coupled to circuit ground through a resistor network; and a feedback circuit extending from the output-node through a feedback resistor to the source of the replica source follower and through at least a first resistor of the resistor network to an inverting input of the OPAMP to couple a feedback voltage thereto. Other embodiments are also provided.

Abstract: A first pump circuit generates a first voltage for decreasing the distance between primary electrodes. The first voltage is limited to a predetermined limit by a first limiter circuit. A second pump circuit generates a second voltage for keeping the distance between the primary electrodes constant. A third pump circuit generates the second voltage and has a supplying capacity smaller than the first one. The second voltage is limited by second and third limiter circuits. A ripple capacitor is charged up to the second voltage by the second pump circuit and the second limiter circuit within a period of time the first voltage is being generated. When a supplying voltage of the first pump circuit reaches to the first voltage, and a deformation stops, the second voltage is supplied by the third pump circuit and the third limiter circuit instead of the second pump circuit and the second limiter circuit.

Abstract: An apparatus is provided that comprises a test circuit; a first receiver unit arranged to receive test commands and to provide the test commands to the test circuit; a power supply unit arranged to supply power to the test circuit and to the first receiver unit; a second receiver unit arranged to receive power commands. The second receiver is arranged to control the operation of the power supply unit in response to the power commands received by the second receiver unit.

Abstract: A circuit to control the slew rate of charging a capacitance using the capacitance is disclosed. An example circuit includes a regulator circuit to regulate a supply voltage during a normal operation mode of the circuit. A capacitance circuit is coupled to the regulator circuit. The regulator circuit is coupled to charge a capacitance between a first node and a second node of the capacitance circuit with a charge current. A slew rate control circuit is coupled to the regulator circuit and the capacitance circuit. The slew rate control circuit sets a slew rate of a voltage between the first and second nodes during a power up mode of the circuit.

Abstract: A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

Abstract: An electronic device with polarity reversal protected connections and irreversibly interruptible programming connections, wherein the interruption is performed through safety elements provided in the programming paths, behind which safety elements diodes are disposed which block towards ground in normal operation, so that an overload current can be passed through the safety elements and through the diodes to ground through intentional polarity reversal of the respective connections, whereby the safety elements are destroyed and the programming conductors are irreversibly interrupted.

Abstract: An integrated circuit includes a first internal voltage generating unit configured to receive an external power and to generate a first internal voltage, and a second internal voltage generating unit configured to receive the first internal voltage, and to generate a second internal voltage having an absolute value of a target voltage level that is less than an absolute value of the first internal voltage, wherein the second internal voltage generating unit is initially enabled at a later time than the first internal voltage generating unit is initially enabled.

Abstract: A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).

Abstract: A semiconductor device includes a plurality of internal circuits, a plurality of low drop output regulators, and a power management unit. The plurality of low drop output regulators are configured to reduce a power source voltage applied from an outside and generate supply voltages which are to be supplied to the plurality of internal circuits. The power management unit is configured to change a voltage value of the power source voltage in accordance with a state of combination of voltage values of the plurality of supply voltages generated by the plurality of low drop output regulators.

Abstract: An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.

Abstract: A temperature-compensated internal voltage having a desired compensation range is generated with a sufficient controllability and stability. A temperature characteristic adding circuit generates a standard voltage having temperature dependence from a reference voltage not having temperature dependence. The standard voltage is A/D-converted and then added with standard code information (TN_VREF <4:0>) which specifies the level of the internal voltage. The additional value (TN_VREF2 <4:0>) is D/A-converted to generate an offset voltage having temperature dependence. The internal voltage of a desired level is generated based on the offset voltage.

Abstract: The present invention provides a semiconductor chip with voltage adjustable function, said semiconductor chip is supplied with a power supply device and comprises a voltage regulating module for adjusting the voltage supplied to said semiconductor chip from said power supply device, based on the best operating voltage at which said semiconductor chip operates.

Abstract: An imaging system, semiconductor device, and method of manufacture of a photo-detector device are disclosed. For example, an imaging system is disclosed, which includes a photo-detector unit including a plurality of conductive trenches formed within the photo-detector unit, and a plurality of electrical contacts, each electrical contact connected to a respective conductive trench. The imaging system further includes a light data processor unit coupled to an output of the photo-detector unit to convert an analog signal received from the photo-detector unit to a digital signal, a processing unit coupled to an output of the light data processor unit to generate a control signal in response to the digital signal, and a display unit coupled to an output of the processing unit to vary the intensity of an image displayed in response to the control signal.