Abstract: Adjustable gain circuits (AGCs) within serial filter stages are initialized to maximum gain. The output of each AGC is then sampled and converted to digital representation for use by control logic in setting the gain for the respective AGC. The gain adjustment decision for each AGC is performed in one shot, sequentially backwards from the last AGC, such that gain may be adapted simply and quickly within a number of cycles equal to the number of AGCs. Performance is enhanced by a fast-adapting cell in which capacitances are switched into the input path and feedback loop of an amplifier to reduce direct current gain within the transfer function through charge sharing dividing down the output voltage.

Abstract: Apparatus, systems, and methods implementing techniques for filtering signals are described. A filter circuit receives an input signal and produces a corresponding filtered signal. The filter circuit has a transfer function that relates the filtered signal to the input signal. The transfer function includes at least one pole and at least one zero, where at least one of the zeros corresponds to a first frequency, and at least one of the poles corresponds to a second frequency. The apparatus also includes a negative-transconductance circuit that is coupled to the filter circuit and that increases a magnitude of a component of the filtered signal that corresponds to the second frequency.

Abstract: An electronic circuit includes a filtering circuit implemented with a distributed inductor-and-capacitor (LC) network that includes metal oxide effect (MOS) trenches opened in a semiconductor substrate filled with dielectric material for functioning as capacitors for the distributed LC network. The electronic circuit further includes a transient voltage suppressing (TVS) circuit integrated with the filtering circuit that functions as a low pass filter wherein the TVS circuit includes a bipolar transistor triggered by a diode disposed in the semiconductor substrate. The distributed LC network further includes metal coils to function as inductors disposed on a top surface of the semiconductor electrically contacting the MOS trenches.

Abstract: A circuit includes an input terminal adapted to receive an input voltage, a MOSFET having its drain terminal and its source terminal connected together, a first switching arrangement configured to be controlled by a first clock signal and adapted to selectively couple the gate terminal to the input terminal, and a further switching arrangement configured to be controlled by a further clock signal in timing relationship with the first clock signal and adapted to selectively couple the source terminal and a first voltage which is capable of pulling carriers out of a channel when the first switching arrangement is not coupling the input terminal to the gate terminal.

Abstract: Systems and methods for reducing harmonic distortion in a power system resulting from non-linear loading on the power system. The power at an interface with a power source is measured, and then distortion in the waveforms of the supplied power is identified. Cancellation signals which cancel all or part of the distortion are then generated and injected at the interface. In one embodiment, the power is sampled to determine the waveform, and then a Fast Fourier Transform is performed on the waveform to convert it to the frequency domain. Harmonics of the fundamental frequency can then be identified, and conjugates of the harmonics generated. An inverse Fast Fourier Transform is performed on the conjugates to generate a signal which is amplified to produce the cancellation signal.

Abstract: The invention enables a reversing IQ polarity in a bandpass filter so that the bandpass filter can filter signals with high side or low side injection.

Abstract: A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and/or stability of the overall circuit.

Abstract: A low-pass filtering circuit and method are disclosed. The circuit includes a low-pass filter with a capacitor, and a multiplier configured to multiply the capacitance of the capacitor by feeding-back a high-frequency signal apparent in an output signal of the low-pass filter to the capacitor.

Abstract: A noise shaping and voltage gain filtering third order electrical circuit and method comprises at least one pair of input resistors; a Frequency Dependent Negative Resistance (FDNR) filter positioned in between the at least one pair of input resistors; a feedback resistor; and an amplifier operatively connected to the feedback resistor and the at least one pair of input resistors, wherein as an electrical signal is introduced to the electrical circuit, the FDNR filter is adapted to filter signal blockers out of the electrical signal prior to the electrical signal reaching the amplifier for signal amplification, wherein the FDNR filter does not contribute noise to a signal-to-noise ratio (SNR) of the electrical signal, and wherein a transfer function of the FDNR filter is substantially elliptical in shape.

Abstract: A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.

Abstract: Disclosed is a complex elliptic filter having an order of three or higher which receives two differential signals that differ in phase from each other by 90 degrees are applied and outputs two differential signals that differ in phase from each other by 90 degrees. The complex filter circuit has internally at least two circuit blocks that include a capacitor connected in series with a coupler (gyrator). The complex filter is a third-order inverse Chebychev filter having an equiripple stopband of 40-dB attenuation amount. Alternatively, the coupler (gyrator) between elliptic capacitors is removed. Alternatively, the elliptic capacitors are made substantially equal to the capacitor arranged in parallel therewith. Alternatively, the gm value of an OTA and the capacitance value are each in an integral ratio represented substantially by a geometric progression of 2.

Abstract: A pseudo-image signal producing section produces a pseudo-image signal imitating an actual image signal. An amplitude detection section detects the amplitude of the pseudo-image signal having passed through a complex filter circuit. A filter control section controls an element value control section in the complex filter circuit so as to decrease the detected amplitude. The element value control section performs an element value adjustment so that absolute element values of a pair of elements corresponding to each other in two filter circuits in the complex filter circuit increase/decrease in opposite directions.

Abstract: An amplifier is provided which includes: a first variable capacitance device of which capacitance is variable, a second variable capacitance device of which capacitance is variable, electrically connected to the first variable capacitance device, and of an inverse conductivity type from the first variable capacitance device, and a first input unit for selectively inputting a bias voltage and a voltage signal to the first variable capacitance device and the second variable capacitance device, wherein, in the event that the bias voltage and the voltage signal are input to the first variable capacitance device and the second variable capacitance device, the capacitance of the first variable capacitance device and the second variable capacitance device is taken as a first value, and wherein the voltage signal is amplified with the capacitance of the first variable capacitance device and the second variable capacitance device as a second value smaller than the first value.

Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit, said current sensor producing an output current related to said common mode current; said active filter comprising a first and second transistor, each having first and second main electrodes and a control electrode, and an amplifier circuit driving said transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled t

Abstract: An example filter includes a differential amplifier and a resistor string coupled between output terminals of the differential amplifier. The resistor string may generate a common mode sense voltage and an intermediate voltage at an intermediate node. A feedback resistor is coupled between the intermediate node of the resistor string and an input terminal of the differential amplifier, and a feedback capacitor is coupled between a differential output terminal of the amplifier and the differential input terminal. Applying feedback in this manner may reduce area and power requirements of the filter to achieve selected frequency and gain performance.

Abstract: An example embodiment provides a method for calibrating an active RC filter and RC time constant calibrator for an active RC filter. The RC time contact calibrator includes a RC timer and a calibration code generator. The RC timer outputs a holding signal based on a comparison of a first output signal and a second output signal. The holding signal output by the RC timer causes a digital count value to be compared to a digital target value. The calibration code generator generates a slope control code and a flag signal based on the comparison of the digital count value and the digital target value and outputs the slope control code as a calibration code based on the flag signal. The slope control code controls the slope of the first output signal and the slope of the second output signal.

Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

Abstract: Disclosed are a circuit and a method for tuning a programmable filter including input terminals, output terminals, a filter network and a transadmittance stage. The input terminals can receive input signals, and the output terminals output a filtered signal. The transadmittance stage, coupled to the input terminals, generates a current at its output based on the input signals. The output of the transadmittance stage can be coupled to the output terminals. The filter network can be a resistive-capacitive network connected to the input terminals. The RC network can include a capacitance respectively coupling the input terminals to output terminals, and a voltage divider network coupling the input and output terminals together. The transadmittance stage output terminals can be connected to the voltage divider, and the output terminals of the programmable filter circuit are coupled to respective intermediate nodes of the voltage divider network to provide a filtered output signal.

Abstract: An adaptive equalizer including an equalizer filter and a tap coefficients generator used to process a sample data stream derived from a plurality of received signals is disclosed. The tap coefficients generator includes an equalizer tap update unit, a vector norm square estimator, an active taps mask generator, a switch and a pilot amplitude reference unit used to minimize the dynamic range of the equalizer filter. A dynamic mask vector is used to mask active taps generated by the equalizer tap update unit when an unmasked signal output by the equalizer filter is selected by the switch to generate an error signal fed to the equalizer tap update unit. A fixed mask vector is used to mask active taps generated by the equalizer tap update unit when a masked signal output by the equalizer filter is used to generate the error signal.

Abstract: In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit.

Abstract: According to an aspect of an embodiment, an apparatus comprises: a first current source and a second current source; a resistor connected between the first current source and a reference potential portion; a switched capacitor circuit having a variable capacitor, first switch and a second switch, the first switch and second switch alternately switching capable of charging a voltage to the variable capacitor and capable of discharging a electric charge of the variable capacitor; an integrating circuit having an output terminal and a first input terminal which is connected a portion between the second current source and the switched capacitor circuit, an integrating circuit for integrating a current from the portion and for exchanging into an output voltage of the output terminal; and a comparator for comparing the voltage between two end of the resistor and an output voltage of the integrating circuit.

Abstract: A model for modeling electromagnetic response in a conductor and in dielectric, a method of modeling the electromagnetic response in the conductor and dielectric and a program product therefor. Coupled supplies (delayed capacitive-current-controlled current sources or delayed inductance-voltage-controlled voltage sources) are low pass filtered in an electromagnetic model for the particular medium, e.g., a Partial Element Equivalent Circuit (PEEC) model for a conductor or dielectric. Thus, high frequency model instabilities are substantially reduced or eliminated.

Abstract: The specification and drawings present a new method and apparatus for using transferred-impedance filtering in RF (radio frequency) receivers (e.g., inside of a mobile communication device), wherein said filtering can be done with MOS-switches transferring impedance of a regular RC or RCL circuit to RF frequency filtering inside an RFIC (radio frequency integrated circuit).

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: An integrated RC filter comprises a first resistor being coupled to a first capacitor through a first node and a signal input of said integrated RC filter is coupled through one of the first resistor and the first capacitor to the first node. To allow for an increase in the RC time constant of the RC filter without losing signal transparency, amplification means are included between said signal input and said one of the first resistor and the first capacitor having a gain factor substantially larger than unity, said first node being coupled through attenuation means to a signal output, said attenuation means having an attenuation factor substantially.

Abstract: An active transconductance is provided by converting an input voltage into a current, and providing the current to a node which is maintained at a generally fixed voltage. Current is mirrored from the fixed voltage node to an output node. Such an active transconductance circuit can meet conventional performance specifications, but at a lower supply current, and/or with lower circuit complexity, and/or with a lower circuit area requirement.

Abstract: One aspect of the embodiments utilizes a filter circuit which can be connected to a signal source has a low-frequency cutoff of 1/(R×C). The filter includes a buffer circuit which can be connected to an output end of the signal source and has an output impedance of R, and a capacitor which is connected to an output end of the buffer circuit in a floating state and has a capacitance of C/2. The filter includes a resistor circuit which is connected to an output end of the capacitor and has a resistance value of R.

Abstract: A low noise nth order filter, system, and method includes a plurality of nested general immittance converters (GICs) operatively connected to one another in successive GIC stages; and a capacitor operatively connected to each of the GICs, wherein a first successive GIC stage begins at a first node located in between a previous GIC stage and a corresponding capacitor operatively connected to the previous GIC stage. A second successive GIC stage begins at a second node located in between the first node and the first successive GIC stage. The filter may further comprise a resistor operatively connected to at least one successive GIC stage, wherein the resistor is preferably located in between the first node and the first successive GIC stage.

Abstract: A noise reduction circuit for AC power, AC power neutral lines, and DC power. In a first embodiment for use with AC power, the invention operates by subtracting the error voltage from an incoming AC signal boosted in voltage by a small boost transformer. In a second embodiment, the present invention reduces noise in AC power neutral lines by effectively operating as a power corrector and reduces unwanted noise on the neutral line at all frequencies without introducing unwanted current in the ground line. In a third embodiment, the invention reduces noise in DC power supplies.

Abstract: A filter includes an input and an output. First and second filter stages having respective stage inputs and stage outputs are connected in cascade between the input and the output. Each filter stage includes an amplifier having an amplifier input and an amplifier output and an inner feedback loop connecting the amplifier output to the amplifier input. An outer feedback loop connects the stage output of the second filter stage with the stage input of the first filter stage. The first and second filter stages and the outer feedback loop are arranged so that an s-space closed-loop transfer function of the filter includes two zeros and a single pole.

Abstract: A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.

Abstract: In a phase compensation circuit having a resistance connected to the output side of an error amplifier, a capacitor, and a conductance amplifier functioning as a capacitance amplifier circuit, capacitance is amplified by the conductance amplifier and used, whereby an essentially required capacitance is ensured, even when the capacitance of the capacitor is small.

Abstract: A variable frequency module controls a cutoff frequency of a high pass filter and includes a resistive element that communicates with a capacitive element of the high pass filter. A first transistor communicates with the resistive element and a reference node and includes a first source/drain region formed in a first well region and a first diode region formed between the first source/drain region and the first well region. A first node of the first diode region is connected to the first source/drain region and the reference node, and a second node of the first diode region is connected to the reference node.

Abstract: A transconductance filtering device with a flexible architecture that can selectively present a different topology and/or order beginning with the same initial structure is disclosed. For example, depending on the communications standard detected, the elementary cells of the filtering circuit required to form the adapted filter are selected and connected in such a manner as to obtain the configuration desired for the filtering means. As an example, the filter may be for use with a wireless communications system forming, in particular, a cellular mobile telephone. The filter is configurable by means of at least two elementary cells of the same structure and of controllable interconnection means each having an open or closed state.

Abstract: A transconductor and filter circuit is described. In one embodiment, a front end module within the transconductor and filter circuit converts a differential input voltage signal into a differential output current and supplies the output current at a differential output. A filter module coupled to the differential output of the front end module receives the differential output current, converts the output current into an intermediary differential voltage, and filters the differential voltage to obtain a filtered differential output voltage signal having low output impedance.

Abstract: A filter circuit includes a voltage amplifier, a resistor, a capacitor, and an analog switch connected between the voltage amplifier and the capacitor. When the voltage amplifier is turned on, the analog switch is opened so that the capacitor is disconnected from the voltage amplifier. Thus, an output voltage of the voltage amplifier sharply increases to its steady state value, as soon as the voltage amplifier is turned on. When the output voltage of the voltage amplifier is fully stabilized, the analog switch is closed so that the capacitor is connected to the voltage amplifier. During the period of time when the analog switch is closed, the filter circuit is configured as an imperfect integrator circuit with filter characteristics that depend on a capacitance of the capacitor and a resistance of the resistor.

Abstract: A circuit has a first capacitive circuit component, having a first terminal and a second terminal, and an amplifier, having a first input and an output, the first input coupled to the first terminal and the output coupled to the second terminal to generate a potential difference between the first terminal and the second terminal.

Abstract: An approach that provides active pre-emphasis for a passive RC network is described. In one embodiment, there is a circuit that comprises an RC filter including a resistive divider formed from a first resistor and a second resistor and a filtering capacitor. The first resistor is configured to receive an input voltage and the second resistor and filtering capacitor are in parallel and configured to generate a reference voltage that is a percentage of the input voltage. An operational amplifier is coupled to the RC filter. A first multiplexer controlled by a pulse pre-emphasis signal is coupled to the operational amplifier and the RC filter. A second multiplexer controlled by a sample and hold clocking signal has inputs that are coupled to the first multiplexer and ground.

Abstract: A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.

Abstract: A filter is electrically coupled to a fan or is built-in with a fan, the filter is also electrically coupled a first power terminal and a second power terminal. The filter includes an amplifier, a capacitor, and a divider. The amplifier includes a first terminal, a second terminal and a third terminal, wherein the third terminal is electrically coupled to a power circuit of the fan. The capacitor is electrically coupled between the third terminal of the amplifier and the second power terminal. The divider is electrically coupled between the first power terminal and the second power terminal, wherein a node of the divider is electrically coupled to the second terminal of the amplifier.

Abstract: Techniques for tuning filters of modulation circuits are described herein.

Abstract: A tuning circuit for tuning an active filter includes a resistor-capacitor circuit comprising a variable capacitor and a resistor equivalent to a first resistor and a second resistor serially connected to the first resistor, a voltage generator for providing a constant reference voltage to the first resistor, a current replicating unit for replicating a current based on the constant reference voltage, a comparator for comparing a charging voltage as the current is charging a variable capacitor with the constant reference voltage, a counter for counting a number of cycles of a clock signal until the charging voltage reaches the constant reference voltage, a adjustment unit for calibrating a capacitance of the variable capacitor based on the number of cycles of a clock signal and a target count value associated with a predetermined RC time constant.

Abstract: In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2.

Abstract: Disclosed is a filter circuit with an order of three or more, comprising at least one means for amplifying an in-band signal, wherein the frequency response of the filter output has a desirable attenuation characteristic obtainable with the order of the filter circuit. The gain of the amplifying means is variably controlled.

Abstract: Various embodiments are disclosed relating filter calibration with cell re-use. According to an example embodiment, an apparatus includes a first circuit, including a variable circuit element. The first circuit is adapted to output an output frequency signal during a calibration mode and to operate as a filter during a filter mode. A control circuit is coupled to the first circuit and is adapted to receive a reference frequency signal and to calibrate the first circuit by adjusting the variable circuit element based on the reference frequency signal and the output frequency signal during the calibration mode. The calibrated first circuit is configured to then operate as a filter during the filter mode.

Abstract: An anti jitter circuit for reducing time jitter in an input pulse train comprises an integrator, a DC removal circuit and a comparator. The anti jitter circuit also has a feedback loop effective to suppress phase deviation of the output pulse train in response to jitter.

Abstract: Tuning circuits and related method for tuning transconductance in a transconductor-capacitor (Gm-C) filter system are provided. In the tuning circuit, a periodic input signal with constant amplitude triggers a transconductor cell to charge/discharge a capacitor for building an output signal across the capacitor, and a magnitude-detection feedback circuit provides feedback to tune a transconductance of the transconductor cell according to a magnitude of the output signal, such that the magnitude of the output signal can be locked within a predetermined magnitude range. When the magnitude of the output signal is locked, the ratio between transconductance and capacitance is also locked to a predetermined value because the magnitude of the output signal is determined by a ratio between transconductance and capacitance.

Abstract: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of the reference capacitor by a factor of N+1, based on the reference capacitor current. The current mirror arrangement includes an operational amplifier operating in conjunction with two mirror transistors to form a current mirror arrangement having little or no series resistance. The current mirror also can include a plurality of resistors configured to reduce the noise from the capacitance multiplier, thus making the capacitance multiplier useful for applications that may require relatively low noise.

Abstract: The present invention relates to a filter and, more particularly, to a tuning circuit of a filter for correcting a cut-off frequency of the filter. The tuning circuit comprises a current generation unit having a first transistor and a variable resistor unit, and a capacitance correction unit having a second transistor, a capacitor unit, an up-down counter and a selection unit for selecting a control path of the up-down counter for varying the resistance or capacitance.

Abstract: A first transistor includes: a first terminal that receives one of differential input signals; a second terminal that receives a control signal for varying an impedance; a third terminal connected to the second transistor; and a fourth terminal that supplies a potential to a substrate. A second transistor includes: a fifth terminal that receives the other of the differential input signals; a sixth terminal that receives a control signal, the seventh terminal connected to the first transistor, and the eighth terminal that supplies a potential to a substrate. The third terminal, the fourth terminal, the seventh terminal, and the eighth terminal are connected together.