Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: The invention provides an electrode arrangement for a capacitive sensor device and for a capacitive sensor, respectively, for detecting a position and/or an approach of an object, which comprises a sensor electrode and a first shield electrode, wherein the sensor electrode is arranged on a first side of a substantially flat substrate with a first side and a second side, and wherein the first shield electrode is arranged on the second side of the substrate and serves for shielding the alternating electric field emitted by the sensor electrode from ground. There is also provided a foil with an electrode arrangement according to the invention as well as a method for the production of a display arrangement with an electrode arrangement according to the invention.

Abstract: An active analog filter (700, 1000) having a MOS capacitor device (730, 1030) with improved linearity is proposed. In an exemplary embodiment, dc bias voltage sources (755, 745) alter the capacitance of MOS varactors (740, 750) connected in anti parallel so that the total capacitance of the MOS capacitor device remains constant or within a range over the voltage range of the filter and the filter linearity is set. In a further exemplary embodiment the output stage (1070) of the operational amplifier circuit (1020) of the active analog filter (1000) is modified so that the dc bias voltage is provided by resistors (1055, 1045) connected to a current source (1060) already existing in the filter. Thus the linearity is set and the die area is significantly reduced.

Abstract: A circuit includes a first filter comprising a first inductor coupled to a first variable capacitor, wherein the first filter is associated with a first resonant frequency. The circuit further comprises an amplifier coupled to the first filter and a second filter coupled to the amplifier. The second filter comprises a second inductor coupled to a second variable capacitor, wherein the second filter is associated with a second resonant frequency that is substantially the same as the first resonant frequency. At least a portion of the first filter and at least a portion of the second filter are formed on an integrated circuit.

Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.

Abstract: A system according to one embodiment includes an analog input for receiving an analog signal; a variable gain amplifier coupled to the analog input; a first integrator coupled to the variable gain amplifier for controlling the gain of the analog signal; a second integrator generating control signals for controlling functions of the first integrator; a serializer for serializing the control signals; and a deserializer coupled to the serializer for deserializing the control signals and passing the deserialized control signals to the first integrator.

Abstract: A high-frequency switch module includes a FET switch mounted on a multilayer substrate and a low pass filter arranged between the FET switch and a transmission signal input terminal. The low pass filter includes at least one inductor connected in series between a transmission input port and the transmission signal input terminal, a first capacitor, one end of which is connected to the transmission input port and the other end of which is grounded, and a second capacitor, one end of which is connected to the transmission signal input terminal and the other end of which is grounded, and the first capacitor and the second capacitor have different capacitance values.

Abstract: An integrator is described that may include a level-shifting capacitor, a feedback capacitor, a pre-amplifier stage and a multi-path amplifier module. The integrator may have inputs for connected an input signal source to the level-shifting capacitor. The level-shifting capacitor is connected to an input of a pre-amplifier stage of an integration signal path and to the input. The level-shifting capacitor may level shift the voltage at the input of the circuit to a lower voltage at the input of the pre-amplifier stage. Thereby, the supply voltage to the pre-amplifier stage may be reduced as well as have limited power consumption, limited temperature rise, and reduced noise that may be attributed to any thermal effects.

Abstract: A filter circuit includes a differential amplifier circuit to provide a number of poles including a dominant pole, and a feedback circuit to feed a portion of an output of the differential amplifier circuit to an input of the differential amplifier circuit. The feedback circuit includes a feedback resistor and a feedback capacitor to provide a controllable increase in an order of a transfer function of the filter circuit along with non-dominant poles of the differential amplifier circuit coupled in parallel with the feedback resistor. Coefficients of a transfer function of the differential amplifier circuit are forced to substantially depend solely on one or more of a plurality of passive circuit elements, the feedback resistor, and the feedback capacitor to control a dependence of the transfer function of the filter circuit on a gain of the differential amplifier circuit and poles of the differential amplifier circuit.

Abstract: The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.

Abstract: A feedback resistor is connected between an input terminal and an output terminal of an operational amplifier. A negative resistor is connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.

Abstract: A transconductance-capacitance (Gm-C) filter of arbitrary order is provided that is biased by a bias circuit such that the Gm-C filter is robust to variations in process corner and temperature as well as input supply noise. The bias circuit includes a biased transistor that has a width-to-length ratio that is a factor X times larger than a corresponding transistor in the Gm-C filter. The biased transistor couples to ground through a switched capacitor circuit.

Abstract: Provided is a method for performing analog to digital conversion of a plurality of analog signal channels. The method may comprise successively processing each analog signal channel of a plurality of analog signal channels. The processing of an analog signal channel of the plurality of analog signal channels may comprise: selecting the analog signal channel from the plurality of analog signal channels, generating an analog output signal corresponding to an analog input signal transmitted over the selected analog signal channel, and sampling the analog output signal using a successive approximation register (SAR) converter. Sampling the analog output signal using a SAR converter may comprise sampling the analog output signal a specific number of times to produce a respective plurality of digital samples corresponding to the selected analog input signal.

Abstract: A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between an input clock signal and an output clock signal. The loop filter multiplies the phase error signal and filters the multiplied phase error signal. The compressor divides the loop filter output. Based on the compressor output, the clock generator generates an output clock signal is provided as a feedback signal to the phase error detector. The apparatus may also include a glitch cleaner for deglitching the input clock signal.

Abstract: A semiconductor switching device includes a field effect transistor and an inductor structure that provides a frequency dependent inductance in a parallel connection. During the off-state of the semiconductor switching device, the frequency dependent impedance component due to the off-state parasitic capacitance of the switching device is cancelled by the frequency dependent inductance component of the inductor structure, which provides a non-linear impedance as a function of frequency. The inductor structure provides less inductance at a higher operating frequency than at a lower operating frequency to provide more effective cancellation of two impedance components of the parasitic capacitance and the inductance. Thus, the semiconductor switching device can provide low parasitic coupling at multiple operating frequencies. The operating frequencies of the semiconductor switching device can be at gigahertz ranges for millimeter wave applications.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: A device comprises at the input a first component (PA) having a first output impedance (Z1), at the output a second component (ANT) having a second input impedance (Z2), and an impedance-matching network between said first and second components. Because the first and/or the second impedance vary/varies, said impedance-matching network comprises a filter (Fadp), with an impedance that is matchable to the first and second impedances, located between said first and second components and comprising at least two acoustic wave coupled resonators. At least one of the resonators comprises a perovskite type material and means for applying a voltage to said resonator, which enable the permittivity and the impedance thereof to be varied.

Abstract: The disclosed invention enables the cutoff frequency of a filter to be automatically adjusted to an arbitrary setting value within the adjustment range. An automatic cutoff frequency adjusting circuit includes a voltage/current converter circuit, a charge circuit, a discharge circuit, a digital capacitance having a plurality of electrostatic capacitances, a comparator for comparing a voltage inputted to the digital capacitance with a reference voltage, and a capacitance control circuit for controlling the digital capacitance. The time until the comparator detects that the voltage inputted to the digital capacitance is higher than the reference voltage after a reset signal has become a predetermined logic level is measured, and the digital capacitance is controlled by repeating, under a predetermined condition, processing for obtaining a next setting value of the digital capacitance, based on a measurement result, a target value of the digital capacitance, and the current value of the digital capacitance.

Abstract: According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.

Abstract: A high pass filter has a cutoff frequency. The high pass filter includes a first amplifier to receive an input signal. The high pass filter attenuates low frequency signals of the input signal that are below the cutoff frequency. A second amplifier provides an output signal. The output signal comprising only high frequency signals of the input signal that are above the cutoff frequency. A capacitive element is coupled in between the first amplifier and the second amplifier. A variable frequency module controls a plurality of resistive paths of the high pass filter. Each resistive path corresponds to a different cutoff frequency for the high pass filter. The variable frequency module is configured to prevent any leakage current from draining the capacitive element.

Abstract: A The present invention relates to a phase matching band-pass filter using exponential function approximation, comprising an inductor including a parasitic resistor, a first device wherein a first amplifier is connected in a feedback mode, a capacitor including a parasitic resistor, a plurality of filter devices including a second device that is connected with a second amplifier in a feedback mode, and a coupling capacitor that connects the plurality of filter devices; the impedance of the first device has an increasing exponential function relation with a frequency, impedance of the second device has a decreasing exponential function relation with the frequency, and the first device is connected with the second device in parallel. According to the phase matching band-pass filter using exponential function approximation of this invention, conventional inductors and capacitors can be used 0 without modification or use of negative resistance, resulting in a high-performance phase matching band-pass filter.

Abstract: In varying embodiments, the present inventive concepts relate to a notch filter for quadrature and differential signaling. No inductor is used in this notch filter, thus the integrated circuits silicon die area is small. In addition, the linearity of the notch filter is excellent because of the linearity of the resistors and capacitors in integrated circuits.

Abstract: A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment.

Abstract: Provided is a discrete filter capable of increasing degree of freedom of design including a DC gain. A sampling mixer (100) includes: a control signal generation unit (104) which generates a control signal including an SO signal; a Ch (6) which successively integrates reception signals sampled by an LO signal frequency as discrete signals; a plurality of Cr (7, 8) which successively integrate discrete signals at a timing based on the control signal; Cb (15) which alternately integrates the discrete signals successively integrated by the respective Cr (7, 8); and a gain control capacitance unit (110) which has gain control capacitors (44, 45, 46) connected in parallel to the respective Cr (7, 8) and integrating the discrete signal and a reset switch (47) for resetting the discrete signal of the gain control capacitors (44, 45, 46) integrated in the past, upon connection between one end of Cr (7) and Cb (15).

Abstract: A method and apparatus for clock signal noise shaping are described. Embodiments of a clock circuit include a filter coupled to receive an input clock signal and to provide an output clock signal. The filter filters noise of the input clock signal to shape the noise to provide the output clock signal. In a method for adjustment of phase noise, input clock signaling having the phase noise is obtained, and the input clock signal is filtered to adjust the phase noise to provide output clock signaling.

Abstract: A radio frequency (RF) mixing circuit including a quadrature mixer that receives non-overlapping in-phase and quadrature local oscillator (LO) signals, and a plurality of low noise amplifiers (LNAs) operatively connected to the quadrature mixer, the plurality of LNAs presenting an input impedance at a baseband. A first voltage at an input node of the quadrature mixer is equal to a second voltage across the impedance up-converted to a frequency of a LO signal received by the quadrature mixer. The second voltage across the LNA input impedance includes a frequency of an input signal of the quadrature mixer down-converted by a frequency of the in-phase and quadrature LO signals and filtered by the impedance. The quadrature mixer down-converts an input signal by a frequency of the in-phase and quadrature LO signals and transfers the noise cancelled impedance to a RF to achieve a noise cancelled match.

Abstract: A low-pass filter of the present invention comprises a plurality of filter units and a regulation unit. The filter units are coupled in series with each other and receive an input signal to filter the input signal for generating an output signal. The regulation unit is coupled to the filter units to regulate voltage levels of the filter units. The low-pass filter of the present invention can be integrated within the integrated circuit and reduce the prime cost.

Abstract: Provided is a discrete filter capable of adjusting the number of notches and the notch frequency and easily eliminating a particular frequency component. In a sampling mixer (100), a control signal generation unit (104) generates a plurality of control signals having the same frequency and different phases. A convolution capacity unit (110) integrates the discrete signals obtained by sampling reception signals by using convolution capacitors at a timing based on the control signals. The signals integrated by the convolution capacitors are successively emitted at the timing based on a control signal other than the control signals used for the integration timing. Cb (15) integrates the emitted discrete signals.

Abstract: Exemplary embodiments of the present disclosure provide a method and controller for damping multimode electromagnetic oscillations in electric power systems which interconnect a plurality of generators and consumers. The controller for damping such oscillations includes a phasor measurement unit (PMU) and a power oscillation damper (POD) controller. Each oscillating mode signal is damped and then superposed to derive a control signal. A feedback controller is used to feedback the control signal to a power flow control device in the power system.

Abstract: The present invention reduces harmonic components of an RF transmission output signal. In the semiconductor integrated circuit which the present invention provides, a transmission switch of an antenna switch thereof includes transmission field effect transistors whose S-D current paths are coupled between a transmission terminal and an input/output terminal and whose gate terminals are coupled to a transmission control terminal. A reception switch of the antenna switch includes reception field effect transistors whose S-D current paths are coupled between the input/output terminal and a reception terminal and whose gate terminals are coupled to a reception control terminal. The transmission and reception n-channel MOS field effect transistors are respectively formed in a silicon-on-insulator structure.

Abstract: A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures.

Abstract: Apparatus and methods for providing integrated RF notch filter subsystems having enhanced Q values are described. An integrated notch filter includes an LC filter element and a Q-enhancement circuit coupled to the LC filter element, with the Q-enhancement circuit configured to offset resistive losses in the LC filter element to adjust the Q value of the filter system. A transceiver having multiple LNAs for various bands may be provided to a single notch filter system including a Q-enhancement circuit.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.

Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.

Abstract: A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps.

Abstract: A notch filter suitable for attenuating certain frequencies of a radio-frequency signal includes an input for receiving the radio-frequency signal and an output for the output of a portion of the radio-frequency signal, first and second capacitive means, at least one inductor and a negative resistance circuit suitable for compensating the resistive losses of said at least one inductor. The inductor and the first and second capacitive means are placed to produce a resonator and the filter comprises a control device suitable for controlling the negative resistance circuit. The input impedance of the filter comprises a pole and a zero, with the pole depending on the second capacitive means and the zero depending on both the first and second capacitive means. The first and second capacitive means are variable and the control device is suitable for controlling the first and second capacitive means.

Abstract: A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Abstract: The voltage-current converter of the present invention includes a converter input terminal, a converter output terminal, a voltage-current conversion unit for converting voltage that is applied as input to the converter input terminal to current, and a current extraction unit for intermittently extracting current from the output terminal of the voltage-current conversion unit and supplying this current as output from the converter output terminal.

Abstract: An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.

Abstract: A cost-effective device for influencing the transmission of electrical energy of an alternating voltage line with a plurality of phases has phase modules, which each have an alternating voltage terminal for connecting to a phase of the alternating voltage line and two connecting terminals. A phase module branch extends between each connecting terminal and each alternating voltage terminal. The phase module branch is formed of a series connection of sub-modules, each having a power semiconductor circuit and an energy accumulator connected in parallel to the power semiconductor circuit. The connecting terminals are connected to one another. The power semiconductor circuit is equipped with power semiconductors that can be switched off and are connected to each other in a half bridge.

Abstract: A filter circuit that removes high-frequency components from an input signal, comprises: an operational amplifier; a first resistor connected between a non-inverting input terminal of the operational amplifier and an input signal source; a first capacitor connected to the non-inverting input terminal of the operational amplifier; a second resistor connected to the non-inverting input terminal of the operational amplifier; a third resistor connected between an inverting input terminal of the operational amplifier and the input signal source; a second capacitor connected between the inverting input terminal of the operational amplifier and an output terminal of the operational amplifier; and a fourth resistor connected to the inverting input terminal of the operational amplifier.

Abstract: The discrete-time receiver system includes: a voltage current conversion device low-noise-amplifying an input voltage signal, and converting the amplified signal into a current signal; a first filter performing IIR filtering on the current signal output from the voltage current conversion device; a discrete-time filter performing FIR filtering on a signal output from the first filter; and a second filter performing IIR filtering on a signal output from the discrete-time filter, wherein the discrete-time filter includes a plurality of current supply units generating a current having a size obtained by multiplying an input current by a determined gain, respectively, an adding unit adding currents supplied from the plurality of current supply units, and a plurality of controllers connecting the plurality of current supply units and the adding unit and controlling the flow of current supplied from the current supply units to the adding unit.

Abstract: A digital proportional integral loop filter is provided. A first proportional amplification unit multiplies a phase error value by a first proportional loop gain, and a first integral amplification unit multiplies a phase error accumulation value by a first integral loop gain. A second proportional amplification unit multiplies the phase error value by a second proportional loop gain, and a second integral amplification unit multiplies the phase error accumulation value by a second integral loop gain. A first offset value generation unit generates a first offset value by subtracting the second proportional loop gain from the first proportional loop gain and multiplying a resulting value by a phase error average value, and a second offset value generation unit generates a second offset value by subtracting the second integral loop gain from the first integral loop gain and multiplying a resulting value by a phase error accumulation average value.

Abstract: In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.

Abstract: A system provides a high quality, and intuitive multi-band filter that adapts when noise frequencies or noise amplitudes change. A system for adaptively filtering patient monitoring signals, comprises a filter controller for adaptively determining the number of, and individual filter bandwidth of, multiple adaptive signal filters to be used in filtering multiple bandwidths within an encompassing signal filtering bandwidth. The filter controller does this in response to, (a) noise data indicating noise source frequencies and (b) configuration data determining medical signal or noise source characteristics, to provide programming data for programming a plurality of adaptive signal filters. The system includes multiple adaptive signal filters individually having a filtering bandwidth and filtering characteristic programmable in response to received programming data. A noise detector automatically identifies a noise component in a received patient monitoring signal and generates the noise data.

Abstract: The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the output of an otherwise ideal Discrete Time Filter (DTF) circuit, and the quick creation of the signal merely requires a designer to input the number of taps and their weights without the need of laying out or considering the circuitry of the DTF. A matrix is created based on a given data stream, and the number of taps and weights, which matrix is processed to create the multi-unit-interval data signal. Noise and jitter can be added to the created signal such that it now realistically reflects non-idealities common to actual systems. The signal can then be simulated using standard computer-based simulation techniques.