Abstract: There is provided a filter device having a function of adjusting the center frequency of a filter. The filter device includes: a filter core unit (102) provided with an adder (109) for outputting an added signal of an input signal and a feedback signal (signal Vf), an AGC circuit for generating an amplification signal in which the added signal is amplified, and a phase shifter (111) for generating the signal Vf by shifting a phase of the amplification signal; an amplitude comparing circuit (101) for comparing the reference amplitude and the amplitude of the signal Vf; a gain control voltage generator (108) for controlling the amplification factor of the AGC circuit (110) based upon the comparison result; a frequency comparing circuit (103) for comparing the reference frequency and the frequency of the signal Vf; a phase shifter control voltage generator (117) for controlling the shift amount of the phase in the phase shifter (111) based upon the comparison result.

Abstract: A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology.

Abstract: A filtering arrangement comprises a reference voltage input (1) and a compensation current arrangement (10) coupled to the reference voltage input (1) and configured to provide a control current at a current output (2) as a function of a voltage at the reference voltage input (1). The filtering arrangement also comprises a first and a second current source (20, 30) each having a control input (4, 5) coupled to the current output (2), a first and a second filter input (7, 8), and a first transistor (T1) and a second transistor (T2). The first transistor (T1) has a first connection (T11), a second connection (T12) and a control connection (T1c), where its first connection (T11) is coupled to the first current source (20) and its second connection (T12) is coupled to the first filter input (7) through a first resistor (R1).

Abstract: Systems and methods which provide DC current path circuitry, such as for providing a DC bias, in association with a filter circuit such that parasitic attributes of the DC current path circuitry combines with the filter component attributes are shown. According to embodiments, the parasitic attributes of the DC current path circuitry components are added into the associated filter circuit network design. A parasitic capacitance of the DC current path circuitry may, for example, be aggregated with a capacitor of the filter circuit to eliminate or mitigate the effect of the presence of the DC current path circuitry on the associated filter frequency response. Embodiments implement an active inductor configuration for providing a DC current path in association with a filter circuit. An active inductor of embodiments is provided using a transistor, appropriately biased to actively exhibit low impedance at DC and high impedance at RF frequencies.

Abstract: A filter circuit includes two parallel digital filters, a DAC, and an LPF. The DAC includes two parallel decoders, a parallel-to-serial converter, a switch driver, and a switch. A PLL circuit supplies a reference clock to the DAC. A frequency divider provided in the DAC divides the frequency of the reference clock by two, and supplies the half frequency clock to a parallel processing section (the two decoders and the parallel-to-serial converter) of the DAC and the two digital filters. This makes it easy to secure a timing margin, permitting use in high-speed communication on the order of several GHz.

Abstract: There is provided a filter circuit that includes: a flying capacitor which maintains polarity when switching from an input terminal to an output terminal, and the polarity of which is reversed when switching from the output terminal to the input terminal; a first capacitor that is provided in parallel with the flying capacitor, at the input terminal of the flying capacitor; and a second capacitor that is provided in parallel with the flying capacitor, at the output terminal of the flying capacitor. The flying capacitor is switched from the input terminal to the output terminal with a delay of a predetermined time after the switching from the output terminal to the input terminal, and the flying capacitor is switched from the output terminal to the input terminal with a delay of a predetermined time after the switching from the input terminal to the output terminal.

Abstract: A transconductance-capacitance (Gm-C) filter of arbitrary order is provided that is biased by a bias circuit such that the Gm-C filter is robust to variations in process corner and temperature as well as input supply noise. The bias circuit includes a biased transistor that has a width-to-length ratio that is a factor X times larger than a corresponding transistor in the Gm-C filter. The biased transistor couples to ground through a switched capacitor circuit.

Abstract: A discrete time filter includes a plurality of sampling cells and a first dummy sampling cell. Each of the sampling cells performs a current mode sampling operation based on current input to an input terminal in response to a corresponding one of a plurality of sampling clock signals and is reset in response to a corresponding one of the plurality of sampling clock signals and a first dummy sampling clocks. The first dummy sampling cell alternately performs with the first sampling cell the current mode sampling operation based on current input to the input terminal in response to the first dummy sampling clock signal and is alternately reset with the first sampling cell in response to the first sampling clock signal.

Abstract: Aspects of the disclosure can provide a second order low pass filter. The second order low pass filter can work in current domain, and have high linearity for in-band signals and out-of-band signals. The second order low pass filter can include a MOS transistor having a gate terminal, a current input terminal and a current output terminal, a first capacitor coupled between the current input terminal and a ground connection and a second capacitor coupled between the gate terminal and the current input terminal.

Abstract: A filter circuit is employed to filter undesirable harmonics in a multi-phase AC input and provide damping for oscillations associated with the filter circuit. The filter circuit includes a damping circuit connected between phases of the multi-phase AC input. The damping circuit including a rectifier for rectifying harmonics in the multi-phase AC input and a single damping resistor connected across the rectifier.

Abstract: A relaxation oscillator for generating a first and a second oscillation signals, comprising: a reference-voltage providing circuit for providing a high and a low reference voltages; switches for directing the high and low reference voltages to inputs of a transconductance amplifier and a non-inverting input of a comparator; the transconductance amplifier for generating an output current with a value determined by its transconductance value, controlled by an input tuning voltage, and multiplied by its inputs' voltage difference; a capacitor connecting between the transconductance amplifier output and ground; and the comparator for generating a first and a second digital signals; wherein the first and second digital signals are digital control signals to the switches, and the first and second oscillation signal of the relaxation oscillator respectively; wherein the oscillation frequency of the relaxation oscillator is independent of the reference voltages, achieving accurate frequency turning, and simplifying t

Abstract: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Abstract: A low-pass filter, including: between a first terminal and a second terminal, a series association of a first resistor, of a second resistor, and of a first amplifier; in parallel with the second resistor, a series association of a second amplifier and of a first capacitor; a second capacitor between an input of the first amplifier and a third terminal of application of a reference voltage; and a third capacitor between the second terminal and the third terminal.

Abstract: A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.

Abstract: The device described herein proposes an electronic active filter void of capacitors and inductors. The circuit utilizes only operational amplifiers (Op-Amps) and resistors, hence the name Op-R. Although capable of being constructed of lumped circuit elements this filter is intended for integrated circuit (IC) applications. Filtering of signals can be accommodated sub-audio through the video frequency range depending on the selected op-amp ICs. Low pass, band pass, high pass, as well as ban reject frequency responses are achievable. Although the circuits described herein are single input-single output, multiple inputs and outputs present no difficulty, being limited only by chip space. Temperature and production spread variations are also considered within the realm of tenability.

Abstract: A method of and circuit for improving stabilization of a non-Foster circuit. The method comprises steps of and the circuit includes means for measuring a noise hump power at an antenna port or an output port of the non-Foster circuit, comparing the measured noise hump power with a desired level of noise power that corresponds to a desired operating state of the non-Foster circuit, and tuning the non-Foster circuit to generate the desired level of noise power to achieve the desired operating state of the non-Foster circuit.

Abstract: A current-mode filter includes a first, a second, and a third transistor having the same channel polarity. The drain of the first transistor is connected to the source of the second transistor functioning as a gate grounded circuit. The drain of the second transistor is connected to the gates of the first and third transistors. A first and a second capacitive element are connected to the gate and drain of the first transistor. The current source supplies a bias current to each of the first and second transistors. The drain of the first transistor is used as an input terminal. An output signal is extracted from a drain current of the third transistor. Therefore, only one transconductance adjustment circuit is enough.

Abstract: An exemplary filter includes N (?2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N?1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N?1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract: An integrated circuit (IC) includes first and second resonator circuits and an isolation barrier. The first resonator circuit includes first and second inductors, wherein the first resonator circuit is connected to a supply voltage. The second resonator circuit includes third and fourth inductors, wherein the second resonator circuit is matched to the first resonator circuit. The isolation barrier separates the first and second resonator circuits. The first and second inductors are inductively coupled to the third and fourth inductors, respectively, thereby providing for transfer of power from the first resonator circuit across the isolation barrier to the second resonator circuit.

Abstract: A line filter includes at least one X capacitor located between two supply lines and at least one discharge resistor that discharges the X capacitor, wherein the discharge resistor is arranged in series with at least one switching element, and at least one detector circuit that detects a network disconnection and closes the switching element to discharge the X capacitor via the discharge resistor when a network disconnection is recognized.

Abstract: A filter including common mode feedback can provide single-ended to differential-ended conversion with minimum loss of performance.

Abstract: An equalizer includes an oversampling logic unit, a direct current setting unit, and an alternating current setting unit. The oversampling logic unit oversamples data from a channel to generate a plurality of direct current terms and a plurality of alternating current terms according to an oversampling clock, and outputting a plurality of direct current terms corresponding to an output clock and a plurality of alternating current terms corresponding to the output clock according to the output clock. The direct current setting unit adjusts a direct current setting of the equalizer according to a plurality of direct current terms inputted by the oversampling logic unit within a first predetermined time. And the alternating current setting unit adjusts an alternating current setting of the equalizer according to a plurality of alternating current terms inputted by the oversampling logic unit within the first predetermined time.

Abstract: A charge domain filter (CDF) and a bandwidth compensation circuit of the CDF are provided. The CDF includes an amplifier, a plurality of switch-capacitor networks (SCNs), a connector, a current adder (CA) and a bandwidth compensation circuit. A first input terminal of the amplifier receives an input signal, and an output terminal thereof is connected to input terminals of the SCNs. The connector is connected between the output terminal of the SCNs and the CA for configuring coupling status of the output terminals of the SCNs and input terminals of the CA. The bandwidth compensation circuit senses a portion of or all of the output terminals of the SCNs and the CA, and outputs the sensing result to a second input terminal of the amplifier.

Abstract: Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of 50 MHz to 20 GHz or more. Example devices include integrators (transconductors), digitally controlled attenuators, buffers, and scalable summers implemented using deep sub-micron CMOS technology. Because the devices are implemented in CMOS, the ratio of trace/component size to signal wavelength is about the same as that of low-frequency devices implemented in printed circuit boards. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing.

Abstract: The present disclosure relates to a first active tunable low-noise RF bandpass filter that includes at least a first transistor element and a tunable frequency selective degeneration circuit coupled to a first non-inverting output of the first transistor element. The first active tunable low-noise RF bandpass filter combines low noise amplifier (LNA) and tunable bandpass filter functionalities into a single active RF bandpass filter. The tunable frequency selective degeneration circuit uses degeneration at frequencies outside of a passband of the active RF bandpass filter to increase feedback, thereby decreasing gain of the active RF bandpass filter. By decreasing the gain, linearity of the active RF bandpass filter may be improved in the presence of strong interfering RF signals, thereby enabling elimination of passive bandpass filter elements, such as surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, without degrading reception of in-band RF signals.

Abstract: A low-pass filter includes an integrator having an adjustable unity frequency. The integrator includes a first input, first output and feedback loop between the first input and output of the integrator. The first input is connected to a branch that includes a first impedance, to which is applied a first input voltage of the low-pass filter. The feedback loop includes a second impedance and the first output of the integrator is the first output of the low-pass filter.

Abstract: Provided is a fully differential adaptive bandwidth phase locked loop with differential supply regulation. One fully differential phase locked loop includes a differential active loop filter and regulator coupled to an output of a differential charge pump, a differential voltage-controlled oscillator coupled to differential control voltages developed by the differential active loop filter and regulator, and a bias circuit coupled to the differential control voltages and providing a bias current to the differential charge pump.

Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.

Abstract: An adaptive filter circuit for sampling a reflected voltage of a transformer of a power converter includes a first switch for receiving the reflected voltage, a resistor having a first terminal and a second terminal, the first terminal of the resistor being coupled to the first switch, a capacitor coupled to the second terminal of the resistor for holding the reflected voltage, and a second switch coupled to the resistor in parallel, wherein the resistor and the capacitor develop a filter for sampling the reflected voltage which is sampled without filtering by the filter in a first period during a disable period of a switching signal and also sampled with filtering by the filter in a second period during the disable period of the switching signal.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.

Abstract: For voltage interpolation amplifiers used in digital-to-analog converter architecture, the number of input differential pairs required by the voltage interpolation amplifier may be reduced such that an N-bit voltage interpolation amplifier comprises N+1 input differential pairs connected through a resistor attenuation network to provide a binary-weighted effective transconductance. In comparison to conventional voltage interpolation amplifier designs, the number of input differential pairs and power consumed by the circuit is significantly reduced, thereby creating a more area- and power-efficient voltage interpolation amplifier.

Abstract: A method of attenuating an input signal to obtain an output signal is described. The method comprises receiving the input signal, attenuating the input signal with a gain factor to obtain the output signal, applying a filter having a frequency response with a frequency-dependent filter gain to at least one of a copy of the input signal and a copy of the output signal to obtain a filtered signal, the frequency-dependent filter gain being arranged to emphasize frequencies within a number N of predetermined frequency ranges, N>1; wherein the filter comprises a sequence of N sub-filters, each one of the N sub-filters having a frequency response adapted to emphasize frequencies within a corresponding one of the N predetermined frequency ranges; determining a signal strength of the filtered signal, and determining the gain factor from at least the signal strength.

Abstract: An acoustic characteristic control apparatus supplies music signal, for example, to input terminal connected to a band-pass filter and a peaking filter. In a zero-cross detection circuit, a pulse signal corresponding to a period while a signal is positive is formed. A pulse-width measuring circuit output a signal corresponding to a pulse width. Next, the output of the pulse-width measuring circuit is inputted to one comparator and another comparator. The one comparator discriminates a time when the pulse width is equal to or larger than a first setting value, and the another comparator discriminates a time when the pulse width is equal to or smaller than a second setting value. The comparator is connected to the up terminal and the down terminal of an up/down counter. The output of the up/down counter is connected to the peaking filter through the subtractor, and acoustic characteristics of the peaking filter is controlled according to the count value of the up/down counter.

Abstract: In an image rejection mixer, when a signal in the first radio frequency band is inputted to an input terminal, the first mixer and the second mixer convert the input signal in the first radio frequency band to a signal in the first intermediate frequency band by using the first local signal from a local signal oscillator, and a filter circuit attenuates an image interfering signal existing in the first intermediate frequency band by means of the first attenuation band. Also, when a signal in the second radio frequency band is inputted to the input terminal, the first mixer and the second mixer convert the input signal in the second radio frequency band to a signal in the second intermediate frequency band by using the second local signal from the local signal oscillator, and the filter circuit attenuates an image interfering signal existing in the second intermediate frequency band by means of the second attenuation band that is narrower than the first attenuation band.

Abstract: A circuit containing a pair of charge pumps and an active filter receives outputs of a phase frequency detector used in a phase locked loop. The charge pump is implemented using switches and resistors to reduce performance variations due to component mismatches. The loop filter includes a resistor and a capacitor coupled in series, the resistor and the capacitor determining a zero of the transfer function of the loop filter. The charge pump circuit simultaneously injects a first current pulse at a first node of the loop filter and a second current pulse at a second node formed by a junction of the resistor and the capacitor. The polarity of the first current pulse is the opposite of the polarity of the second current pulse. Multiplication of the capacitance of the capacitor is thereby achieved, enabling implementation of the loop filter in integrated circuit form.

Abstract: An exemplary filter includes N (?2) unity gain amplifiers, each with a pair of differential input terminals and a pair of differential output terminals; a pair of filter differential input terminals; a first pair of variable resistances coupling the pair of filter differential input terminals to the pair of differential input terminals of the first unity gain amplifier; N?1 pairs of variable resistances coupling the pairs of differential output terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential input terminals of its downstream neighbor; N?1 pairs of variable capacitances coupling the pairs of differential input terminals of each of the N unity gain amplifiers, other than the last one, to the pairs of differential output terminals of its downstream neighbor; and a variable capacitance coupling the pair of differential input terminals of the last unity gain amplifier to each other.

Abstract: An active RC resonator includes a first operational amplifier having first and second inputs and first and second outputs, a second operational amplifier having first and second inputs and first and second outputs, a first resistor coupled between the first input of the first operational amplifier and the second output of the second operational amplifier, a second resistor coupled between the second input of the first operational amplifier and the first output of the second operational amplifier, a third resistor coupled between the first output of the first operational amplifier and the first input of the second input of the second operational amplifier, a fourth resistor coupled between the second output of the first operational amplifier and the second input of the second operational amplifier, and at least one of 1) a first capacitor coupled between the first input of the first operational amplifier and the first output of the second operational amplifier, and a second capacitor coupled between the second

Abstract: An initialization circuit comprises a section signal generator generating a section signal, of which a prescribed section is enabled in response to a power-up signal, a first oscillator generating a first period signal in response to the section signal, a first period multiplier generating a first multiplied signal by multiplying a period of the first period signal, and a signal selector transferring the first multiplied signal or a second multiplied signal selectively as a self-refresh enable signal in response to the section signal.

Abstract: An active poly-phase filter has a converting section and a filtering section having two first input terminals, two second input terminals and four output terminals. The converting section has first, second, fourth and fifth transistors forming a translinear circuit and a third transistor forming a current mirror circuit with the second transistor. The converting section converts unbalanced high-frequency power into a difference input between a collector current of the third transistor and a collector current of the first transistor having phase difference of ? radians. The filtering section receives one collector current at the first input terminals and receives another collector current at the second input terminals and outputs a first difference output between outputs of two output terminals and a second difference output between outputs of other two output terminals such that the difference outputs has a phase difference of ?/2 radians.

Abstract: Power amplifying systems and modules and components therein are designed based on CRLH structures, providing high efficiency and linearity.

Abstract: A circuit and method for filtering a signal. An amplifier (330) receives an input signal (310) and generates a differential output signal. A first resonator (340) having series and parallel resonant frequencies is connected to the positive output port (335) of the amplifier. A second resonator (350) having series and parallel resonant frequencies is connected to the negative output port (336) of the amplifier. The first and second resonators are coupled at a connection point (340). A buffering device (370) receives the combined outputs of the resonators and outputs a filtered signal. The filtering method receives signals and passes them through the elements of the filter circuit to generate a filtered output signal.

Abstract: Techniques are generally described herein related to filters including first operational transconductance amplifier (first OTA) and a second operational transconductance amplifier (second OTA). In some examples described herein, the first OTA and second OTA have substantially the same transconductance. The first and second OTAs can be configured to realize filters such as first-order all-pass filters, second-order all-pass filters, higher-order all-pass filters, and quadrature oscillators.

Abstract: The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the output of an otherwise ideal Discrete Time Filter (DTF) circuit, and the quick creation of the signal merely requires a designer to input the number of taps and their weights without the need of laying out or considering the circuitry of the DTF. A matrix is created based on a given data stream, and the number of taps and weights, which matrix is processed to create the multi-unit-interval data signal. Noise and jitter can be added to the created signal such that it now realistically reflects non-idealities common to actual systems. The signal can then be simulated using standard computer-based simulation techniques.

Abstract: A module for an active mains filters for determining reference currents for a subsequent current adjustment control with transformation of the inflowing currents, first determines active power of the load, then directly calculates the reference currents taking into account the active power and the ?-? components of the mains voltage. A module for an active mains filter for compensating one or more harmonic currents or voltages using selective signal analysis and an active mains filter for a 3-phase supply mains with a reference module for determining reference currents are also provided.

Abstract: An active filter includes a first filter and a second filter. The first filter receives an input signal, and generates a first output signal by filtering the input signal. The second filter receives the first output signal during a time period adjusted based on a variation of a time constant of the first filter, and generates a second output signal by filtering the first output signal received during the time period. Therefore, a variation of a time constant is compensated by using post integration time control.

Abstract: Aspects of the disclosure can provide a second order low pass filter. The second order low pass filter can work in current domain, and have high linearity for in-band signals and out-of-band signals. The second order low pass filter can include a MOS transistor having a gate terminal, a current input terminal and a current output terminal, a first capacitor coupled between the current input terminal and a ground connection and a second capacitor coupled between the gate terminal and the current input terminal.

Abstract: A sampling filter of such circuitry as not requiring a high frequency REF signal even if the number of decimation is decreased. In the sampling filter, the rotate capacitor in each switched capacitor circuit including Cr (7a-7d) arranged in four parallel arrays operates in four phases of integration, discharge, reset and feedback different from each other at the same timing. Consequently, a control signal for driving the switched capacitor circuit is used commonly. As a result, the circuit scale of a DCU (104) is reduced and the frequency of the REF signal can be lowered to the frequency of an LO signal even in operation without decimation.

Abstract: A 4-phase filter includes four filter units including resistors and capacitors which inputs input signals, and provides the input signal via a switch buffer to a secondary capacitor provided in parallel to a primary capacitance of each filter unit, thus enabling a shift of an operational frequency band according to whether or not the switch buffer is in an output-high-impedance state.

Abstract: The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively.

Abstract: A driver integrated circuit for driving at least one high voltage half bridge stage. The driver including a filter circuit for filtering a signal provided to the half bridge stage, a minimum pulse width of the signal being near a constant time of the filter, wherein the filter circuit prevents distortions introduced when the signal is at its minimum pulse width from being passed to the half bridge stage.