Strip Type Patents (Class 333/246)
  • Patent number: 6888061
    Abstract: The present invention relates to optimization of communication equipment with respect to size and undesired signal interference. To this aim a ceramic feedthrough interconnection assembly is proposed in order to transport an electrical information signal to and from a communication capsule. In addition to at least one signal lead (103a, 103b) for communicating an electrical information signal, the assembly contains at least one auxiliary lead and a shield (103c, 103d, 104, 104a, 104b, 104f) that electrically shields the at least one signal lead (103a, 103b) from the at least one auxiliary lead. The shield (103c, 103d, 104, 104a, 104b, 104f) has such dimensions (d1, d2) and is positioned at such distance (d3, d4, d12) from the at least one signal lead (103a, 103b) that the electrical information signal experiences a well-defined and substantially constant impedance in the assembly. This in turn, minimizes the risk of undesired signal reflections. At the same time the assembly allows a high lead density, i.e.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: May 3, 2005
    Assignee: Optillion AB
    Inventors: Lars Lindberg, Lars-Gote Svenson, Edgard Goodbar
  • Patent number: 6882253
    Abstract: The invention provides a highly-reliable, low-loss non-radiative dielectric waveguide. According to one aspect of the invention, a non-radiative dielectric waveguide comprises parallel planar conductors arranged at an interval of half or below of a high-frequency signal wavelength, and a dielectric strip interposed between the parallel planar conductors. The dielectric strip has a 0.01 to 0.3 mm-wide chamfer formed at its edge portion in a high-frequency signal transmission direction. According to another aspect of the invention, a non-radiative dielectric waveguide comprises parallel planar conductors arranged at an interval of half or below of a high-frequency signal wavelength, and a dielectric strip interposed between the parallel planar conductors. The dielectric strip is made of a ceramics having an open pore ratio of 5% or less.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: April 19, 2005
    Assignee: Kyocera Corporation
    Inventors: Takeshi Okamura, Nobuki Hiramatsu
  • Patent number: 6876268
    Abstract: A coupling element for an HF strip line structure on an HF substrate, implemented in thin-layer technology as a finger coupler structure on a silicon support is described. The bonding to the strip line tracks of the HF strip line structure is effected via metallizations, in particular in the form of spacers.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: April 5, 2005
    Assignee: Robert Bosch GmbH
    Inventors: Thomas Walter, Markus Ulm, Stefan Keith, Dirk Steinbuch, Mathias Reimann
  • Patent number: 6876279
    Abstract: A tunable dielectric structure includes a first layer of dielectric material, a second layer of dielectric material positioned adjacent to the first layer of dielectric material, with the second layer of dielectric material having a dielectric constant that is less than the dielectric constant of the first layer of dielectric material, and electrodes for applying a controllable voltage across the first dielectric material, thereby controlling a dielectric constant of the first dielectric material, wherein at least one of the electrodes is positioned between the first and second layers of dielectric material. The dielectric materials can be formed in various shapes and assembled in various orientations with respect to each other. The tunable dielectric structure is used in various devices including coaxial cables, cavity antennas, microstrip lines, coplanar lines, and waveguides.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: April 5, 2005
    Assignee: Paratek Microwave, Inc.
    Inventors: Louise Sengupta, Steven C. Stowell, Yongfei Zhu, Somnath Sengupta, Luna H. Chiu, Xubai Zhang
  • Patent number: 6876062
    Abstract: An apparatus and method for protecting die corners in a semiconductor integrated circuit. At least one irregular seal ring having two sides can be configured, wherein the irregular seal ring is located at a corner of a die utilized in fabricating a semiconductor integrated circuit. A dummy configuration for stress relief can then be arranged, wherein the dummy configuration is located at the two sides of the at least one irregular seal ring, thereby protecting the corner of the die against thermal stress and the semiconductor integrated circuit against moisture and metallic impurities. The irregular seal ring can be configured to generally comprise a non-rectangular seal ring. The irregular seal preferably comprises an octangular seal ring.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: April 5, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tze-Liang Lee, Shih-Chung Chen, Ming-Soah Liang, Chen-Hua Yu
  • Patent number: 6873230
    Abstract: The problem is that, since a coplanar ground conductor located immediately below a line conductor is absent near a through conductor for providing connection between the one ends of the line conductors each having the coplanar ground conductor, characteristic impedance mismatch occurs and this leads to poor transmission characteristics. The invention provides a high-frequency wiring board in which, given that the interval between the first/second line conductor and part of the first/second coplanar ground conductor located around each side of the line conductor is S, and that the distance between the first/second line conductor and its corresponding second/first coplanar ground conductor facing each other via the dielectric substrate is H, then the following relationship holds: S<H/2.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: March 29, 2005
    Assignee: Kyocera Corporation
    Inventor: Takayuki Shirasaki
  • Patent number: 6873229
    Abstract: An RF device includes a substrate (502) formed of a low temperature co-fired ceramic (LTCC). A cavity structure, such as a conduit (508) can be provided within the substrate with at least one fluid dielectric contained within the cavity structure. The RF device can also include a piezoelectric structure (504) for concurrently applying agitation force to the fluid dielectric in at least two opposing directions. The opposing directions can include substantially all directions normal to an interior surface defining a fluid conduit over a selected length of the fluid conduit.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: March 29, 2005
    Assignee: Harris Corporation
    Inventor: Randy T. Pike
  • Patent number: 6867661
    Abstract: A millimeter wave system includes a plurality of millimeter wave modules, each of which comprises a substrate; a microstrip conductor formed on one surface side of the substrate; a ground plate formed on the other surface side of the substrate; and conductive pads which are disposed on both sides of a strip conductor portion which extends from said microstrip conductor via a tapered portion, and which are connected to the ground potential of said ground plate through a via hole, wherein the strip conductors of this plurality of millimeter wave modules are connected to each other using conductive ribbon. Moreover, when a plurality of millimeter wave modules is connected to form a millimeter wave system, the effect produced by the interaction between the unnecessary conductive pads connected to the ground potential and the strip conductor can be reduced.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Debasis Dawn, Yoji Ohashi, Toshihiro Shimura
  • Patent number: 6867669
    Abstract: Method and apparatus for interfacing a circuit, such as a microcircuit, with an IC. The circuit is formed on a thick film dielectric structure supported by a substrate having a cut out to receive the IC. A ground plane is formed on the substrate. The thick film dielectric structure abuts the cut out with an area having at least two projections forming at least one recess, the edge of the recess having a conductive layer in electrical communication with the ground plane. A conductive pad on top of the dielectric structure is in electrical communication with the conductive layer in the recess. A ground connection on the IC is connected to the conductive pad thereby grounding the IC.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: March 15, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Lewis R. Dov, John F. Casey
  • Patent number: 6867668
    Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure, a microstrip structure, a stripline structure, or the like. The cable can be coupled to destination components using a variety of connection techniques, e.g., direct bonding to a circuit substrate, direct soldering to a flip chip, mechanical attachment to a component, or integration with a circuit substrate. The cable can also be terminated with any number of known or standardized connector packages, e.g., SMA, GPPO, or V connectors.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: March 15, 2005
    Assignee: Applied Micro Circuits Corporation
    Inventors: Carlos Chávez Dagostino, Ronald Edward Perez
  • Patent number: 6856210
    Abstract: A high-frequency multilayer circuit substrate having a plurality of circuit layers includes a via hole for connection between the circuit layers, a metal pad, an impedance matching transmission line, rectangular stubs and a signal transmission line. A via hole connecting portion is constructed of the via hole, the rectangular stubs and the impedance matching transmission line. A characteristic impedance of the via hole connecting portion is matched to a characteristic impedance of the signal transmission line by adjusting widths and lengths of the impedance matching transmission line and the rectangular stubs. Thereby, the reflection of the signal wave in the via hole connecting portion is reduced to decrease a transmission loss.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: February 15, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yu Zhu, Eiji Suematsu
  • Publication number: 20040246064
    Abstract: A multilayer circuit board for high-frequency signals includes: a multilayer wiring board unit including, at least one wiring layer, one or more ground layers configured by a conductive material, insulating layers between the layers, and a first external electrode electrically connected to a transmission line on an episurface; and a connector unit including a second external electrode electrically connected to the first external electrode, and a fitting portion for holding on the multilayer wiring board unit an external circuit board or an external connector. The distance d between the first external electrode (7) and the ground layer perpendicularly below and most closely disposed to the first external electrode is determined within the range dl≦d≦du with respect to the values dl and du defined based on tolerance of the impedance &Dgr;Z.
    Type: Application
    Filed: May 21, 2004
    Publication date: December 9, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Junichi Abe, Yuichirou Murata
  • Publication number: 20040233024
    Abstract: A microwave frequency device includes: a first substrate having a dielectric layer and a conductive film disposed on opposing first and second sides of the dielectric layer, the conductive film on the first side of the dielectric layer of the first substrate including at least one signal line; and a second substrate having a dielectric layer, conductive film disposed on at least one of first and second opposing sides of the dielectric layer, and at least one cut-out where the dielectric layer and conductive film have been removed, wherein the first and second substrates are bonded together to form a bonded assembly such that (i) a portion of the signal line of the first substrate is sandwiched between the dielectric layers of the first and second substrates, and (ii) the at least one cut-out exposes a portion of the signal line, thereby forming a microstrip portion. A method of forming same is also disclosed.
    Type: Application
    Filed: May 22, 2003
    Publication date: November 25, 2004
    Inventors: Antonio Almeida, Shankar Joshi, Meta Rohde, Mahadevan Sridharan
  • Publication number: 20040233023
    Abstract: An RF device includes a substrate (502) formed of a low temperature co-fired ceramic (LTCC). A cavity structure, such as a conduit (508) can be provided within the substrate with at least one fluid dielectric contained within the cavity structure. The RF device can also include a piezoelectric structure (504) for concurrently applying agitation force to the fluid dielectric in at least two opposing directions. The opposing directions can include substantially all directions normal to an interior surface defining a fluid conduit over a selected length of the fluid conduit.
    Type: Application
    Filed: May 19, 2003
    Publication date: November 25, 2004
    Inventor: Randy T. Pike
  • Patent number: 6822532
    Abstract: A suspended stripline device and method for manufacturing thereof. The device includes first and second conductive traces disposed on a dielectric substrate, each of the first and second conductive traces having a first edge and a second edge, and a housing at least partially surrounding the dielectric substrate, wherein the second edge of each of the first and second conductive traces includes at least one outwardly extending protrusion, the size and orientation of which may be selected so as to compensate for unequal even and odd mode propagation velocities through the suspended-stripline device. The device may be packaged by folding solder-coated tabs, provided on the housing, around the dielectric substrate and heating the device such that the solder melts causing the housing to be secured to the substrate.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: November 23, 2004
    Assignee: Sage Laboratories, Inc.
    Inventors: John R. Kane, Richard J. Garabedian
  • Patent number: 6816041
    Abstract: A microwave monolithic integrated circuit (MMIC) assembly and related method are disclosed. A dielectric substrate has a surface on which radio frequency circuits and microstrip lines are formed. At least one MMIC chip opening is dimensioned for receiving therethrough a MMIC chip. A metallic carrier is mismatched as to coefficient of thermal expansion to the dielectric substrate and includes a component surface adhesively secured to the dielectric substrate on the surface opposing the radio frequency circuits and microstrip lines. At least one raised pedestal is on the component surface that is positioned at the MMIC chip opening. A MMIC chip is secured on the pedestal and extends through the MMIC chip opening for connection to the radio frequency circuits and microstrip lines. Stress relief portions are formed in the metallic carrier that segment the carrier into subcarriers and provide stress relief during expansion and contraction created by temperature changes.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: November 9, 2004
    Assignee: Xytrans, Inc.
    Inventors: Danny F. Ammar, Gavin Clark
  • Publication number: 20040217830
    Abstract: An RF multilayer circuit board having: a first conductive device in a first plane for providing a first RF signal line; a first reference potential plane in a second plane for providing a reference potential of the first RF signal line; at least one second reference potential plane in a third plane for providing a reference potential of an at least one second RF signal line; at least one second conductive device in a fourth plane for providing a second RF signal line; a plated through hole device for electrically connecting the first and second conductive devices, the first and second reference potential planes each having a recess between them in the area of the plated through hole device; and at least one additional conductive device in the area of the plated through hole device at least between the first and second reference potential planes and bonding them in order to provide a waveguiding channel around the plated through hole device.
    Type: Application
    Filed: February 10, 2004
    Publication date: November 4, 2004
    Inventors: Thomas Hansen, Martin Schneider, Oliver Brueggemann
  • Patent number: 6812805
    Abstract: In one aspect, the invention relates to a waveguide structure for differential transmission lines. The waveguide structure includes a first ground structure, a first signal line, a second ground structure, a second signal line, a third ground structure. The first signal line is typically positioned adjacent and substantially parallel to the first ground structure. The second ground structure has a first separation distance from the first ground structure and is typically positioned adjacent and substantially parallel to the first signal line. The first signal line is typically positioned between both the first and second ground structures. The second signal line typically a has a second separation distance from the first signal line and is positioned adjacent and substantially parallel to the second ground structure. The second ground structure is typically positioned between both the first and second signal lines.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: November 2, 2004
    Assignee: Multiplex, Inc.
    Inventor: Liang D. Tzeng
  • Patent number: 6806416
    Abstract: Method for preventing degradation of a fluid dielectric (106) in an RF device (100). The method can include the steps forming a substrate (102) of the RF device (100) from a low temperature co-fired ceramic (LTCC), positioning within a cavity structure (104) of the substrate (102) at least one fluid dielectric (106), and agitating the fluid dielectric (106) with a piezoelectric device (112). According to one aspect of the invention, the piezoelectric device (112) can be formed from lead zirconate titanate.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: October 19, 2004
    Assignee: Harris Corporation
    Inventor: Randy T. Pike
  • Patent number: 6803836
    Abstract: A multilayer ceramic structure (30) includes a first ceramic layer (32), a second ceramic layer (34) adjacent to the first ceramic layer, and a transmission line (38) formed between the first and second ceramic layers. The transmission line includes first and second portions (44, 46) having a first width, third and fourth portions (47, 48) formed between the first and second portions and having a second width that is narrower than the first width, and a fifth portion (49) formed between the third and fourth portions. A probe (40), comprising a conductively filled via, is attached at one end to the fifth portion, the probe passing through the second ceramic layer for providing a test point (42). The structure compensates for return loss induced by the probe.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: October 12, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John C. Estes, Rudolfo Lucero, Anthony M. Pavio
  • Publication number: 20040196122
    Abstract: A concentric ‘conductor within a via’ RF interconnect architecture, has an inner via through which at least one RF signal conductor passes. The inner conductive via is coaxially formed within and stably coaxially aligned within an outer conductive via, which serves as a coaxial ground plane that completely surrounds the inner conductive via. The outer conductive via passes through dielectric layers of microstrip or stripline structures on opposite sides of a multi printed circuit laminate.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 7, 2004
    Applicant: HARRIS CORPORATION
    Inventors: Charles Robert Fisher, Anders P. Pedersen, Walter M. Whybrew
  • Patent number: 6801108
    Abstract: The present invention provides a millimeter-wave passive FET switch by using impedance transformation network to transfer the effective capacitance seen from the drain to source of an FET at off-state to low impedance, while transfer low impedance seen at on-state to high impedance. Since both on-state and off-state are transferred to high impedance, and low impedance respectively, a high-performance switch can be achieved. Since the size of the transformation network is small, the performance of the switch can be promoted with low cost.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: October 5, 2004
    Assignee: Taiwan University
    Inventors: Huei Wang, Yu-Jiu Wang, Kun-You Lin
  • Patent number: 6798317
    Abstract: A vertically-stacked filter employing a ground-aperture broadside-coupled resonator device that can advantageously be employed within various systems (e.g., communication systems). The filter comprises a plurality of metal layers and a plurality of dielectric layers arranged in a vertically-stacked topology. The plurality of metal layers form a resonator device having two or more resonators. At least one pair of resonators have opposing broadside surfaces that are coupled. One mechanism for broadside coupling the pair of resonators is a metal layer between the pair of resonators wherein the metal layer has an aperture between the broadside surfaces.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: September 28, 2004
    Assignee: Motorola, Inc.
    Inventors: Seth David Silk, Stephen Kuffner
  • Patent number: 6798319
    Abstract: A high-frequency filter for use in a superhigh frequency band such as of microwaves and millimeter waves has a substrate, a metal conductor disposed on a first main surface of the substrate, a resonator comprising a transmission line of a coplanar structure which is made of the metal conductor, and input and output lines disposed on a second main surface of the substrate transversely across the resonator and electromagnetically coupled to the resonator. The resonator may be a coplanar line resonator (coplanar waveguide resonator) or a slot line resonator. The high-frequency filter has a steep attenuating gradient in filter characteristics. The high-frequency filter may be combined with variable-reactance devices such as variable-capacitance diodes for electronically controlling the filter characteristics.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: September 28, 2004
    Assignees: Nihon Dempa Kogyo Co., Ltd.
    Inventors: Masayoshi Aikawa, Eisuke Nishiyama, Yoshifumi Kawamura, Fumio Asamura, Takeo Oita
  • Patent number: 6778043
    Abstract: A method and apparatus for adding inductance is disclosed. Inductance may be added to a transmission line coupled to a printed circuit board to increase the inductance associated with a transmission line by utilizing ferromagnetic materials.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: August 17, 2004
    Assignee: Maxxan Systems, Inc.
    Inventors: Donald Joseph Stoddard, Matthew J. Schumacher
  • Publication number: 20040155734
    Abstract: The present invention provides a high frequency module having a base substrate unit (2) which has its uppermost layer planarized to form a buildup-forming surface (16), a high frequency circuit unit (3) having multiple wiring layers which are formed on the base substrate unit (2), each of which layers has a wiring pattern and film elements formed on a dielectric insulating layer thereof, whose uppermost wiring layer (17) has plural lands (22) and ground patterns (20) formed thereon together with the wiring pattern and inductor elements (19), and a semiconductor chip (4) mounted on the wiring layer (17) of the high frequency circuit unit (3). Transmission lines (24) to connect the inductor elements (19) and lands (22) which are formed on the wiring layer (17) are directed within hollowed pattern regions (20c) formed at the ground pattern (20) to constitute coplanar type transmission lines.
    Type: Application
    Filed: October 27, 2003
    Publication date: August 12, 2004
    Inventors: Takahiko Kosemura, Akihiko Okubora
  • Patent number: 6771147
    Abstract: A high frequency filter design for the GHz frequency range is provided. The high frequency filter comprises at least a microstrip design that incorporates both transverse and lateral couplings between the filters resonators. The high frequency filter further incorporates an opened or fully enclosed enclosure over the strip line or microstrip circuitry and may be manufactured on a relatively thick dielectric substrate having a thickness that is greater than about a twentieth of the filter's band-pass wavelength in the dielectric substrate. The high frequency filter design provides a small, easily reproducible filter design better than prior art microstrip filters.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: August 3, 2004
    Assignee: Remec, Inc.
    Inventor: Rajesh Mongia
  • Patent number: 6768400
    Abstract: A microstrip line includes a ground conductor layer, a dielectric layer formed on the ground conductor layer, and a linear conductor layer formed on the dielectric layer to have a linear configuration. The linear conductor layer has a wider portion in the upper part of a cross section thereof taken in a direction perpendicular to the direction in which the linear conductor layer extends and a narrower portion in the lower part of the cross section. The narrower portion is smaller in width than the wider portion.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: July 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Mitsuru Tanabe
  • Patent number: 6759921
    Abstract: The present invention provides a characteristic impedance equalizer and method of manufacture thereof for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedancs equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Yogendra Ranade
  • Patent number: 6756860
    Abstract: Disclosed is a dual band coupler, in which a dielectric layer having a coupling signal line is positioned between dielectric layers having a first main signal line and a second main signal line. Coupling coefficients of first and second signal lines can be independently controlled by laminating different numbers of dielectric layers between the coupling signal line and main signal lines, respectively. A shielding pattern for excluding mutual electromagnetic interference between the first and second main signal lines is formed on the dielectric layer having the coupling signal line to improve an isolation, and a small sized-dual band coupler can be provided because the dielectric layer having a ground pattern can be omitted.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: June 29, 2004
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Ji Hwan Shin
  • Publication number: 20040119565
    Abstract: The problem is that, since a coplanar ground conductor located immediately below a line conductor is absent near a through conductor for providing connection between the one ends of the line conductors each having the coplanar ground conductor, characteristic impedance mismatch occurs and this leads to poor transmission characteristics. The invention provides a high-frequency wiring board in which, given that the interval between the first/second line conductor and part of the first/second coplanar ground conductor located around each side of the line conductor is S, and that the distance between the first/second line conductor and its corresponding second/first coplanar ground conductor facing each other via the dielectric substrate is H, then the following relationship holds: S<H/2.
    Type: Application
    Filed: July 23, 2003
    Publication date: June 24, 2004
    Applicant: KYOCERA CORPORATION
    Inventor: Takayuki Shirasaki
  • Patent number: 6753744
    Abstract: A circuit (100) for processing radio frequency signals includes a substrate (50) where the circuit can be placed. The substrate can be a meta-material and can incorporate at least one dielectric layer (20, 30, or 40). The circuit such as a three port circuit and at least one ground can be coupled to the substrate. The dielectric layer can include a first region (40) with a first set of substrate properties and a second region (20) with a second set of substrate properties. Substrate properties can include permittivity and permeability. A portion (32 or 46) of the three port circuit can be selectively coupled to the second region. The permittivity and/or permeability of the second region can be higher than the permittivity and/or permeability of the first region. The increased permittivities and/or permeabilities can reduce a size of the three port circuit and effect a change in a variety of electrical characteristics associated with the three port circuit.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 22, 2004
    Assignee: Harris Corporation
    Inventors: William D. Killen, Randy T. Pike
  • Patent number: 6753746
    Abstract: The present invention relates a printed circuit board having jumper lines, and a method for making the printed circuit board. An isolation layer made of a dielectric material is coated on the line layer of the printed circuit board, and multiple pads are formed in the isolation layer, thereby exposing part of the line layer without covered by the isolation layer. A high conductive material is coated on the isolation layer to connect the multiple pads, thereby forming a planar jumper layer that is connected to the line layer through the circular pads. Thus, the planar jumper layer may be made simultaneously during fabrication of the printed circuit board, without having to perform the wire-bonding work.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: June 22, 2004
    Assignee: Compeq Manufacturing Co., Ltd.
    Inventors: Wen-Yen Lin, Wen-Bo Ho
  • Patent number: 6750740
    Abstract: A printed circuit for processing radio frequency signals includes a substrate including substrate regions upon which the printed circuit can be placed. The circuit is an interdigital filter including a plurality of resonator elements. The plurality of resonator line elements are at least partially coupled to respective substrate regions that have substrate characteristics that are each independently customizable. The circuit further comprises at least one ground or ground plane (50) coupled to the substrate.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: June 15, 2004
    Assignee: Harris Corporation
    Inventors: William D. Killen, Randy T. Pike
  • Publication number: 20040108922
    Abstract: A microwave monolithic integrated circuit (MMIC) assembly and related method are disclosed. A dielectric substrate has a surface on which radio frequency circuits and microstrip lines are formed. At least one MMIC chip opening is dimensioned for receiving therethrough a MMIC chip. A metallic carrier is mismatched as to coefficient of thermal expansion to the dielectric substrate and includes a component surface adhesively secured to the dielectric substrate on the surface opposing the radio frequency circuits and microstrip lines. At least one raised pedestal is on the component surface that is positioned at the MMIC chip opening. A MMIC chip is secured on the pedestal and extends through the MMIC chip opening for connection to the radio frequency circuits and microstrip lines. Stress relief portions are formed in the metallic carrier that segment the carrier into subcarriers and provide stress relief during expansion and contraction created by temperature changes.
    Type: Application
    Filed: November 19, 2003
    Publication date: June 10, 2004
    Applicant: XYTRANS, INC.
    Inventors: Danny F. Ammar, Gavin Clark
  • Patent number: 6741142
    Abstract: A high-frequency circuit element including a substrate, a high-frequency circuit formed on the substrate, a metal box electromagnetically shielding the high-frequency circuit by enclosing the substrate and an input/output terminal placed on the metal box and inputting/outputting a high-frequency signal to/from the high-frequency circuit. Adding at least one plate for interrupting unwanted higher-order mode cutting off the propagation path of the high frequency waves in the space inside the metal box by substantially dividing the space inside the metal box makes it possible to cut off the propagation path where the high frequency waves propagates in the space inside the box and to suppress excitation and propagation of the unwanted higher-order mode that adversely affects the frequency characteristic of the high frequency circuit element.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: May 25, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunao Okazaki, Akira Enokihara, Kentaro Setsune
  • Patent number: 6741148
    Abstract: A printed circuit for processing radio frequency signals includes a substrate including substrate regions upon which the printed circuit can be placed. The circuit is a coupled line filter including a plurality of resonator elements. The plurality of resonator line elements are at least partially coupled to respective substrate regions that have substrate characteristics that are each independently customizable. The circuit further comprises at least one ground or ground plane (50) coupled to the substrate.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 25, 2004
    Assignee: Harris Corporation
    Inventors: William D. Killen, Randy T. Pike
  • Publication number: 20040095214
    Abstract: The present invention consists of an electrical communications device including a three-dimensional substrate and a plurality of electrical devices attached thereto. The substrate is preferably a dielectric. The electrical device is preferably of the sort needed to conduct high frequency communications, such as a microwave antenna and photonic receivers and transmitters. The electrical devices are attached to the substrate at the connection points described by the intersection of a series vias and one of the substrate surfaces. The electrical devices are attached to the substrate in numerous ways, including solder, flipped chip ball bonds, wire bonds, or a gold stud assembly. In particular, the gold stud assembly is utilized to attach the antenna to the substrate, thereby providing a predetermined air gap therebetween.
    Type: Application
    Filed: November 18, 2002
    Publication date: May 20, 2004
    Inventors: C. Allen Marlow, Jay DeAvis Baker, Lawrence Leroy Kneisel, Rosa Lynda Nuno, William David Hopfe
  • Patent number: 6737931
    Abstract: Device interconnects and methods of making the same are described. In one aspect, a device interconnect system includes a bonding pad portion and a transmission line portion. The bonding pad portion is disposed on a device substrate and is constructed and arranged for electrical connection to a bond wire. The transmission line portion is disposed on the device substrate and is constructed and arranged to electrically couple the bonding pad portion to a device formed on the device substrate. The transmission line portion has a width dimension that is substantially parallel to the device substrate and a height dimension that is substantially perpendicular to the device substrate. The width dimension and the height dimension of the transmission line portion both vary from the bonding pad portion to the device.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: May 18, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Alfonso Benjamin Amparan, David Lee Gines
  • Patent number: 6737883
    Abstract: An apparatus includes a substrate, a ground plane on the substrate, the ground plane having a slot, transmission lines lying over the slot, and data processing agents each connected to one of the transmission lines. A method includes inducing a transient return current on a reference plane in response to a driving agent sourcing a current being representative of binary data onto a first transmission line, the current being representative of binary data, propagating energy of the transient return current to a slot in the reference plane, inducing a transient voltage pulse onto a second transmission line connected to a receiving agent when the propagating energy encounters the second transmission line and generating a binary digital signal in the receiving agent from the transient voltage pulse received on the second transmission line.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventor: Stephen H. Hall
  • Patent number: 6734750
    Abstract: A surface mount crossover component comprising first and second conductor lines electrically isolated from one another by an interposed dielectric layer and capacitively isolated from one another by an interposed ground plane layer. Current flowing through the crossover component via one of the conductor lines encounters no substantial interference from current flowing through the other one of the conductor lines.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: May 11, 2004
    Assignee: Anaren Microwave, Inc.
    Inventor: Hans Peter Ostergaard
  • Patent number: 6731189
    Abstract: A multi-layer stripline assembly interconnection includes a first stripline sub-assembly having a first surface and a first plurality of vias disposed in the first surface adapted to receive a plurality of solid metal balls. The interconnection further includes a second stripline sub-assembly having a second plurality of vias disposed in the first surface of the second sub-assembly adapted to be aligned with the first plurality of vias. Reflowed solder is wetted to the second plurality of vias and to the corresponding plurality of solid metal balls.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 4, 2004
    Assignee: Raytheon Company
    Inventors: Angelo Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica
  • Publication number: 20040080386
    Abstract: A connection structure is provided, which can perform an electrical connection between high-frequency circuit substrates in a manner of high workability and productivity. A connection structure comprises: a high-frequency transmission line lead frame connecting a first high-frequency transmission line formed on a first high-frequency circuit substrate to a second high-frequency transmission line formed on a second high-frequency circuit substrate; a plurality of GND electrode lead frames disposed in parallel to the high-frequency transmission line lead frame on both sides thereof, and providing a connection between a first GND electrode of the first high-frequency circuit substrate and a second GND electrode of the second high-frequency circuit substrate; and a reinforcing substrate integrally securing the high-frequency transmission line lead frame and a plurality of GND electrode lead frames.
    Type: Application
    Filed: April 8, 2003
    Publication date: April 29, 2004
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA.
    Inventors: Yoichi Kitamura, Yukihiro Tahara, Akira Tsumura
  • Patent number: 6728113
    Abstract: Apparatus is described for capacitively signalling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signalling, and reduces or eliminates the requirements for exotic metallurgy.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: April 27, 2004
    Assignee: Polychip, Inc.
    Inventors: Thomas F. Knight, David B. Salzman
  • Patent number: 6724283
    Abstract: The invention relates to a microwaveguide that is integrated in the dielectric layer of a conductor carrier, e.g. a printed circuit board. The waveguide enables different types of active and/or passive functions intended to influence the signals sent through the waveguide to be integrated at appropriate positions in the waveguide.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: April 20, 2004
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Leif Bergstedt, Spartak Gevorgian
  • Patent number: 6717494
    Abstract: Occurrence of EMI is reduced without a sharp increase of the manufacturing cost by suppressing a common mode current stably. There is provided a disclosed printed-circuit board being adapted such that a width of an outer edge section of a T-shaped pattern is widened so as to surround a recessed section with a frame-shaped additional electric conductor by electrically connecting the frame-shaped additional electric conductor with the T-shaped pattern making up a ground pattern so as to close the recessed section.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: April 6, 2004
    Assignee: NEC Toppan Circuit Solutions, Inc.
    Inventors: Hideo Kikuchi, Toshiyuki Kaneko, Hideki Kikuchi, Kazuhiro Kinoshita, Kiyohiko Kaiya, Yutaka Akimoto
  • Publication number: 20040061576
    Abstract: A multilayer ceramic structure (30) includes a first ceramic layer (32), a second ceramic layer (34) adjacent to the first ceramic layer, and a transmission line (38) formed between the first and second ceramic layers. The transmission line includes first and second portions (44, 46) having a first width, third and fourth portions (47, 48) formed between the first and second portions and having a second width that is narrower than the first width, and a fifth portion (49) formed between the third and fourth portions. A probe (40), comprising a conductively filled via, is attached at one end to the fifth portion, the probe passing through the second ceramic layer for providing a test point (42). The structure compensates for return loss induced by the probe.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: John C. Estes, Rudolfo Lucero, Anthony M. Pavio
  • Patent number: 6714104
    Abstract: The invention relates to a transmission cable realized by multilayer technique, where the signal cable (20) is set at a desired distance from the wall of the cavity constructed for said transmission cable by means of a separate support element (25). The ground cable (21) included in the structure is placed on the cable cavity wall opposite to the signal cable. By using the transmission cable according to the invention, there is achieved a low attenuation per unit of length at RF frequencies.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: March 30, 2004
    Assignee: Nokia Networks Oy
    Inventor: Olli Salmela
  • Patent number: 6714095
    Abstract: A constant “R” network distributed amplifier formed in a multi-layer, low temperature co fired ceramic structure comprises multiple cascaded constant “R” networks for amplifying a signal applied thereto. Each one of the multiple cascaded constant “R” networks is formed in the ceramic structure and includes a plurality of ceramic layers each of which have a top and bottom planar surfaces which, when bonded together form the ceramic structure. A transmission line is formed on the top surfaces of each of the ceramic layers having a beginning end and a distal end and has a generally rectangular shape. The distal end of the transmission line formed on a lower ceramic layer is connected to the beginning end of the transmission line formed on the next adjacent upper ceramic layer by way of vias formed in the ceramic layers through which metal conductive material is formed there through.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: March 30, 2004
    Assignee: Motorola, Inc.
    Inventors: Anthony M. Pavio, Lei Zhao
  • Patent number: 6710255
    Abstract: A first signal path is connected to a first plane via a plated hole. A first metal flood is connected to the plated hole to form a first plate. A second signal path is on a second plane. A second metal flood connected to the second signal path to form a second plate above the first plate.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Jason Ross, Timothy J. Maloney