Abstract: A general-purpose graphics processing unit (GPU) module, a system containing the general-purpose GPU module, and a method for driving the system are provided in accordance with various embodiments of the invention. In an embodiment, a general-purpose GPU module comprises a GPU, a data transfer input/output (I/O) port, a power supply I/O port, a control/SYNC module, and a power supply module. When a new general-purpose GPU module is detected being coupled to the transfer link bus, the graphics processing tasks are allocated to all the coupled general-purpose GPU modules. In accordance with various embodiments of the invention, the costs of designing and using GPUs will be decreased.

Abstract: An information processing apparatus includes a first graphics chip having a first drawing processing capacity and being capable of producing a first image signal; a second graphics chip having a second drawing processing capacity higher than the first drawing processing capacity and being capable of producing a second image signal; an output changeover section capable of selectively outputting one of the first or second image signals; an inputting section configured to input a user operation to select one of the first graphics chip or the second graphics chip; and a control section configured to control the output of the output changeover section in response to the inputted user operation.

Abstract: Exemplary apparatus, method, and system embodiments provide for processing an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; first circuitry configured to convert a plurality of descriptive elements of the action script into a plurality of operational codes; and second circuitry configured to execute the plurality of operational codes using corresponding data stored in the first memory to generate pixel data for the graphical image. Exemplary embodiments may further include third circuitry configured to parse the action script into the plurality of descriptive elements and the corresponding data, and fourth circuitry configured to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Various embodiments of a method and system for modifying and rendering scenes via display lists are described. Various embodiments may include a graphical application for generating a display list including display list nodes each corresponding to a respective scene element. To generate a given display list node, the graphical application may determine a scene graph node of a scene graph, allocate a portion of memory dedicated to the display list node, and store in that portion of memory, at least one of the attributes of the respective scene element determined from the particular scene graph node. The graphical application may modify a particular display list node corresponding to the particular scene element by modifying a respective attribute stored in the portion of memory allocated to the particular display list node, and render an image of a scene that includes the particular scene element modified according to the notification.

Abstract: Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary apparatus comprises: a first memory; and a plurality of processors to separate the action script from other data, to convert a plurality of descriptive elements of the action script into a plurality of hardware-level operational or control codes, and to perform one or more operations corresponding to an operational code of the plurality of operational codes using corresponding data to generate pixel data for the graphical image. In an exemplary embodiment, at least one processor further is to parse the action script into the plurality of descriptive elements and the corresponding data, and to extract data from the action script and to store the extracted data in the first memory as a plurality of control words having the corresponding data in predetermined fields.

Abstract: Exemplary apparatus, method, and system embodiments provide for accelerated hardware processing of an action script for a graphical image for visual display. An exemplary method comprises: converting a plurality of descriptive elements into a plurality of operational codes which at least partially control at least one processor circuit; and using at least one processor circuit, performing one or more operations corresponding to an operational code to generate pixel data for the graphical image. Another exemplary method for processing a data file which has not been fully compiled to a machine code and comprising interpretable descriptions of the graphical image in a non-pixel-bitmap form, comprises: separating the data file from other data; parsing and converting the data file to a plurality of hardware-level operational codes and corresponding data; and performing a plurality of operations in response to at least some hardware-level operational codes to generate pixel data for the graphical image.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: The disclosure describes an adaptive multi-shader within a processor that uses one or more high-precision arithmetic logic units (ALUs) and low-precision ALUs to process data based on the type of the data. Upon receiving a stream of data, the adaptive multi-shader first determines the type of the data. For example, the adaptive multi-shader may determine whether the data is suitable for high-precision processing or low-precision processing. The adaptive multi-shader then processes the data using the high-precision ALUs when the data is suitable for high-precision processing, and processes the data using the high-precision ALUs and the low-precision ALUs when the data is suitable for low-precision processing. The adaptive multi-shader may substantially reduce power consumption and silicon size of the processor by implementing the low-precision ALUs while maintaining the ability to process data using high-precision processing by implementing the high-precision ALUs.

Abstract: A display controller which prevents the duplication of functional parts and processes and which displays dynamic content on a plurality of displays is provided. A terminal used as the controller has a shared dynamic image decoder which decodes the dynamic content. A first frame buffer used by the terminal stores the decoded dynamic content. A buffer transfer unit sends the dynamic content stored in the first frame buffer to a second frame buffer used by an external monitor. A terminal display displays the dynamic content stored in the first frame buffer on a display of the terminal. An external monitor interface displays the dynamic content stored in the second frame buffer on an external monitor.

Abstract: The disclosed embodiments provide a system that configures a computer system to switch between graphics-processing units (GPUs). In one embodiment, the system drives a display using a first graphics-processing unit (GPU) in the computer system. Next, the system detects one or more events associated with one or more dependencies on a second GPU in the computer system. Finally, in response to the event, the system prepares to switch from the first GPU to the second GPU as a signal source for driving the display.

Abstract: To provide an image display device to simplify software for rewriting data, and shorten rewrite time, a vehicle meter 1 includes the image display device including: a display device 10 displaying the image data; a main microprocessor 30 including Flash-ROMa 31 and I/F 32 communicating with external; and GDC microprocessor 40 including Flash-ROMb 41 the image data is stored, controlled by the main microprocessor 30, and controlling the display device 10, whereby the GDC microprocessor 40 includes an I/F 42 for directly rewriting the image data from external.

Abstract: Embodiments of an apparatus for having overlapping displays and methods for operating such apparatus can provide enhanced display and operational capabilities. The overlapping displays may include multiple overlapping transparent displays. Embodiments of additional apparatus, systems, and methods are disclosed.

Abstract: Aspects of the present invention are related to systems and methods for rendering graphical objects in a printing system. According to one aspect of the present invention a graphic list may be partitioned, and the graphic-list partitions may be rendered “out-of-order” or concurrently.

Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.

Abstract: The fragment processing pipeline 10 of a graphics processing core 2 has an associated occlusion query cache 19 that is used to maintain a set of local occlusion counters 21. The occlusion query cache 19 is maintained in a local memory 3 of the graphics processing system and can communicate via an interconnect 7 with a set of master occlusion counters 22 in a main memory 5 for the graphics processing system. When an occlusion query starts, a corresponding occlusion counter 22 is initialised in the main memory 5. A corresponding local occlusion counter 21 is also provided in the occlusion query cache 19 in the local memory 3 of the graphics processor, and is used to count the results of the occlusion query. The local occlusion counter value is written back to the occlusion counter 22 for the query in the main memory 5 at the appropriate time for further processing.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A rendering device includes a temporary memory, plural rendering processors, and a rendering controller. The temporary memory stores one or more rendering instructions and rendered results therefor in association with each other. The plural rendering processors each perform rendering processing in accordance with a rendering instruction, store the one or more rendering instructions and rendered results in association with each other in the temporary memory, when one or more similar rendering instructions exist for pages for which rendering processing was consecutively performed, and read and use the rendered results, in a case where rendered results associated with one or more rendering instructions are stored in the temporary memory. The rendering controller controls assigning a given rendering instruction to a corresponding one of the rendering processors in accordance with a given page editing instruction and causing the corresponding one of the rendering processors to perform rendering processing.

Abstract: A method is provided for optimizing computer processes executing on a graphics processing unit (GPU) and a central processing unit (CPU). Process data is subdivided into sequentially processed data and parallel processed data. The parallel processed data is subdivided into a plurality of data blocks assigned to a plurality of processing cores of the GPU. The data blocks on the GPU are processed with other data blocks in parallel on the plurality of processing cores. Sequentially processed data is processed on the CPU. Result data processed on the CPU is returned.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract: A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or GPUs concurrently are described. One or more executables are compiled online from a source having an existing executable for a type of physical compute devices different from the one or more physical compute devices. Dependency relations among elements corresponding to scheduled executables are determined to select an executable to be executed by a plurality of threads concurrently in more than one of the physical compute devices. A thread initialized for executing an executable in a GPU of the physical compute devices are initialized for execution in another CPU of the physical compute devices if the GPU is busy with graphics processing threads.

Abstract: A method includes automatically acquiring, through a resource manager module associated with a driver program executing on a node of a cluster computing system, information associated with utilization of a number of Graphics Processing Units (GPUs associated) with the node, and automatically calculating a window of time in which the node is predictably underutilized on a reoccurring and periodic basis. The method also includes automatically switching off, when one or more GPUs is in an idle state during the window of time, power to the one or more GPUs to transition the one or more GPUs into a quiescent state of zero power utilization thereof. Further, the method includes maintaining the one or more GPUs in the quiescent state until a processing requirement of the node necessitates utilization thereof at a rate higher than a predicted utilization rate of the node during the window of time.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: One or more embodiments of the invention set forth techniques to allocate a memory buffer in the system memory of a computer system that is shared among a plurality of graphics processing units (GPUs) in the computer system. The GPUs are able to engage in Direct Memory Access (DMA) with the memory buffer thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such a shared memory buffer.

Abstract: The subject matter of this specification can be embodied in, among other things, a method that includes computer-implemented graphics frame buffer process that establishes on a computing device a graphics frame buffer accessible to be written by an application process and to be read by a graphics server process. The method further comprises generating a token whose value or values control access to the frame buffer by the application process and the graphics server process and reading frames from the frame buffer using the value or values in the token.

Abstract: Synchronized access to a shared surface from multiple rendering contexts is provided. Only one rendering context is allowed to access a shared surface at a given time to read from and write to the surface. Other non-owning rendering contexts are prevented from accessing and rendering to the shared surface while the surface is currently owned by another rendering context. A non-owning rendering context makes an acquire call and waits for the surface to be released. When the currently owning rendering context finishes rendering to the shared surface, it release the surface. The rendering context that made the acquire call then acquires access and renders to the shared surface.

Abstract: A terminal equipped with a central processing unit (CPU) and a graphics processing unit (GPU) performs a method for executing applications in adaptation to the load of the CPU and GPU. The application execution method of the present invention includes checking, when a code of application to be executed is input, workloads of a central processing unit and a graphics processing unit. The method also includes comparing the workloads of the central processing unit and the graphics processing unit with respective workload threshold values, and compiling the code according to comparison result. The method further includes generating a binary for executing the application at one of the central processing unit and the graphics processing unit using the compiled code, and executing the application with the generated binary. The method reduces application execution time by adjusting the workloads of the CPU and GPU according to the total workload, thereby saving power.

Abstract: According to one aspect, a display controller is included in a graphics processing system where the display controller includes a plurality of look up tables in a data path. According to one embodiment, each of the plurality of look up tables is configured to be coupled to a source of surfaces, each of the plurality of look up tables includes circuitry that is physically separate from circuitry included in others of the plurality of look up tables, and the display controller is configured to employ a combination including at least two of the plurality of look up tables to process a first component of a plurality of pixels included in a surface received from the source of surfaces.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: The disclosed embodiments provide a system that drives a display from a computer system. During operation, the system detects an idle state in a first graphics-processing unit (GPU) used to drive the display. During the idle state, the system switches from using the first GPU to using a second GPU to drive the display and places the first GPU into a low-power state, wherein the low-power state reduces a power consumption of the computer system.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: One embodiment of the present invention sets forth a technique for selecting a boot VGA adapter in a multiple VGA adapter system by controlling the system boot process using the VBIOS display detection service and boot flags that are stored in non-volatile platform memory. The SBIOS initiates a first boot that selects the motherboard integrated graphics processing unit (MGPU) as the boot VGA adapter. During this first boot, if the SBIOS determines that there are display devices attached to the MGPU, then the first boot completes normally. Otherwise, the SBIOS aborts the first boot and initiates a second boot that selects a secondary, discrete graphics processing unit GPU (DGPU) as the boot VGA adapter. During this second boot, if the SBIOS determines that there are display devices attached to the DGPU, then the second boot completes normally.

Abstract: A computing system may include a plurality of GPUs, one or more CPUs, and a data store containing data to be analyzed. A user may register a calculation to be performed on the data, and the system may determine a scheme for allocating portions of the calculation and subsets of the data to different GPUs for concurrent execution. The system may also modify a user-provided algorithm to convert portions of the algorithm that are path-dependent into atomic path-independent operations that may be performed by GPU threads asynchronously. The system may also determine coordination operations sufficient for merging sub-results generated from individual GPU threads' execution of the atomic operations back into a path-dependent computation. The system may be configured to use any number of similar or different GPU devices, and for GPU devices to be added to or removed from the system without requiring programmers to alter their algorithms.

Abstract: A video processing system, method, and computer program product are provided for encrypting communications between a plurality of graphics processors. A first graphics processor is provided. Additionally, a second graphics processor in communication with the first graphics processor is provided for collaboratively processing video data. Furthermore, such communication is encrypted.

Abstract: Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU.

Abstract: A secure display system for a movable object, such as an aircraft, includes: a screen comprising at least two independent matrices formed of pixels, each of the matrices being controlled by an independent graphic channel; a light box comprising at least two independent subassemblies, each backlighting each half-screen; two bypass functions, a bypass function being associated with a graphic channel, a bypass function being linked to an input of one of the matrices; a central module having a function of mixing the data originating from the two independent graphic channels, and a function of separating said data, said separation module being connected to said bypass functions; each graphic channel comprising image-generation means; and two power supply means. The display system may be used in an aeroplane.

Abstract: A system includes first and second processors, first and second graphics processing units (GPUs), one or more peripheral devices, a switch matrix, and processor-readable memory. The switch matrix comprises programmable data paths between the processors, the GPUs, and the peripheral devices. Software encoded in the process-readable memory includes a first operating system (OS) executed by the first processor, a second OS executed by the second processor, a matrix scheduling engine, and a media interface switch (MIS) engine. The first OS boots faster than the second OS. The matrix scheduling engine runs on both OSs and configures the data paths in the switch matrix to couple the processors and the GPUs, and to couple the processors and the peripheral devices. The MIS engine runs on the operating systems, detects presence of the peripheral devices, and configures the data paths in the switch matrix to couple the processors and the peripheral devices.

Abstract: The disclosed embodiments provide a system that configures a computer system to switch between graphics-processing units (GPUs). In one embodiment, the system drives a display using a first graphics-processing unit (GPU) in the computer system. Next, the system detects one or more events associated with one or more dependencies on a second GPU in the computer system. Finally, in response to the event, the system prepares to switch from the first GPU to the second GPU as a signal source for driving the display.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

Abstract: A portable development and execution framework for processing media objects. The framework involves: accepting an instruction to perform a media processing function; accepting a media object to be associated with the media processing function; wrapping the media object with an attribute that specifies a type and format of the media object, and a hardware domain associated with the media object; and causing an execution domain to perform the media processing function on the media object. The instruction to perform the media processing function is expressed in a form that is independent of the hardware domain associated with the media object, and may also be independent of the type and format of the media object. The media object may be an image, and the media processing function may include an image processing function performed on a GPU.

Abstract: According to an aspect of the disclosure, a portable handheld device includes a CPU for processing a script; a multi-core processor for processing an image, and a DRAM for storing image data. The CPU and multi-core processor are integrated on one wafer and share a data cache provided on the same wafer. The DRAM is provided external to the wafer. The portable handheld device further comprises a DRAM interface for receiving and sending data to the DRAM, the DRAM interface being provided on the same wafer and sharing the data cache with the CPU and the multi-core processor.

Abstract: Systems and methods that provide for a common device enumeration point to a class of software objects, which represent hardware and can emit 2D bitmaps, via a presentation interface component. Such presentation interface component can further include a factory component that centralizes enumeration and creation for any components that control or communicate with the frame buffer of the graphics display subsystems. Accordingly, a smooth transition can be supplied between full screen and window models, within desktop composition systems, wherein applications can readily support such transitions.

Abstract: A method and system for controlling multiple displays is provided. The disclosed method is used to control a plurality of graphics processing units (GPUs), wherein every GPU controls one or more displays. The method includes the following steps: providing a graphical interface the same to a graphical program library of an operating system to replace the graphical program library to receive a drawing command from an application program; determining a display set of the GPUs according to a display region of the application program, wherein a frame displayed by the display controlled by each GPU is intersected to the display region; and delivering coordinate-transformed drawing commands to the GPUs in the display set according to the display intersection region, wherein each GPU in the display set only draws the content of the corresponding display intersection region.

Abstract: Techniques, apparatus and systems are disclosed for performing graphics processor unit (GPU)-based fast cone beam computed tomography (CBCT) reconstruction algorithm based on a small number of x-ray projections. In one aspect a graphics processor unit (GPU) implemented method of reconstructing a cone beam computed tomography (CBCT) image includes receiving, at the GPU, image data for CBCT reconstruction. The GPU uses an iterative process to minimize an energy functional component of the received image data. The energy functional component includes a data fidelity term and a data regularization term. The reconstructed CBCT image is generated based on the minimized energy functional component.

Abstract: One embodiment of the present invention sets forth a method for managing a power state of an audio device resident in a graphics processing unit. The method includes the steps of directing audio data originated from a client application via an audio path in an audio driver stack to the audio device, determining whether an active stream of audio data along the audio path is present in response to a notification of an attempt to shut down the graphics processing unit, and requesting a plug and play manager to disable the audio device, if no active stream of audio data is present along the audio path.

Abstract: A method and system for using a graphics processing unit (“GPU”) frame buffer in a multi-GPU computing device as cache memory are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of designating a first GPU subsystem in the multi-GPU computing device as a rendering engine, designating a second GPU subsystem in the multi-GPU computing device as a cache accelerator, and directing an upstream memory access request associated with an address from the first GPU subsystem to a port associated with a first address range, wherein the address falls within the first address range. The first and the second GPU subsystems include a first GPU and a first frame buffer and a second GPU and a second frame buffer, respectively.

Abstract: In an example embodiment, a computing module includes a case, an optical display subsystem coupled to the case, a circuit element assembly, a power cell and an interface connector. The case includes a bottom portion and multiple lateral sidewalls. The case defines an enclosure. The circuit element assembly is positioned within the enclosure and is coupled to the optical display subsystem. The power cell is coupled to the circuit element assembly. The interface connector is defined in the case and includes multiple side openings, multiple bottom openings and multiple connector pads. The side openings are defined in at least one of the lateral sidewalls. The bottom openings are defined in the bottom portion of the case. The connector pads include multiple side pads coupled to the case and in communication with the side openings and multiple bottom pads coupled to the case and in communication with the bottom openings.

Abstract: A tile-based graphics system, and method of operation of such a system, are provided for generating graphics data for a frame comprising a plurality of tiles. Graphics processing circuitry is provided which is arranged to be switched between a first mode of operation and a second mode of operation. In the first mode of operation, the graphics processing circuitry receives the plurality of graphics primitives for the frame, and performs a binning operation to determine, for each of the plurality of tiles, a tile list identifying the graphics primitives which intersect that tile. In the second mode of operation, the graphics processing circuitry receives the tile list for an allocated tile, and performs a rasterization operation to generate the graphics data for the allocated tile dependent on the tile list.

Abstract: Disclosed is a method and apparatus for performing tile-based rendering. A sequence of tiles to be processed may be determined based on a locality among the tiles. A tile dispatch unit selects a subsequent tile to be dispatched, based on the determined sequence.

Abstract: Graphics processing in a computer graphics apparatus having architecturally dissimilar first and second graphics processing units (GPU) is disclosed. Graphics input is produced in a format having an architecture-neutral display list. One or more instructions in the architecture neutral display list are translated into GPU instructions in an architecture specific format for an active GPU of the first and second GPU.