Abstract: Disclosed are an apparatus and a method for processing data, capable of controlling the use of a graphic controller based on data usage in a memory, a variation speed of a memory data value, and/or operating states/conditions of a system.

Abstract: Disclosed herein is an information processing apparatus including: a first drawing processing block configured to generate a video signal by executing predetermined signal processing on entered image data; a second drawing processing block having a higher drawing processing power than the first drawing processing block and being configured to generate a video signal by executing predetermined signal processing on entered image data; a workload measuring block configured to measure at least one of a workload in the first drawing processing block and a workload in the second drawing processing block; a storage block configured to store an application; and a control block configured to select the first drawing processing block or the second drawing processing block to execute the application read from the storage block, on the basis of at least one of the measured workload in the first drawing processing block and the second drawing processing block.

Abstract: Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments include a frame processor module in a graphics processing system that examines the intra-coded and inter-coded frames in an encoded video stream and initiates migration of decoding and rendering functions to a second graphics processor from a first graphics processor based on the location of intra-coded frames in a video stream and the composition of intermediate inter-coded frames.

Abstract: A method for volume rendering a volumetric dataset with multiple graphics processing units (GPUs) coupled to a computer system, comprises building a block hierarchical structure of blocks for the volumetric dataset, the block hierarchy comprising a block sequence; partitioning the block sequence into a plurality of groups; determining a target work load for each GPU; allocating each group of the plurality to a respective GPU in accordance with the target load; rendering respective intermediate images by the respective GPUs; and compositing for a final image by blending the respective intermediate images.

Abstract: One embodiment of the invention sets forth a mechanism for controlling the initialization order of an iGPU and a dGPU in a hybrid graphics processing environment to ensure that the iGPU is recognized by the operating system as the primary GPU. When the device initialization request associated with the dGPU is received, the interface module determines whether the iGPU has already been initialized. If the iGPU has already been initialized, then the interface module transmits the device initialization request to the dGPU driver for dGPU initialization. However, if the iGPU flag indicates that the iGPU has not yet been initialized, then the interface module terminates the device initialization request and transmits an initialization failure notification to the operating system. In such a manner, the dGPU is initialized only after the iGPU has previously been initialized, thereby ensuring that the iGPU is recognized by the operating system as the primary GPU.

Abstract: Configuration information is used to make a determination to bypass fragment shading by a shader unit of a graphics processing unit, the shader unit capable of performing both vertex shading and fragment shader. Based on the determination, the shader unit performs vertex shading and bypasses fragment shading. A processing element other than the shader unit, such as a pixel blender, can be used to perform some fragment shading. Power is managed to “turn off” power to unused components in a case that fragment shading is bypassed. For example, power can be turned off to a number of arithmetic logic units, the shader unit using the reduced number of arithmetic logic unit to perform vertex shading. At least one register bank of the shader unit can be used as a FIFO buffer storing pixel attribute data for use, with texture data, to fragment shading operations by another processing element.

Abstract: A system, method, and computer program product are provided for synchronizing operation of a first graphics processor and a second graphics processor in order to secure communication therebetween. A first graphics processor is provided for processing video data. In addition, a second graphics processor is provided for processing the video data. Furthermore, a data structure is provided for use in synchronizing operation of the first graphics processor and the second graphics processor in order to secure communication therebetween.

Abstract: Systems and methods for providing scalability of multiple graphic processor units (GPU) that work together in a multi-coprocessor fashion to provide parallel graphics rendering methodology for an information handling system. The total number of active GPUs working together to provide parallel graphics rendering methodology for a given information handling system may be increased in a modular manner beyond one or two GPUs, e.g., so as allow as many GPUs as desired to be attached to a given information handling system such as a desktop computer or notebook computer.

Abstract: The invention provides, in some aspects, a system for rendering images, the system having one or more client digital data processors and a server digital data processor in communications coupling with the one or more client digital data processors, the server digital data processor having one or more graphics processing units. The system additionally comprises a render server module executing on the server digital data processor and in communications coupling with the graphics processing units, where the render server module issues a command in response to a request from a first client digital data processor.

Abstract: A method for enabling a user to review a body of information that includes first and second segments from respective first and second information sources includes: storing second segment digital data representing the second segments; receiving an indication that the user has selected for display a particular first segment; identifying one or more of the second segments that are related to the particular first segment by comparing first segment digital data to the second segment digital data; and providing display digital data for display of one or more representations or portions of the identified second segments contemporaneously with display of the particular first segment. The display digital data enables the displayed representations or portions of the second segments to be selected by the user when displayed.

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state.

Abstract: A method and an apparatus are provided for combining multiple independent tile based graphic cores. An incoming geometry stream is split into a plurality of streams and sent to respective tile based graphics processing cores. Each one generates a separate tiled geometry lists. These may be combined into a master tiling unit or, alternatively, markers may be inserted into the tiled geometry lists which are used in the rasterization phase to switch between tiling lists from different geometry processing cores.

Abstract: A system for distributed of plane equation calculations. A work distribution unit is configured to receive a set of vertex data that includes meta data associated with each vertex in a modeled three-dimensional scene, to divide the set of vertex data into a plurality of batches of vertices, and to distribute the plurality of batches of vertices to one or more general processing clusters (GPCs). A processing cluster array includes the one or more (GPCs), where each GPC includes one or more shader-primitive-controller units (SPMs), and each SPM is configured to calculate plane equation coefficients for a subset of the vertices included in a batch of vertices. Advantageously, a distributed configuration of multiple plane equation calculation units decreases the size of the data bus that carries plane equation coefficients and increases overall processing throughput.

Abstract: A method and an apparatus for notifying a display driver to update a display with a graphics frame including multiple graphics data rendered separately by multiple graphics processing units (GPUs) substantially concurrently are described. Graphics commands may be received to dispatch to each GPU for rendering corresponding graphics data. The display driver may be notified when each graphics data has been completely rendered respectively by the corresponding GPU.

Abstract: Graphics processing in a computer graphics apparatus having architecturally dissimilar first and second graphics processing units (GPU) is disclosed. Graphics input is produced in a format having an architecture-neutral display list. One or more instructions in the architecture neutral display list are translated into GPU instructions in an architecture specific format for an active GPU of the first and second GPU.

Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.

Abstract: The present invention provides a portable dual display reader including a first panel, a second panel, and an embedded system. The second panel attaches to one side of the first panel to be selectively in a folded configuration and an unfolded configuration. The embedded system is coupled to either the first panel or second panel. The embedded system has a microprocessor, a data source, and an operation system. The microprocessor processes or compiles a data string from the data source and displays the data string simultaneously on the first panel and the second panel. The operation system allows a user to enter at least one command to drive the related hardware apparatus of the embedded system, so as to accomplish the operation of the command. The data string further includes a first data string. The operation system cuts the first data string into several data segments and selectively displays the data segments on the first panel and the second panel in a sequential or non-sequential mode.

Abstract: Exemplary embodiments of methods, apparatuses, and systems for seamlessly migrating a user visible display stream sent to a display device from one rendered display stream to another rendered display stream are described. For one embodiment, mirror video display streams are received from both a first graphics processing unit (GPU) and a second GPU, and the video display stream sent to a display device is switched from the video display stream from the first GPU to the video display stream from the second GPU, wherein the switching occurs during a blanking interval for the first GPU that overlaps with a blanking interval for the second GPU.

Abstract: The object of the present invention is to provide a processor that is specifically suitable for three dimensional computer graphics that can handle pluralities of programs by only one processor. The control unit 11 of the processor of the present invention has n units of process controllers 21. The execute unit 13a-13h in the processor has register areas that correspond to the n units of process controllers 21. The present invention can therefore provide a processor that is specifically suitable for three dimensional computer graphics that can handle pluralities of programs by only one processor.

Abstract: An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel.

Abstract: Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Abstract: In a data processing system for determining intersections between geometric objects, the work is split between a CPU and a stream processor. The intersection determination is controlled by the CPU. Data processing intensive parts of intersection algorithms, such as checking possible overlap of objects, checking overlap of normal fields of objects, approximating the extent of an object, approximating the normal fields of an object, or making conjectures for intersection topology and/or geometry between objects, are run on the stream processor. The results of the algorithmic parts run on the stream processor are used by the part of the algorithms run on the CPU. In cases where conjectures for the computational result are processed on the stream processor, the conjectures are checked for correctness by algorithms run on the CPU. If the correctness check shows that the result found is incomplete or wrong, additional parts of the algorithm are run on the CPU and possibly on the stream processor.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A method of managing multiple contexts for a single mode display includes receiving a plurality of tasks from one or more applications and determining respective contexts for each task, each context having a range of memory addresses. The method also includes selecting one context for output to the single mode display and loading the selected context into a graphics processor for the display.

Abstract: An information processing apparatus including: a GUI generation unit configured to generate GUI data in which one of two mutually-orthogonal directions on a screen is allocated as a direction in which information flows, a plurality of processing systems for information processing are expressed as a plurality of lines along the one direction, and one or more blocks in which a name and setting value of one or more setting items of the processing system corresponding to at least one of the lines are displayed on the line are arranged; and a display processing unit configured to display the generated GUI data on the screen.

Abstract: A multi-pass method of generating an image frame of a 3D scene while eliminating the overdrawing of objects within the multiple graphics processing pipelines (GPPLs) supported on a parallel graphics processing system The GPPLs include a primary GPPL, and each GPPL, includes a color frame buffer and Z depth buffer. The GPPLs support an object-division based parallel graphics rendering process, in which the 3D scene is decomposed into objects that are assigned to particular GPPLs for processing. The multi-pass method involves, during a first pass, locally a Global Depth Map (GDM) which is provided to the Z depth buffer of each GPPL. This step involves the transmission of graphics commands and data for all objects in the image frame, to all GPPLs to be rendered. Then, during subsequent passes, a complementary-type partial image consisting of visible pixels only is generated within the color buffer of each GPPL using the GDM and a Z test filter supported by the Z depth buffer.

Abstract: A software engine for decomposing work to be done into tasks, and distributing the tasks to multiple, independent CPUs for execution is described. The engine utilizes dynamic code generation, with run-time specialization of variables, to achieve high performance. Problems are decomposed according to methods that enhance parallel CPU operation, and provide better opportunities for specialization and optimization of dynamically generated code. A specific application of this engine, a software three dimensional (3D) graphical image renderer, is described.

Abstract: Exemplary embodiments of methods and apparatuses to dynamically redistribute computational processes in a system that includes a plurality of processing units are described. The power consumption, the performance, and the power/performance value are determined for various computational processes between a plurality of subsystems where each of the subsystems is capable of performing the computational processes. The computational processes are exemplarily graphics rendering process, image processing process, signal processing process, Bayer decoding process, or video decoding process, which can be performed by a central processing unit, a graphics processing units or a digital signal processing unit. In one embodiment, the distribution of computational processes between capable subsystems is based on a power setting, a performance setting, a dynamic setting or a value setting.

Abstract: According to embodiments of the invention, a data structure may be created which may be used by both a ray tracing unit and by a rendering engine. The data structure may have an initial or upper portion representing bounding volumes which partition a three-dimensional scene and a second or lower portion representing objects within the three-dimensional scene. The integrated acceleration data structure may be used by a rendering engine to render a two-dimensional image from a three-dimensional scene, and by a ray tracing unit to perform intersection tests.

Abstract: A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.

Abstract: A system, method, and computer program product are presented for providing access to graphics processor central processing unit (CPU) cores, to both a graphics processor and a central processing unit. In operation, access is provided to a plurality of central processing unit cores of a graphics processor, to both the graphics processor and a central processing unit. Additionally, first requests are received from the central processing unit to execute first code utilizing at least one of the central processing unit cores of the graphics processor. Furthermore, second requests are received from the graphics processor to execute second code utilizing at least one of the central processing unit cores of the graphics processor. Still yet, there is arbitrating among the first requests and the second requests.

Abstract: One embodiment of the present invention sets forth a system that allows a software developer to perform shader debugging and performance tuning. The system includes an interception layer between the software application and the application programming interface (API). The interception layer is configured to intercept and store source code versions of the original shaders included in the application. For each object in the frame, the interception layer makes shader source code available to the developer, so that the developer can modify the source code as needed, re-compile only the modified shader source code, and run the application. Consequently, shader debugging and performance tuning may be carried out in a manner that is more efficient and effective relative to prior art approaches.

Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

Abstract: A method for controlling a video wall system, in which the video wall system includes a plurality of host processors. The method includes the step of transmitting a plurality of continuous commands without time interval therebetween one by one to the host processors and the step of the host processors synchronously performing corresponding operations according to the commands. A video wall system is also disclosed herein.

Abstract: The current invention allows the connection of a plurality of monitors to a single host computer, allowing the use by a plurality of users without the additional cost and complexity of a terminal server, local area network and thin clients or additional computers for each user. The host computer includes a video card having at least two separate video outputs, each connected to a monitor. Alternatively or additionally, the host includes a plurality of video cards. Each user interacts with a unique session that executes the user's application and displays its results on one of the monitors. The invention disclosed methods for enabling use of one or more physical graphics cards for one or more user sessions within a single computer. The invention disclosed methods to allow the assignment of a separate video output to each user by using video a plurality of drivers.

Abstract: A portable terminal that includes a first processing core configured to process data; a second processing core, which is faster than the first processing core, configured to process the data; and a storage unit configured to store multimedia data. The first and second processing cores are integrated into a single chipset, and are configured to be individually enabled or disabled based on a workload. The portable terminal is configured to be operated in one of a standby state and an operating state, to play back the multimedia data stored in the storage unit, and for Internet access.

Abstract: A method and apparatus for parallel processing of at least two bins relating to at least one of a video and an image. The method includes determining scan type of at least a portion of the at least one of video and an image, analyzing neighboring position of a bin, removing dependencies of context selection based on the scan type and position of location being encoded in a transform, and performing parallel processing of that least two bins.

Abstract: One embodiment of the present invention sets forth a technique for dynamically switching between a power-saving integrated graphics processing unit (IGPU) and a higher-performance discrete graphics processing unit (DGPU). This technique uses a single graphics driver and a single digital-to-analog converter (DAC) and leverages the GPU switching capability of the operating system to ensure a seamless transition. When additional graphics performance is desired, the system enters a hybrid graphics mode. In this mode, the DGPU is powered-up, and the graphics driver maintains the current display, while the operating system switches applications running on the IGPU to the DGPU. While in the hybrid graphics mode, the DGPU performs the graphics processing, and the graphics driver transmits the rendered images from the DGPU to the IGPU local memory and, then, to the IGPU DAC.

Abstract: A system and method for resolving the blank screen issue when switching between graphics processing units. The system and method provide a graphics adapter LCD timing controller (Tcon) with a frame buffer specifically dedicated to storing previously presented screen data for use when switching graphic processing units. The system further includes a protocol comparator unit within a serial-to-parallel converter and a memory controller coupled to the protocol comparator.

Abstract: One embodiment of the present invention sets forth a set of application programming interface (API) extensions that enable a software application to control the processing work assigned to each GPU in a multi-GPU system. The software application enumerates a list of available GPUs, sets an affinity mask from the enumerated list of GPUs and generates an affinity device context associated with the affinity mask. The software application can then generate and utilize an affinity rendering context that directs rendering commands to a set of explicitly selected GPUs, thus allocating work among specifically selected GPUs. The software application is empowered to use domain specific knowledge to better optimize the work assigned to each GPU, thus achieving greater overall processing efficiency relative to the prior art techniques.

Abstract: Direct macroblock mode techniques for high performance hardware motion compensation are described. An embodiment includes a hardware motion compensation graphics display device driver. More specifically, an embodiment mitigates a macroblock data parsing bottleneck in the display device driver by directly generating macroblock instructions and storing them in a dedicated buffer. For example, an embodiment includes an independent direct memory access instruction execution buffer for macroblock instructions separate from the direct memory access instruction execution buffer for all other hardware motion compensation instructions. Other embodiments are described and claimed.

Abstract: Embodiments of the invention provide devices and techniques for partitioning a spatial index. In one embodiment of the invention, an image processing system may partition a spatial index into a plurality of portions such that different processing elements may be responsible for traversing a ray through different portions of the spatial index. The determination of where to partition the spatial index may be made based on any number of factors. For example, according to some embodiments of the invention, the spatial index may be partitioned to evenly distribute workload (e.g., determined by real-time performance metrics) amongst multiple processing elements. Partitioning of the spatial index to distribute workload may be based on the total number of nodes, the number of leaf nodes or the number of primitives which will be included in each resulting partition.

Abstract: A data processing apparatus includes a plurality of processing units each performing a respective one of process parts into which a predetermined process to be performed on data is divided, and a changing unit that changes a connection between the plurality of processing units on the basis of setting parameters that are set to enable a plurality of types of processing procedures.

Abstract: A novel graphics system including workload detection software is disclosed. The novel graphics system increases the voltage and frequency of the graphics hardware in an integrated graphics chipset, depending on operations performed by the hardware, for either a performance advantage or a power savings advantage.

Abstract: One embodiment of the present invention sets forth a method for accessing display configuration information in a multi-GPU system, which includes the steps directing the display configuration information of a display device, coupled to a discrete GPU (dGPU), to a controller capable of accessing a display data bus, if the dGPU is unavailable, wherein the controller is capable of making the display configuration information available via a system interface, and validating the display configuration information prior to availing the dGPU or the display device as an option to be selected.

Abstract: Where each of m and n are any natural number: a drawing region subdivider 5 for subdividing a drawing region into an m×n matrix of drawing subregions having m rows and n columns,; a target vector data selector 6 for discriminating, for each of the drawing subregions, vector data necessary for drawing the drawing subregion from vector data of an image; and a subdivisional drawer 7 for drawing, for each of the drawing subregions after the subdivision by the drawing region subdivider 5, an image based on a drawing subregion target vector data 23 discriminated by the target vector data selector 6 are provided as necessary for drawing the drawing subregion. Preferably, a curve vector data replacer 71 of the subdivisional drawer 7, for each of the drawing subregions, replaces curve vector data outside of the drawing subregion from vector data configuring a figure to be subdivisionally drawn with straight-line vector data and performs a fill processing.

Abstract: The present invention uses a common, hybrid system platform to provide a generalized medical image processing system that can handle the existing medical image application as it is and route the compute intensive medical image processing to a multi-core processor/processing system. The invention allows the processing platform to be shared among healthcare system such as mammography, X-ray, CT Scan MRI, two-photon, laser microscopy, digital pathology, etc. It also allows the processing platform to deliver medical images to a variety of client devices, such as a desktop computer or a handheld device, through the network without high-performance graphical display capabilities because the rendering of the medical images is performed on the Cell BE based platform of the invention.

Abstract: A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.

Abstract: One embodiment of the present invention sets forth a technique for dynamically switching between a power-saving integrated graphics processing unit (IGPU) and a higher-performance discrete graphics processing unit (DGPU). This technique uses a single graphics driver and a single digital-to-analog converter (DAC) and leverages the GPU switching capability of the operating system to ensure a seamless transition. When additional graphics performance is desired, the system enters a hybrid graphics mode. In this mode, the DGPU is powered-up, and the graphics driver maintains the current display, while the operating system switches applications running on the IGPU to the DGPU. While in the hybrid graphics mode, the DGPU performs the graphics processing, and the graphics driver transmits the rendered images from the DGPU to the IGPU local memory and, then, to the IGPU DAC.

Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.