Abstract: A system (100) useful in compositing images (100) comprises a pre-visualization application (102) for producing an initial graphics output (104). A visual effects (VFX) compositor (106) receives the initial graphics output (104), input data (108), and a captured image (110). The VFX compositor and produces a composite image (112) based on the initial graphics output (104), the input data (108) and the captured image (110).

Abstract: One embodiment of the present invention sets forth a method for dynamically load balancing rendering operations across an IGPU and a DGPU. For each frame, the graphics driver configures the IGPU to pre-compute Z-values for a portion of the display surface and to write feedback data to the system memory indicating the time that the IGPU used to process the frame. The graphics driver then configures the DGPU to use the pre-computed Z-values while rendering to the complete display surface and to write feedback data to the system memory indicating the time that the DGPU used to process the frame. The graphics driver uses the feedback data from the IGPU and DGPU in conjunction with the percentage of the display surface that the IGPU Z-rendered for the frame to scale the portion of the display surface that the IGPU Z-renders for one or more subsequent frames. In this fashion, overall processing within the graphics pipeline is optimized across the IGPU and DGPU.

Abstract: According to one embodiment, a graphics processing unit comprises a host interface, a plurality of processing cores, an arithmetic control unit, a video signal output interface, and an audio signal output interface. The host interface is configured to receive video data and audio data from a host. The arithmetic control unit is configured to process the video and audio data using at least a first processing core and a second processing core respectively. The video signal output interface is configured to output a video signal corresponding to the processed video data. The audio signal output interface is configured to output an audio signal corresponding to the processed audio data.

Abstract: One embodiment of the present invention sets forth a system configured for transferring data between independent application programming interface (API) contexts on one or more graphics processing units (GPUs). Each API context may derive from an arbitrary API. Data is pushed from one API context to another API context using a peer-to-peer buffer “blit” operation executed between buffers allocated in the source and target API context memory spaces. The source and target API context memory spaces may be located within the frame buffers of the source and target GPUs, respectively, or located within the frame buffer of a single GPU. The data transfers between the API contexts are synchronized using semaphore operator pairs inserted in push buffer commands that are executed by the one or more GPUs.

Abstract: A processing unit, method, and graphics processing system are provided for processing a plurality of frames of graphics data. For instance, the processing unit can include a first plurality of graphics processing units (GPUs), a second plurality of GPUs, and a plurality of compositors. The first plurality of GPUs can be configured to process a first frame of graphics data. Likewise, the second plurality of GPUs can be configured to process a second frame of graphics data. Further, each compositor in the plurality of compositors can be coupled to a respective GPU from the first and second pluralities of GPUs, where the plurality of compositors is configured to sequentially pass the first and second frames of graphics data to a display module.

Abstract: The present invention relates to an apparatus and method for processing graphic data. According to an embodiment, the graphic data processing apparatus includes a CPU having at least one core; a GPU configured to process graphic data; a usage level checking unit configured to check a usage level of the CPU and/or a usage level of the GPU; and a control unit configured to compare the checked usage level of the CPU with a usage level reference of the CPU and/or to compare the checked usage level of the GPU with a usage level reference of the GPU, to allow the graphic data to be processed in parallel by the CPU and the GPU or only by the GPU according to the comparison results.

Abstract: A method of coding, in the form of a digital file of a three-dimensional synthesis image, a model of an object formed by a stream of image elements (FEI) in which elementary images which are subsets of image elements {EIe}e=1e=ex are discriminated (A) in the stream (FEI), each elementary image is coded (B) according to an index value (n) representative of the elementary image, the numerical values (Zk,g,i) of the 3D synthesis image are calculated (C) and these values are stored in the form of a digital file. Application to 3D display involving an interactive dialogue with a user of a graphics application.

Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.

Abstract: Methods of operating a portable media device 100 including two onboard hardware media decoders (124, 128) operative to decode a given digital content item 148 are disclosed. In some embodiments, one of the onboard hardware media decoders 128 has a relatively high power consumption and produces a relatively ‘high quality’ media signal, and the other of the onboard hardware media decoder 124 has a relatively low power consumption and produces a relatively ‘low quality’ media signal.

Abstract: A graphics processing unit includes a first processing controller controlling a first set of multi-threaded processors. A second processing controller controls a second set of multi-threaded processors. A serial bus connects the first processing controller to the second processing controller. The first processing controller gathers first state information from the first set of multi-threaded processors in response to a context switch token and then passes the context switch token over the serial bus to the second processing controller. The second processing controller gathers second state information from the second set of multi-threaded processors in response to the context switch token.

Abstract: Methods and apparatuses are disclosed for improving switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of GPUs, a multiplexer coupled to the plurality of GPUs, a timing controller coupled to the multiplexer, where the timing controller may provide an indication signal to the multiplexer indicative of a period when a first GPU is experiencing a first blanking interval.

Abstract: An apparatus and method for processing a frame in consideration of processing capability and power consumption for each core in a multi-core system are provided. To perform a user interface drawing in a multi-core environment, an optimum combination of hardware components capable of operating with the minimum of power consumption while satisfying a requirement of a user may be obtained and a parallel user interface drawing may be performed by use of the optimum combination of hardware components.

Abstract: An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: A graphics processing method and apparatus described herein is capable of converting graphics processing of a window system into a vector-based application program interface (API) format usable in the GPU and performing the converted graphics processing in the GPU. For example, the vector-based API may be based on an OpenVG standard or an EGL standard.

Abstract: Some embodiments provide a method of performing several shading operations for a graphic object in a scene that is displayed on a device. The device includes several processing units. The method receives a set of criteria that can define a set of parameters that relate to the shading operations. The method determines an allocation of the shading operations to the processing units based on the received criteria. The method allocates the shading operations to the processing units based on the determined allocations. The method renders the graphic object based on several instructions that comprise the shading operations. In some embodiments, the set of criteria is received during execution of the operations.

Abstract: Disclosed is a system for producing images including techniques for reducing the memory and processing power required for such operations. The system provides techniques for programmatically representing a graphics problem. The system further provides techniques for reducing and optimizing graphics problems for rendering with consideration of the system resources, such as the availability of a compatible GPU.

Abstract: A method, computer program product, and computing system are provided for processing a graphics operation. For instance, the method can include receiving the graphics operation from an application. The method can also include allocating a first portion of the graphics operation to a first processing unit and a second portion of the graphics operation to a second processing unit. This allocation between the first and second processing units can be based on at least one of a performance profile and a functionality profile of the first and second processing units.

Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Abstract: A system, method, and computer program product are provided for enabling or disabling a graphics processor during runtime. In use, a command is received to disable or enable a graphics processor. Such graphics processor is enabled or disabled during runtime, in response to the command.

Abstract: A data processing apparatus including a first graphic controller configured to process a first image, the first image being one of a first still, moving and three dimensional (3D) image; a second graphic controller configured to process a second image, the second image being one of a second still, moving and three dimensional (3D) image, the first and second graphic controllers being integrated into one chip; and a controller operatively connected to the first and second graphic controllers and configured to determine whether to enable the second graphic controller, and change the second graphic controller from an inactive state to an enabled state. Further, though the second graphic controller is changed from the inactive state to the enabled state, the first graphic controller is maintained in an enabled state.

Abstract: Collaborative environments in a geographic information system (GIS) are disclosed. Collaboration between multiple processors can be provided within the GIS. A first processor can stream a scenario describing geo-spatial analysis of the image conducted by the first processor. The scenario can include a set of parameters executed by the first processor for review by a user of a second processor. The user of the second processor can transmit a response back to the first processor. The response can include an addition to the scenario, an edit to the scenario, a comment, or acceptance of the scenario. The server can stream the scenario, and/or the images as well as the response between the first and second processors. The image can include three dimensional data and streaming of data can occur across networks such as the Internet.

Abstract: A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

Abstract: In some aspects, finer grained parallelism is achieved by segmenting programmatic workloads into smaller discretized portions, where a first element can be indicative both of a configuration or program to be executed, and a first data set to be used in such execution, while a second element can be indicative of a second data element or group. The discretized portions can cause program execute on distributed processors. Approaches to selecting processors, and allocating local memory associated with those processors are disclosed. In one example, discretized portions that share a program have an anti-affinity to cause dispersion, for initial execution assignment. Flags, such as programmer and compiler generated flags can be used in determining such allocations. Workloads can be grouped according to compatibility of memory usage requirements.

Abstract: A system with switch and on-screen display function includes a display device and a switch device. The display device includes a display panel and a display circuit. The display circuit is coupled with the display panel and is configured to control the display device. The display circuit includes an on-screen display generating circuit. The switch device is coupled with the display device and is configured to switch an access to one of at least two computers. The on-screen display generating circuit includes a signal receiving circuit, a processing circuit and a signal outputting circuit. The signal receiving circuit is configured to receive command signals from the switch device. The processing circuit generates first on-screen display menu signals for providing a first on-screen display menu in response to the received command signals. The signal outputting circuit of the on-screen display generating circuit provides the first on-screen display signals to the display panel.

Abstract: A plurality of vertex or fragment processors on a graphics processor perform computations. Each vertex or fragment processor is capable of executing a separate program to compute a specific result. A combiner manages the combination of the results from the respective processors, and produces a final transformed vertex or pixel value. The vertex or fragment processors and the combiner can be programmable to modify their operations. As such, the vertex or fragment processors can operate in a parallel or serial configuration, or both. The combiner manages and resolves the operations of the serial and/or parallel configurations. A synchronization barrier enables the combiner to perform data-dependency analysis to determine the timing and ordering of the respective processors' execution. A transformation module can include one or more programmable vertex processors that transforms three-dimensional geometric data into fragments.

Abstract: Electronic devices with more than one video output terminals and capable of providing distinct videos at different video output terminals. The electronic device comprises first and second display processors driving first and second video output terminals, respectively. The first display processor comprises a blender and a multiplexer. The blender blends a video with image signals, provides a fully-blended video for the first video output terminal, outputs the video, the partly-blended videos and the fully-blended video to the multiplexer. The second display processor is coupled between the output terminal of the multiplexer and the second video output terminal.

Abstract: A graphics engine and related method of operation are disclosed in which a pixel distributor distributes pixel data across a plurality of pixel shaders using a first approach when the presence of one or more rendering features is indicated, else using a second approach different from the first approach.

Abstract: Graphics processing units (GPUs) deployed in general purpose GPU (GPGPU) units are combined into a GPGPU cluster. Access to the remote GPGPU cluster is then offered as a service to users who can use their own computers to communicate with the GPGPU cluster. The users' computers can be standalone desktop systems, laptops, or even another GPGPU cluster. The user can run a parallelized application locally and patiently wait for results or can dynamically recruit the remote GPGPU cluster to obtain those results more quickly. Dynamic recruitment means that the users can add remote GPGPU resources to a running application.

Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.

Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.

Abstract: Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: Exemplary embodiments include an interception mechanism for rendering commands generated by interactive applications, and a feed-forward control mechanism based on the processing of the commands on a rendering engine, on a pre-filtering module, and on a visual encoder. Also a feed-back control mechanism from the encoder is described. The mechanism is compression-quality optimized subject to some constraints on streaming bandwidth and system delay. The mechanisms allow controllable levels of detail for different rendered objects, controllable post filtering of rendered images, and controllable compression quality of each object in compressed images. A mechanism for processing and streaming of multiple interactive applications in a centralized streaming application server is also described.

Abstract: An image processing unit includes a computing unit, a data input unit that inputs image data to the computing unit, a data output unit that outputs the image data computed by the computing unit, and a setting unit. The computing unit includes computing cells including multiple types of computing cells, input domain selectors, and at least one of output domain selectors. The setting unit sets the input domain selectors and the output domain selectors so that image data inputted by the data input unit to the computing unit on which desired computing has been performed by at least one computing cell among the computing cells is outputted from the data output unit.

Abstract: A system is presented that is configured to reduce power consumption when performing processing tasks. The system includes a first processing entity capable of performing a set of operations, and a second processing entity configured to consume less power than the first processing entity and capable of performing a subset of operations that is part of the set of operations. During system operation, the second processing entity is configured to perform the subset of operations instead of the first processing entity.

Abstract: One embodiment of the present invention sets forth a method, which includes the steps of generating a first rendered image associated with a first application, independently generating a second rendered image associated with a second application, applying a first set of blending weights to the first rendered image to establish a first weighted image, applying a second set of blending weights to the second rendered image to establish a second weighted image, and blending the first weighted image and the second weighted image before scanning out a blended result to a first display device.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: Techniques to generate partial display updates in a buffered window system in which arbitrary visual effects are permitted to any one or more windows (e.g., application-specific window buffers) are described. Once a display output region is identified for updating, the buffered window system is interrogated to determine which regions within each window, if any, may effect the identified output region. Such determination considers the consequences any filters associated with a window impose on the region needed to make the output update.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: A parallel graphics rendering system is embodied within a host computing system and includes a plurality of graphic processing pipelines (GPPLs) and graphics processing modules. The parallel graphics rendering system supports one or more modes of parallel operation selected from the group consisting of object division, image division, and time division. a plurality of graphic processing pipelines The GPPLs support a parallel graphics rendering process that employs one or more of the object division, image division and/or time division modes of parallel operation in order to execute graphic commands and process graphics data, and render pixel-composited images containing graphics for display on a display device during the run-time of the graphics-based application. An automatic mode control module automatically controls the mode of parallel operation of the parallel graphics rendering system during the run-time of the graphics-based application.

Abstract: A system, module, and method of enabling a video interface within a limited resource enabled information handling system are disclosed. In a particular form, a processing module can include a processor configured to initiate an outputting of a video signal to a host processing system including a video display. The processing module can further include a Mini-card enabled interface operable to be coupled to the host processing system to the host processing system to allow the video signal to be transmitted there between. The processing module can also include a video output channel configured within the Mini-card enabled interface and accessible to the processor to output the video signal to the host processing system.

Abstract: A virtual graphics processing unit within a virtual machine may be restored by causing a reset to the virtual graphics processing unit. The state of the virtual graphics processing unit may not be saved during a migration or save and restore operation, but a reset of the virtual graphics processing unit may cause all applications with processes in the virtual graphics processing unit to re-start and thereby recreate the state of the virtual graphics processing unit. A hypervisor may include a separate graphics processor unit process that may present a virtual graphics processing unit to a virtual machine and communicate with a physical graphics processing unit in hardware. When a virtual machine may be restored after a save or migration, the hypervisor may cause the virtual graphics processor unit to reset and its state to be recreated.

Abstract: Multiprocessor graphics systems support distributed antialiasing. In one embodiment, two (or more) graphics processors each render a version of the same image, with a difference in the sampling location (or locations) used for each pixel. A display head combines corresponding pixels generated by different graphics processors to produce an antialiased image. This distributed antialiasing technique can be scaled to any number of graphics processors.

Abstract: Systems, methods, and computer-readable media for efficiently processing graphical data using an electronic device are provided. A characteristic of graphical data may be identified and compared to a threshold. Based on whether the identified characteristic meets the threshold, the graphical data may be rendered either entirely by a first type of graphical processing unit or by both the first type of graphical processing unit and by a second type of graphical processing unit.

Abstract: A game console system capable of parallelizing the operation of multiple graphics processing units (GPUs) supported on game console board, using a graphics hub device, and a multi-mode parallel graphics rendering subsystem supporting multiple modes of parallel operation and having software and hardware implemented components. The game console system includes (i) CPU memory space for storing one or more graphics-based applications, (ii) one or more CPUs for executing the graphics-based applications, (iii) a plurality of graphic processing pipelines (GPPLs), implemented using the GPUs, and (iv) an automatic mode control module. During the run-time of the graphics-based application, the automatic mode control module automatically controls the mode of parallel operation of the multi-mode parallel graphics rendering subsystem so that the GPUs are driven in a parallelized manner.

Abstract: In an information processing apparatus (1) according to the invention, a GMCH (13) is connected to a CPU (11) through a CPU bus (12), and an ICH (15) is connected to the GMCH (13) through a dedicated bus (14). The GMCH (13) includes a graphics controller (131) which borrows a part of a memory (171) mounted to a memory card (17) in order to execute display processing. A graphics card (19) can be connected to the GMCH (13). In this case, a graphics controller (131) becomes a stop state. While the graphics card (19) is connected to the GMCH (13), the CPU (11) instructs the graphics controller (13) to execute processing other than display control processing, for example, processing such as MC and IDCT. As a result, it is possible to reduce a load applied to the CPU (11).

Abstract: An electronic device is provided. The electronic device includes a base, a first cover and a second cover. The first cover is rotatably disposed on the base between a first position and a second position. When the first cover is at the first position, the cover is closed relative to the base, and when the first cover is at the second position, the cover is open relative to the base. The second cover is movably disposed on the base between a third position and a fourth position. When the first cover is rotated from the first position to the second position, the second cover is pushed thereby from the third position to the fourth position.

Abstract: A server auxiliary operating system is disclosed, which includes a case, a plurality of swappable GPUs and a printed circuit back plane. The case includes a bottom board and a first mounting bay located at the front portion of the case. The swappable GPUs are disposed in the first mounting bay. The printed circuit back plane is disposed on the bottom board and has a plurality of first interfaces and a plurality of second interfaces electrically corresponding to the first interfaces, wherein the swappable GPUs are respectively coupled to the first interfaces, and the servers are respectively electrically connected to the corresponding swappable GPUs through the second interfaces respectively connected to the servers so as to expand the server operation capability.

Abstract: A method and apparatus employing selectable hardware accelerators in a data driven architecture are described. In one embodiment, the apparatus includes a plurality of processing elements (PEs). A plurality of hardware accelerators are coupled to a selection unit. A register is coupled to the selection unit and the plurality of processing elements. In one embodiment, the register includes a plurality of general purpose registers (GPR), which are accessible by the plurality of processing elements, as well as the plurality of hardware accelerators. In one embodiment, at least one of the GPRs includes a bit to enable a processing element to enable access a selected hardware accelerator via the selection unit.