Abstract: A method for fully-automatically aligning the quality of an image is provided. The method processes the video signals provided by the Video Graphic Array (VGA) display card in the computer system through the multi-sync display itself, and further interprets whether a computer host ID stored in the VGA display card or the computer host matches with a computer host ID stored in the multi-sync display, so as to avoid repetitious aligning to the same computer system, and achieve full automatic aligning to the quality of the image displayed on the multi-sync display. Therefore, even if the multi-sync display is situated under different computer hosts or VGA display cards and placed where an user cannot touch, the inconvenience of pressing a button on the multi-sync display to align the quality of the image displayed on the multi-sync display in conventional techniques can be prevented.

Abstract: Provided are a display device with low power consumption which enables reduction of an operation processing amount of a GPU and which does not require a storage device for storing image data corresponding to one screen, and a display system using the display device. The display device is constituted by pixels each including storage circuits, an operation processing circuit, and a display processing circuit and circuits each having a function of storing image data in arbitrary storage circuits. The display system is constituted by the display device and an image processing device including the GPU. Image data is formed for each structural component through operation processing in the GPU in the display system. The formed image data is stored in the corresponding storage circuit for each pixel. The stored image data is subjected to composition processing by the operation processing circuit for each pixel. Then, the image data is converted into an image signal in the display processing circuit.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.

Abstract: In response to a requirement of transferring a file from a personal computer PC to a projector 10 that is output by dragging and dropping a corresponding file icon onto a projector icon, a CPU 50 requires setting of a password. The CPU 50 maps the preset password to a file and transfers the file with the password to an external storage device of the projector 10. The projector 10 requires input of a password, which is expected to be assigned to the file, and allows reproduction of the file when the input password is coincident with the preset password.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method of controlling timing signals includes; selectively providing both master control data and slave control data, which are included in control data, to a memory part based on a write enable signal provided form an external device, reading control data stored in the memory part in response to a reset signal provided from an external device, and controlling output timing of at least one power voltage based on the stored control data.

Abstract: Disclosed herein is an image processing apparatus, including: first storage means for storing data in a unit of a word; second storage means for storing data in a unit of a word, address information for managing writing and reading out of the data of a unit of a word and a correction flag which indicates, in a unit of a word, whether or not it is necessary to correct the data, in an associated relationship with each other; and supplying means for reading out and supplying the data of a unit of a word, corresponding address information and a corresponding correction flag stored in the second storage means to the first storage means; the first storage means referring to the address information to correct the data of a unit of a word corresponding to the correction flag to the data of a unit of a word.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: A display apparatus include a connector, a readable/writable EDID storage to store EDID, and a controller to control the EDID storage to be write-protected from error data transmitted from a computer through the connector. With this configuration, the display apparatus and a method of controlling the same can prevent error data from being stored in an EDID storage.

Abstract: A display device of the present invention displays a first image stored in first memory and a second image stored in second memory, by overlaying the first image on the second image. Once a display size/position of the first image is acquired, a first image generation unit is controlled to start generating the first image complying with the acquired display size/position. Until generation of the first image is completed, (i) a second image generation unit is controlled to generate an opaque second image that is opaque and large enough in size to cover the first image being generated, and (ii) the opaque second image is displayed. Upon completion of generation of the first image, (i) the second image generation unit is controlled to generate a partially transparent second image including a transparent part to be positioned over the first image, and (ii) the partially transparent second image is displayed.

Abstract: One embodiment of the invention includes an image compensation module, an OLED display panel, and an OLED display apparatus. A target current value corresponding to a target gray level is stored in a compensation memory portion. A reference gray level and a reference current value corresponding to the reference gray level are stored in a reference memory portion. A compensation gray level can be obtained by an arithmetic compensation unit according to the target current value, reference gray level, reference current value, and gamma parameter. This may reduce the memory space needed for the compensation and reference memory portions, and compensate the images of the display apparatus and panel so that precise colors can be displayed with a high image quality.

Abstract: An electrophoresis display is provided to reduce writing time of a memory. The electrophoresis display includes: an electrophoresis display panel; a first memory and a second memory for alternatively storing a previous state image and a current state image; and a controller sets the first digital data generated by the system as the current state image and stores it alternately in one of the first and second memories every cycle, keeps storing the first digital data previously stored in the other one of the first and second memories in it as the previous state image, compares the current state image and the previous state image, and generates second digital data to be displayed on the electrophoresis display panel by use of waveform information corresponding to the result of the comparison among the plurality of waveform information.

Abstract: A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.

Abstract: A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing system includes an embedded memory array having at least three separate banks of single-ported memory in which graphics data are stored in memory page format. A memory controller coupled to the banks of memory writes post-processed data to a first bank of memory concurrently with reading data from a second bank of memory. A synchronous graphics processing pipeline processes the data read from the second bank of memory and provides the post-processed graphics data to the memory controller to be written back to the bank of memory from which the pre-processed data was read. The processing pipeline is capable of concurrently processing an amount of graphics data at least equal to the amount of graphics data included in a page of memory.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.

Abstract: A driving method of a display device for performing time-division gray scale display is disclosed, which is capable of inputting accurate data into a panel by using one memory. M groups each having a pair of a first period and a second period are provided in one frame period. Video signals are written into a memory in the first period of at least one group among the m groups, while video signals are read out from the memory in the respective second periods of the m groups. The start timing of reading out video signals from the memory is synchronized with the start timing of each of the n sub-frame periods.

Abstract: A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.

Abstract: Video processors and memory management methods thereof are provided, wherein the video processor is controlled by a central processing unit, and is coupled to a system memory to receive a macroblock. The video processor has two local memories, a control circuit and an image processing unit. The control circuit divides the macroblock into pixel segments, and disposes the pixel segments in the two local memories. The image processing unit accesses the two local memories for executing an image processing procedure. The system memory is refreshed by a processed macroblock in the two local memories.

Abstract: A data receiving apparatus and control method are provided. The apparatus includes a determining part determining whether a clock signal and a data signal are respectively in a high state and/or in a low state based on a predetermined value of a standard level, when the clock signal and the data signal are received from an external apparatus; and a controller determining a data communicating state corresponding to the high state and/or the low state of the clock signal and the data signal determined in the determining part.

Abstract: The camera reads identification information of the user, which is contained in an identification card, through a card reading part. The camera connects automatically to a server designated in accordance with the read identification information through a communication interface. Then, the camera transmits and stores the data of recorded images to the designated server. The camera retrieves the image data stored in the server, and reproduces and displays the image on an image display at the back of the camera. A plurality of cameras in which the same user's identification information is set can be controlled altogether in the image-recording and reproduction by one camera. One camera in which the identification information of a plurality of user's is set can distribute the recorded image data to the servers of the users simultaneously.

Abstract: An object is to realize high-capacity of a memory while reducing power consumption and making the power consumption even throughout the memory. A memory includes a plurality of memory block arranged to be symmetrically to each other. Also, a specific combination of signals among address signals supplied to the memory, a memory block including a memory cell to be read from or written to is specified. Further, signals supplied to other memory blocks than the above memory block is maintained at a constant value. Consequently, a wiring length of a bit line in a memory array can be shortened, and current consumption can be made to be even among data reading or writing from/to memory cells of a variety of addresses within the memory, at the same time as reducing load capacitance.

Abstract: A liquid crystal display includes a liquid crystal panel and a timing controller. The timing controller includes a first memory unit which sequentially receives a first image signal and a second image signal at a first data rate and outputs the first and second image signals at a second data rate, a second memory unit which compresses and stores the first image signal at the second data rate as a compressed first image signal and outputs the compressed first image signal as a restored first image signal, and an image signal compensation unit which receives the second image signal and the restored first image signal at the second data rate, compensates the second image signal to generate a compensated second image signal using the restored first image signal at the second data rate, and outputs the compensated second image signal at the second data rate to the liquid crystal panel.

Abstract: In a method of compensating image data, a lookup table (LUT) memory storing compensating data that corresponds to received image data is disabled when the received image data is substantially the same as previous image data that is stored in a cache memory. Compensating data that corresponds to the previous image data stored in the cache memory is outputted as compensating data that corresponds to the received image data. The previous image data stored in the cache memory and the compensating data are maintained.

Abstract: Methods and machines which increase image processing performance by efficiently copying image data from input memory to main memory before performing CPU intensive operations, such as image enhancement, compression, or encryption, and by efficiently copying image data from main memory to output memory after performing CPU intensive operations, such as decryption, decompression, image enhancement, or reformatting.

Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.

Abstract: In a display method applied to an electrophoretic display, the electrophoretic display has a first memory, a second memory and an electrophoretic display panel. A plurality of data is stored in the first memory according to a predetermined sequence. The display method includes the following steps. Firstly, whether a first datum of the data is stored in the second memory is determined. Next, the first datum is read out from the first memory and stored in the second memory if the first datum is not stored in the second memory. Next, the first datum stored in the second memory is displayed on the electrophoretic display panel. Next, a second datum before the first datum and/or a third datum after the first datum are/is read out from the first memory and stored in the second memory during displaying the first datum on the electrophoretic display panel.

Abstract: Disclosed is a system and method for processing graphic operations on a plurality of data structures of an image with a graphics processing unit and memory. The disclosed techniques of the system and method create an accumulation buffer of the data structures for accumulating changes to the data structures. A separate buffer is then created from at least a portion of the data structures of the accumulation buffer. The disclosed techniques read the data structures from the separate buffer with the graphics processing unit. The graphics processing unit operates on the data structures read from the separate buffer with the operation. Then, the disclosed techniques write the results of the operation onto the portion of the accumulation buffer corresponding to the separate buffer.

Abstract: A method for rapidly displaying pictures on an electronic device receives an identifier of a picture to be displayed. If processed data of the picture exists in a second memory of the electronic device, the processed data is retrieved from the second memory, and the picture is displayed. Otherwise, if processed data of the picture does not exist in the second memory, raw data of the picture is retrieved from a first memory of the electronic device, and the processed data is generated by encoding the raw data. The generated processed data are stored and the picture is displayed.

Abstract: An apparatus includes an image buffer, a graphics buffer, a memory, a router, and a sensor interface. The apparatus further includes a memory controller for controlling transfer of image data from the image buffer to the memory via the router and for controlling transfer of graphics data from the memory to the graphics buffer via the router. The apparatus also includes an image controller simultaneously operable with the memory controller for controlling transfer of the image data from the sensor interface to the image buffer. Optionally, the sensor interface comprises a receiver and a transmitter. Optionally, the apparatus further includes a header buffer, and a header controller simultaneously operable with the memory controller for controlling transfer of header data from the sensor interface to the header buffer. The apparatus optionally further includes a sensor for communicating with the header controller via the sensor interface.

Abstract: Methods and apparatuses for dynamic virtual frame buffer management. At least one embodiment of the present invention dynamically enables or disables the use of a virtual frame buffer, which is not under control of graphics hardware of a data processing system, without restarting the graphical user interface system (e.g., the window system) of the data processing system. For example, in response to the addition or removing of a frame buffer that is under control of a graphics controller (e.g., due to the activation or deactivation of the graphics controller, or the hot plug-in or hot disconnection of the graphics controller), the virtual frame buffer is disabled or enabled respectively.

Abstract: Digital tile-based mapping techniques are disclosed that enable efficient online serving of aesthetically pleasing maps. In one particular embodiment, an image tile-based digital mapping system is configured for generating map tiles during an offline session, and serving selected sets of those tiles to a client when requested. Also provided are solutions for handling map labels and other such features in a tile-based mapping system, such as when a map label crosses map tile boundaries. Various processing environments (e.g., servers or other computing devices) can be employed in the system.

Abstract: A hierarchical movie is provided. A hierarchical movie is a movie that contains one or more embedded movies. Embedded movies may themselves contain embedded movies. Each movie contains zero or more media sequences. Within a hierarchical movie, media sequences that should be edited together may be grouped together using embedded movies. The media sequences of a hierarchical movie may be sequenced during playback based on a different time coordinate system than the time coordinate system that governs any embedded movies. This allows a movie to contain both time-based and time-independent media sequences. Also, the relative timing of events in the movie may vary from performance to performance. The hierarchical movie structure allows movies to be used as user interface controls, and even as field-sensitive databases.

Abstract: Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.

Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.

Abstract: A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen.

Abstract: A technique for performing an anti-aliasing operation by multiple graphics processing units includes utilizing a first graphics processing unit to generate a first subset of filtered data resulting from performing anti-aliasing processing and similarly utilize a second graphics processing unit to generate a second subset of filtered data. The first graphics processing unit then pulls a first portion of the second subset of filtered data from a first memory block of a temporary buffer and blends such pulled data with a first portion of the first subset of filtered data. Overlapping in time with the pulling and blending operation of the first graphics processing unit, the second graphics processing unit pulls a second portion of the first subset of filtered data from a second memory block of the temporary buffer and blends such pulled data with a second portion of the second set of filtered data.

Abstract: ABSTRACT OF THE DISCLOSURE In an active matrix type display device including two source line side drivers for driving a plurality of pixel TFTs, one gate line side driver, two line memories respectively including at least first and second memories, and a controller for controlling the first and second line memories, storing and transmitting of picture data of the two line memories are switched to transmit the data to the two source line side drivers at the same time.

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: A pixel load instruction for a programmable graphics processor. The pixel load instruction may be used during processing of graphics data to load graphics data from a writable output buffer into a local storage element. Using the pixel load instruction may ensure that the graphics data loaded is current, i.e., any pending writes to the location storing the graphics data are completed prior to loading the graphics data. Furthermore, the pixel load instruction may be enabled and disabled for one or more writable output buffers by setting or clearing bits in a pixel load enable register.

Abstract: An image loading method applied to an electronic device having a display is provided. The method has the following steps. Firstly, an image is decompressed into a second bitmap file. Afterward, a bitmap attribute is obtained according to the second bitmap file. Following, a bitmap attribute is obtained according to the second bitmap file. Then, the bitmap attribute corresponding to an image is accessed. Next, a first bitmap file is generated in a first system memory according to the bitmap attribute. Then, the first bitmap file is outputted to the display.

Abstract: A method for processing display data includes: storing an image data in a plurality of first-type memories by taking scanning line data as a unit; providing one of the scanning line data stored in a particular memory of the first-type memories to one of a plurality of second-type memories, the particular memory being one of the first-type memories, which are not receiving and storing the image data; and outputting the scanning line data stored in the second-type memories. Time periods for outputting the scanning line data of the image data from the second-type memories are not overlapped.

Abstract: A display of CPU utilization in a multiprocessor system is provided. This feature illustrates processor utilization and application group assignments to CPUs and clusters of CPUs. Various graphic indicator are described that can be used to display processor utilization and indicate processors that have no application group assignments. For example, bar graphs as well as gauge displays can be used to visually convey processor utilization. As a result, a user can visually determine the processor utilization and application group assignments across a multiprocessor system. Additionally, various colors and shadings can be used to visually convey application group assignments.

Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.

Abstract: An image signal processing circuit, comprising: a first memory part; a second memory part; and a control circuit which controls the first memory part and the second memory part, wherein the image signal processing circuit is constituted so that image signals outputted from one of the first memory part and the second memory part are inputted into the other of the first memory part and second memory part; and wherein the control circuit is a circuit which controls the first memory part so that image signals are outputted in inverse order from the first memory part to inputted order into the first memory part, and controls the second memory part so that image signals are outputted in inverse order of lines composed of image signals from the second memory part to inputted order of lines composed of image signals into the second memory part.

Abstract: Circuits, methods, and apparatus for multiplexing addresses and data at a memory interface such that multiple data widths are provided without the need to change a motherboard or other printed circuit board design. A specific embodiment of the present invention achieves this using a single integrated circuit design where the datapath width is selected using a bonding option, fuse, data input, or other selection mechanism. The specific embodiment supports both 64 and 128-bit datapaths, though other numbers of datapaths, and other datapath widths are supported by other embodiments.

Abstract: Methods and apparatus for adjusting the geometry of buffer pages.

Abstract: Methods and systems for processing pixels within a decoded video stream are disclosed. Processed pixels may be received within the decoded video stream and may be buffered in a buffer at a first rate. The buffered received processed pixels may be transferred out of the buffer at a second rate, where the first rate is greater than said second rate. The buffering of the received processed pixels and the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent an overrun of the buffer. The first rate of the buffering of the received processed pixels may be reduced to prevent the overrun of the buffer. The second rate of the transferring of the buffered received processed pixels out of the buffer may be monitored to prevent the overrun of the buffer. Amount of the buffered received processed pixels within the buffer may be determined.

Abstract: A method and apparatus for processing vector data is provided. A processing core may have a data cache and a relatively smaller vector data cache. The vector data cache may be optimally sized to store vector data structures that are smaller than full data cache lines.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.