Abstract: A multilayer chip capacitor includes: a capacitor main body; a plurality of first and second inner electrodes; and m (m?3) number of first and second outer electrodes. The plurality of first and second inner electrodes are connected with two outer electrodes positioned on both opposing surfaces and having the same polarity as that of the first and second inner electrodes, and classified into a plurality of groups depending on the locations of the outer electrodes connected to the first and second inner electrodes. At least one of two outer electrodes connected with inner electrodes of each group is different from an outer electrode connected with inner electrodes of a different group having the same polarity, and inner electrodes of one group are connected to outer electrodes connected with at least another one group so that all the inner electrodes belonging to the same polarity can be electrically connected.

Abstract: There are a plurality of types of first internal electrodes and each type of first internal electrode includes a first main electrode portion and a first lead portion. A second internal electrode includes a plurality of second main electrode portions forming respective capacitance components with the respective types of first internal electrodes, an interconnection portion connecting between each pair of second main electrode portions, and a second lead portion. Positions of the first lead portions of the respective types of first internal electrodes are different from each other and distances from the first lead portions of the respective types of first internal electrodes to the second lead portion are different from each other. The width of the interconnection portion is smaller than the width of at least one second main electrode portion out of the plurality of second main electrode portions.

Abstract: A manufacturing method includes forming a dielectric part by oxidizing an entire first surface of a valve metal sheet; forming a through hole in the valve metal sheet in which the dielectric part is formed; applying an adhesive conductive material to a surface of a substrate; attaching the valve metal sheet in which the through hole is formed, to the substrate so that the first surface contacts the conductive material on the substrate surface; forming a conductive layer by curing the conductive material; forming a protection layer which covers a second surface of the valve metal sheet which is opposite to the first surface of the valve metal sheet; forming openings in the protection layer, so that the conductive layer in the through hole and the second surface of the valve metal sheet are partially exposed from the openings; and filling up the openings in the protection layer with another conductive material to form electrode terminals.

Abstract: A multilayer ceramic capacitor includes first internal electrodes extending to a first end surface of a ceramic element assembly, a plurality of second internal electrodes extending to a second end surface, floating internal electrodes arranged so as to overlap the first and second internal electrodes with ceramic layers disposed therebetween to define first and second effective regions, inner conductors that are elongated from the first end surface beyond a region that overlaps the first effective region in the direction of layering, and a relationship X1<Y1<(L?E) is satisfied where L is the dimension in the longitudinal direction extending from the first end surface to the second end surface, X1 is the longitudinal-direction dimension of each of the first internal electrodes, Y1 is the distance between the first end surface and an end of each of the first internal electrodes, and E is the distance between the second end surface and an end of the second extended section.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: An electric multilayer component includes a stack of dielectric layers and electrode layers arranged side by side. External contacts have different polarities that are arranged at an outer surface of the stack and are flip-chip contact-connectable. The electrode layers are connected by one end in each case to an external connection having the same polarity.

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally toward the ground plane, and a ground plane extension that extends from the ground plane generally toward the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract: A multilayer capacitor which can prevent chattering noises from occurring and improve the packaging density and packaging yield, and a method of manufacturing a multilayer capacitor are provided. Even when an electrostrictive vibration is generated in this multilayer capacitor upon voltage application, a joint surface of a metal terminal can flex, so as to mitigate the electrostrictive vibration, thereby preventing chattering noises from occurring. The joint surface is formed with a cutout and thus can fully secure its flexibility. In this multilayer capacitor, a step formed by a terminal connecting surface, a substrate connecting surface, and the joint surface is positioned within an area overlapping a capacitor element body as seen in the laminating direction of dielectric layers. Therefore, solder fillets do not protrude out of the capacitor element body, whereby the packaging density on a mounting substrate K can be improved.

Abstract: Multilayer capacitors incorporate both low inductance (ESL) and controlled Equivalent Series Resistance (ESR) features into a cost-effective unitary device. Internal electrode patterns generally include one or more pairs of mother electrodes adapted for external connection (e.g., to a circuit, another electrical component, circuit board, or other mounting environment), and multiple pairs of daughter electrodes adapted only for internal connection to other electrodes (e.g., other daughter electrodes and/or selected mother electrodes) without direct connection to an external circuit. Mother and daughter electrodes are interdigitated with electrode tab features, where daughter electrodes have internal-connection tabs, and mother electrodes have both internal-connection tabs and circuit-connection tabs, all of which are connected to respective internal-connection or circuit-connection terminals.

Abstract: A method for manufacturing a multilayer electronic component includes a step of preparing a laminate which includes a plurality of stacked insulator layers and a plurality of internal electrodes extending along the interfaces between the insulator layers, and in which an end of each of the plurality of internal electrodes is exposed at a predetermined surface corresponding to one of the first and second end surfaces; a step of forming external electrodes on the predetermined surfaces; and a step of forming thick-film edge electrodes at edge portions. The step of forming external electrodes includes a step of attaching a plurality of conductive particles having a particle size of about 1 ?m or more to the predetermined surfaces of the laminate, and a step of performing plating directly on the predetermined surfaces to which the conductive particles are attached.

Abstract: A semiconductor device incorporating a capacitor and a method of fabricating the same include a first inter-layer dielectric film formed on a semiconductor substrate, a first electrode pattern formed on the first inter-layer dielectric film, and a capacitor region self-aligned to the first electrode pattern and in which the first inter-layer dielectric film is etched. An MIM capacitor is conformably formed on the sidewall of the first electrode pattern in the capacitor region. In the capacitor region, a first hollow region is formed enclosed by the MIM capacitor and a second electrode pattern fills the first hollow region. The second electrode pattern has a sidewall opposite to the sidewall of the first electrode pattern. The MIM capacitor is conformably formed in the capacitor region that is deepened more than a thickness of an interconnection layer, so that it has a capacitor area wider than an area contacting with the interconnection layer.

Abstract: A multilayer ceramic capacitor having external electrodes. Each of the external electrodes has a lower layer resistance electrode and an upper layer conductive electrode. A glass contained in the upper layer conductive electrode has a softening point higher than that of a glass contained in the lower layer resistance electrode by 20° C. or more.

Abstract: The present invention is intended to solve the problem of a conventional thermosetting conductive paste with respect to bonding-property between an internal electrode(s) and an external electrode(s) so as to provide a multilayer ceramic electronic part suitable for its mounting on a substrate and for its plating-treatment. The present invention relates to a multilayer ceramic electronic part, characterized in that it has an external electrode(s) formed from a thermosetting conductive paste comprising conductive particles having a high melting point, metal powder having a melting point of 300° C. or less and a resin(s).

Abstract: A region where a plating film constituting an external electrode is formed can be accurately controlled in an electronic component in which the external electrode is formed by directly plating a particular region in a surface of a component body. In a component body, a bump is provided in a position in which a region where an external electrode should be formed is partitioned. In a plating process, growth of the plating film constituting the external electrode is substantially stopped or delayed in the bump. As a result, a termination point of the growth of the plating film constituting the external electrode can be accurately controlled in the position of the bump.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.

Abstract: In a laminated ceramic electronic component in which, by directly carrying out a plating process on an outer surface of a component main body, an external electrode is formed thereon, an attempt is made to improve the adhesion strength between a plated film forming the external electrode and the component main body. A brazing material containing Ti is applied to at least one portion of a surface on which external electrodes of a component main body is formed, and by baking this brazing material, a metal layer containing Ti is formed. Moreover, the external electrodes are formed by a plating process so as to coat at least the metal layer, and a heating process is then carried out so as to cause counter diffusion between the metal layer and the plated film that is to form the external electrodes.

Abstract: In a capacitor body, a single second capacitor unit is interposed between two first capacitor units. The width direction dimension of each of extended portions of first and second internal electrodes included in the first capacitor unit is larger than the width direction dimension of each of extended portions of third and fourth internal electrodes included in the second capacitor unit. The area of each of the respective portions of a first opposed portion of the first internal electrode and a second opposed portion of the second internal electrode, the respective portions being opposed to each other, is smaller than the area of each of respective portions of opposed portions of the third and fourth internal electrodes, the respective portions being opposed to each other. Thus, a multilayer capacitor has a characteristic that is a combination of a low-ESL characteristic of the first capacitor unit and a high-ESR characteristic of the second capacitor.

Abstract: A low-inductance capacitor exhibits a first characteristic inductance during use in a first capacitor subsection and a second characteristic inductance during use in a second capacitor subsection, and the first and second characteristic inductances act to neutralize each other. A process of forming the low-inductance capacitor includes heat curing. A package includes a low-inductance capacitor and a mounting substrate.

Abstract: A circuit device capable of suppressing reduction of reliability resulting from heat generated in a circuit element is obtained. This circuit device comprises a first insulating layer having a first opening and a second opening, a first conductor filling up the first opening of the first insulating layer, a second conductor, formed along the inner side surface of the second opening of the first insulating layer, having a concave upper surface and a circuit element arranged above a region of the first insulating layer formed with the first opening.

Abstract: In a ceramic electronic component having a thin structure, the occurrence of cracks due to stress applied when the ceramic component is being mounted or in a mounted state are prevented. Each of first and second external terminal electrodes has a substantially rectangular region on a principal surface of a ceramic element body, the principal surface being directed to the mounting surface side. An end of the first external terminal electrode, which is arranged in contact with a gap region, and an end of the second external terminal electrode, which is positioned in contact with the gap region, each preferably have a concave-convex shape on the principal surface.

Abstract: Metal-insulator-metal capacitors are provided that are formed in integrated circuit dielectric stacks. A line-plate-line capacitor is provided that alternates layers that contain metal plates with layers that contain straight or angled parallel lines of alternating polarity. A segmented-plate capacitor is provided that has metal plates that alternate in polarity both within a layer and between layers. The line-plate-line and segmented-plate capacitors may exhibit a reduced parasitic inductive coupling. The capacitances of the line-plate-line capacitor and the metal-insulator-metal capacitor may have an enhanced contribution from an interlayer capacitance component with a vertical electric field than a horizontal intralayer capacitance component with a horizontal electric field.

Abstract: In a laminated ceramic electronic component, external terminal electrodes include plating films directly covering exposed portions of internal electrodes on end surfaces of a ceramic element assembly. On the boundaries between the end surfaces and principal surfaces of the ceramic element assembly, substantially rounded corners are provided, and the plating films are arranged such that the ends of the plating films stop at the corners and do not project from the principal surfaces.

Abstract: A method is provided for testing a built-in component including multiple terminals in a multi-layered circuit board. At least one signal pad is provided on a top surface of the multi-layered circuit board for signal transmission. Each of the signal pads are electrically connected to one of the multiple terminals. At least one test pad is provided on the top surface of the multi-layered circuit board and each of the test pads is electrically connected to one of the multiple terminals. Then, detection occurs regarding one of the signal pads and one of the test pads that are electrically connected to a same one of the multiple terminals in order to determine a connection status of an electric path extending from the one signal pad through the same one terminal to the one test pad.

Abstract: A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a metal element concentration which is disproportionate relative to concentrations of the element within metal alloy layers on either side of the metal-oxide layer. A method includes forming a BL upon a BMF such that portions of a first DL adjacent to the BMF are exposed, selectively depositing a second DL upon the BL, cleaning the topography thereafter, and blanket depositing a third DL upon the cleaned topography. Another method includes polishing a microelectronic topography such that a metallization layer is coplanar with a DL and further includes spraying a deionized water based fluid upon the polished topography to remove debris from the DL.

Abstract: An electrical component includes ceramic layers that are stacked to form a base body, electrode layers among the ceramic layers to form at least one capacitor, at least one phase gate on a ceramic layer that corresponds to a surface of the base body, contact surfaces on a top surface of the base body, and through contacts that electrically connect the electrode layers to the contact surfaces. The through contacts are inside the base body at least in part. Side surfaces of the base body are substantially free of surface metallic contacts and of metal plating.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a second direction perpendicular to the third face, is arranged with a gap in a third direction perpendicular to the second directions so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

Abstract: A humidity sensor apparatus and method of forming the same. A substrate can be provided upon which a plurality of humidity sensing components are disposed to form a humidity sensor thereof. Each humidity sensing component generally includes an associated particular parasitic capacitance. This parasitic capacitance is utilized to reduce and/or control a sensitivity and a total capacitance value associated with the humidity sensor without increasing a size of the humidity sensor and/or humidity sensor components (e.g., capacitors).

Abstract: A capacitor comprises m electrode plates that are arranged spaced apart and in parallel, where m is an integer greater than one. Even ones of the m electrode plates comprise x extensions that extend from the first side and that have a first width. Odd ones of the m electrode plates comprise y extensions that extend from the first side and that have a second width that is less than the first width. The x extensions are located between the y extensions when the m electrode plates are arranged in parallel. n first external terminals that are arranged on a first exterior surface of the capacitor. The x extensions are coupled to x of the n first external terminals and wherein the y extensions of the odd ones of the m electrode plates are coupled to y of the n first external terminals.

Abstract: A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a third direction perpendicular to the third face, is arranged with a gap in the second direction so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

Abstract: A multilayer chip capacitor includes: a capacitor body having a plurality of dielectric layers laminated therein and comprising first and second capacitor units; and first to fourth external electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the first and second external electrodes, and having different polarities, each pair of first and second internal electrodes being laminated one or more times to discriminate a plurality of capacitors with a certain capacitance, the second capacitor unit comprises third and fourth internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the third and fourth external electrodes, and having the same polarities as those of the first and second internal electrodes, each pair of third and fourth internal electrodes being laminated one or more times to discriminate

Abstract: A laminated chip varistor comprises a varistor body, first and second inner electrodes, a heat conductor, and first and second outer electrodes. The varistor body has first and second outer faces. The first and second inner electrodes are disposed in the varistor body so that at least portions thereof are opposing to each other. The first and second outer electrodes are formed on the first outer face, the first outer electrode being connected to the first inner electrode, and the second outer electrode being connected to the second inner electrode. The heat conductor is formed in the varistor body extending in a direction from the first outer face toward the second outer face with one end face thereof exposed on the first outer face and the other end face thereof exposed on the second outer face.

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device.

Abstract: A multilayer capacitor which can inhibit impedance from decreasing near a resonance frequency is provided. The multilayer capacitor comprises a dielectric matrix, a plurality of first and second inner electrodes, a pair of terminal electrodes, and a pair of linking electrodes. The first inner electrode has a first region located closer to a first terminal connection part than is a portion provided with a first linking connection part and a second region located closer to an opposite side of the first terminal connection part than is the portion provided with the first linking connection part. The second inner electrode has a third region located closer to a second terminal connection part than is a portion provided with a second linking connection part and a fourth region located closer to an opposite side of the second terminal connection part than is the portion provided with the second linking connection part.

Abstract: A multilayer chip capacitor includes: a capacitor body having a plurality of dielectric layers laminated therein and comprising first and second capacitor units; and first to fourth external electrodes formed on an outer surface of the capacitor body, wherein the first capacitor unit comprises first and second internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the first and second external electrodes, and having different polarities, each pair of first and second internal electrodes being laminated one or more times to discriminate a plurality of capacitors with a certain capacitance, the second capacitor unit comprises third and fourth internal electrodes facing each other with the dielectric layer interposed therebetween, connected to the third and fourth external electrodes, and having the same polarities as those of the first and second internal electrodes, each pair of third and fourth internal electrodes being laminated one or more times to discriminate

Abstract: A varistor comprises a varistor element body, first and second inner electrodes opposing each other, a first outer electrode connected to the first inner electrode physically and electrically, a second outer electrode connected to the second inner electrode physically and electrically, and an electrically insulating layer. The first and second inner electrodes are arranged within the varistor element body so as to have end portions exposed at two outer surfaces of the varistor element body. The first outer electrode is arranged on one of the two outer surfaces so as to cover a portion of the end portion of the first inner electrode exposed at the one outer surface. The second outer electrode is arranged on the one outer surface so as to cover a portion of the end portion of the second inner electrode exposed at the one outer surface.

Abstract: A method of manufacturing a multilayer capacitor comprises a first layer forming step, a first electrode forming step, a second layer forming step, a second electrode forming step, a separation step, an element forming step and a terminal forming step. In the first layer forming step, a first ceramic green layer is formed on a supporting body. In the first electrode forming step, a first electrode pattern is formed on the first ceramic green layer. In the second layer forming step, a second ceramic green layer is formed laminated on the first ceramic green layer. In the second electrode forming step, a second electrode pattern is formed at the second ceramic green layer. In the separation step, the support body is separated from the laminated body. In the element forming step, elements are formed by laminating a plurality of the laminated bodies.

Abstract: A multi-layer capacitor includes several electrically insulating layers that are stacked on top of one another. Parallel electrode plates are arranged between the insulating layers alternately one on top of the other, with each of the plates being separated by an intervening insulating layer. At least one first connecting line which extends perpendicularly through the layers is connected to one set of electrode plates and is insulated in relation to the other set of second electrode plates. Similarly, second connecting lines extend perpendicularly through the layers and are connected to the other set of plates and are insulated in relation to the one set of plates. The first connecting line extends centrally through the stacked electrode plates and is designed to carry a high-frequency signal.

Abstract: A circuit board including: a substrate having a mounting area for mounting a vertical multilayer chip capacitor having first and second external electrodes of a first polarity and a third external electrode of a second polarity; first to third pads arranged on the mounting area, the first and second pads having the first polarity and disposed separately from each other on the mounting area, the third pad having the second polarity and disposed between the first and second pads to be connected to the third external electrode; at least one first via formed in the substrate and connected to the first pad; at least one second via formed in the substrate and connected to the second pad; and a plurality of third vias formed in the substrate and connected to the third pad.

Abstract: A ceramic electronic component that is hardly influenced by a stress generated when an external electrode containing a metal sintered compact is formed at the end of the ceramic component body, and a method for manufacturing the same are provided. A laminated ceramic capacitor includes a ceramic component body and first electrodes to be connected to internal electrodes that are led to the end surfaces are formed. The first external electrodes are arranged so that the ends are spaced apart from the side surfaces of the ceramic component body. Second external electrodes containing a conductive resin are arranged so as to entirely cover the first electrodes and first and second metal layers and are formed thereon. The first external electrodes are formed by supplying a conductive paste containing conductive metal powder and glass frit having a softening point higher than the sintering starting temperature of the conductive metal powder, and heating the same.

Abstract: A method of manufacturing a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board manufactured by the method of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon.

Abstract: There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.

Abstract: There is provided a multilayer capacitor including an inner connecting conductor of at least one polarity; a plurality of first and second outer electrodes formed on a surface of the body, wherein the inner connecting conductor is connected to a corresponding one of the outer electrodes having identical polarity, a corresponding one of the inner electrodes having identical polarity to the inner connecting conductor includes a plurality of groups each including at least one of the inner electrodes, wherein the inner electrodes of the respective groups are connected to the outer electrodes having identical polarity that are different from one another for each of the groups and electrically connected to the inner connecting conductor through the connected outer electrode.

Abstract: A multilayer capacitor array includes a capacitor body having rectangular first and second main faces opposing each other. In the capacitor body having a dielectric characteristic, first inner electrodes are arranged in a first region, second inner electrodes are arranged in a second region, and third and fourth inner electrodes are arranged so as to extend over the first and second regions. Each of the third inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. Each of the fourth inner electrodes opposes at least one of the first inner electrodes and at least one of the second inner electrodes. The third inner electrodes are adjacent to the fourth inner electrodes, respectively.

Abstract: A capacitor device mountable on a plane of a substrate includes an electrically conductive bottom plate adapted to be mounted substantially parallel to, and in electrical contact at the plane of the substrate and a first multilayer capacitor having substantially parallel first and second electrode plates oriented substantially perpendicular to the bottom plate with the first electrode plates being electrically connected to the bottom plate. An electrically conductive top lead frame overlaps with, and is electrically isolated from, the bottom plate. The top lead frame electrically connected to the second electrode plates and adapted to be electrically connected at the plane of the substrate. The bottom lead frame may have a corrugated shape, where the corrugated shape provides compliance between the first multilayer capacitor and the substrate. A portion of the top lead frame may contact at least a portion of a side of the first multilayer capacitor.

Abstract: A component-embedded substrate includes a chip capacitor. The chip capacitor includes a ceramic laminate body and a plurality of terminal electrodes. The component-embedded substrate has a first principal surface and a second principal surface. At least two of the plurality of terminal electrodes are connected to the first principal surface and define a first terminal electrode group, and at least two of the plurality of terminal electrodes are connected to the second principal surface and define a second terminal electrode group. One terminal electrode in the first terminal electrode group is electrically connected to one terminal electrode in the second terminal electrode group via the internal electrodes, and capacitance is provided by a pair of the terminal electrodes in the first terminal electrode group via the dielectric layer, and capacitance is provided by a pair of the terminal electrodes in the second terminal electrode group via the dielectric layer.

Abstract: A capacitor having improved surface breakdown voltage performance and a method for applying laser marking to capacitors which does not reduce capacitor surface breakdown voltage, can be applied using existing laser marking technologies and apparatus, and which results in a mark that is legible and clear, is disclosed. In a first exemplary embodiment a capacitor includes a laser mark which is located near one of the capacitor terminals. The exact location is not critical as long as the mark does not make physical contact with the terminal. Conventional laser marking technologies and apparatus may be used to fix the mark in the new location. In a second embodiment the laser mark is oriented so that a flat portion of the mark is is oriented closest to the adjacent terminal.

Abstract: A multilayer capacitor has a laminate body in which a first internal electrode and a second internal electrode are alternately laminated with a dielectric layer in between, a first terminal electrode provided on one end side of the laminate body, and a second terminal electrode provided on the other end side of the laminate body. The first internal electrode has a first lead portion connected to the first terminal electrode. The second internal electrode has a second lead portion connected to the second terminal electrode. The first internal electrode consists of plural types of first internal electrodes and the plural types of first internal electrodes have their respective first lead portions at different positions. Distances between the first lead portions of the respective types of the first internal electrodes and the second lead portion are different from each other.