Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A laminated ceramic capacitor includes a body having an inner layer portion and an outer layer portion and a plurality of terminal electrodes spaced apart from each other in a length direction of the body. The inner layer portion has a plurality of internal electrodes stacked in a height direction of the body. The internal electrodes have led-out portions led out to a side face of the body. The outer layer portion is disposed on one of opposite faces of the inner layer portion in the height direction. The terminal electrodes are each provided with a connecting portion and a spreading portion. The connecting portion extends along the height direction to cover corresponding one of the led-out portions. The spreading portion has a width gradually increasing from one of opposite ends of the connecting portion in the height direction toward an edge of the side face.

Abstract: A laminated capacitor includes: a dielectric body; first terminal electrodes arranged at intervals on one surface of the dielectric body; second terminal electrodes arranged at intervals on the surface of the dielectric body; first internal electrodes arranged in layers within the dielectric body; second internal electrodes arranged in layers within the dielectric body to alternate with the first internal electrodes; first outer through-hole conductors each connecting each first terminal electrode to one first internal electrode which is located closest to the surface of the dielectric body among the first internal electrodes; second outer through-hole conductors each connecting each second terminal electrode to one second internal electrode which is located closest to the surface of the dielectric body among the second internal electrodes; a first inner through-hole conductor connecting the first internal electrodes to one another; and a second inner through-hole conductor connecting the second internal elec

Abstract: A monolithic capacitor includes a main capacitor unit having first capacitor portions and a second capacitor portion arranged in a direction of lamination, with the first capacitor portion located towards at least one end in the direction of lamination, so that the first capacitor portion is located closer to a mounting surface than the second capacitor portion. The number of pairs of third and fourth lead-out portions for third and fourth internal electrodes in the second capacitor portion is less than the number of pairs of first and second lead-out portions for first and second internal electrodes in the first capacitor portion, so that the first capacitor portion contributes to decreasing ESL while the second capacitor portion contributes to increasing ESR.

Abstract: A multilayer capacitor comprises a ceramic sintered body, an internal electrode disposed in the ceramic sintered body, and an external electrode disposed on an external surface of the ceramic sintered body. The external electrode has a first electrode layer formed on the external surface of the ceramic sintered body, a second electrode layer formed on the first electrode layer, and a conductive resin layer formed on the second electrode layer. The internal electrode and the first electrode layer consist primarily of a base metal. The second electrode layer consists primarily of a noble metal or a noble metal alloy. The conductive resin layer contains a noble metal or a noble metal alloy as a conductive material.

Abstract: A laminated ceramic capacitor including a capacitor body where internal electrodes and a dielectric layer are alternately laminated, and external electrodes are provided on the end faces thereof. In this capacitor body, high resistance layers are provided between the internal electrodes and dielectric layer. These high resistance layers contain a ceramic material, an element including at least one selected from Mn, Cr, Co, Fe, Cu, Ni, Mo and V, and/or a rare earth element.

Abstract: A multilayer capacitor includes a multilayer body in which dielectric layers and inner electrodes are alternately laminated, and terminal electrodes formed on the multilayer body. The inner electrodes include first inner electrodes and second inner electrodes alternately arranged. The terminal electrodes include at least three terminal electrodes. The first inner electrodes are electrically connected to each other via a through-hole conductor. The second inner electrodes are electrically connected to each other via a through-hole conductor. At least two first inner electrodes in the first inner electrodes are electrically connected via a lead conductor to at least two respective terminal electrodes whose number is smaller than the total number of the terminal electrodes by at least 1 in the at least three terminal electrodes.

Abstract: Internal electrode layers are superimposed in a dielectric substrate 1 at intervals. Step absorption layers are respectively provided on lateral sides of the internal electrode layers. A side portion of the internal electrode layer forms an inclined surface, and the step absorption layer is superimposed so as to partially overlap the inclined surface of the internal electrode layer. This is also applied to the other internal electrode layers and step absorption layers.

Abstract: This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

Abstract: A multi-layer chip capacitor includes a capacitor body; first and second internal electrodes alternately arranged therein and separated by dielectric layers, each of the internal electrodes having at least one opening formed at one or more sides thereof; first and second conductive vias passing through the openings and electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes of opposite polarities formed on one or more side faces of the capacitor body; and first and second lowermost electrode patterns being coplanar, each pattern including a via contact portion and a lead portion extending therefrom. The first and second lowermost electrode patterns are connected to the first and second terminal electrodes, respectively, through the respective lead portions of the lowermost patterns.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and a plurality of outer conductors (first and second terminal conductors, and first and second outer connecting conductors) formed on the multilayer body. Each of the outer conductors is formed on one of two side faces of the multilayer body opposing each other. Each of the first and second inner electrodes is electrically connected to the corresponding outer connecting conductor. At least one inner connecting conductor layer including a first and a second inner connecting conductors is laminated in the multilayer body. Each of the inner connecting conductors is electrically connected to the corresponding terminal and outer connecting conductors. The equivalent series resistance of the multilayer capacitor is set to a desirable value by adjusting the number or position of inner connecting conductor layer.

Abstract: A capacitor with conductive layers arranged in parallel relationship. The conductive layers have nickel alloyed or add mixed with a refractory metal in an amount sufficient to raise the melting temperature of said conductive layer at least 1° C. above the melting temperature of nickel. A dielectric layers is between the conductive layers. Alternating layers of said conductive layers are in electrical contact with external terminations of opposing polarity.

Abstract: An objective is to provide a multilayer filter capable of preventing an electric current rapidly flowing by virtue of varistor effect, from passing as noise, upon application of noise of a high voltage over a varistor voltage to its input. A multilayer filter has an inductor part 10 and a varistor part 20 in a laminate 2, and the inductor part 10 has the DC resistance of 4 ?-100 ?. This prevents an electric current rapidly flowing by virtue of the varistor effect, from passing as noise, upon application of noise of a high voltage over the varistor voltage to the input.

Abstract: The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

Abstract: The capacitor 10 (laminated ceramic capacitor) of the invention comprises a capacitor body 11 wherein internal electrodes 12 (electrodes) and a dielectric layer 14 are alternately laminated, and external electrodes 15 are provided on the end faces thereof. The dielectric layer 14 has a site containing particles of a dielectric material which is formed of only one of these particles in its thickness direction. Regions 24 comprising at least one element selected from a group comprising Si, Li and B are scattered between the internal electrodes 12 and dielectric layer 14.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A method for manufacturing a capacitor includes the steps of: forming a lanthanum nickelate layer above a base substrate; forming a dielectric layer above the lanthanum nickelate layer; forming a conductive layer above the dielectric layer; and patterning at least the dielectric layer until the lanthanum nickelate layer is exposed.

Abstract: Thin-film capacitors are formed on ceramic substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are annealed at high temperatures.

Abstract: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The first coil and the second coil are electrically connected in series to form a spiral coil. The coil portion composed of a ferrite ceramic having a small number of pores has a high permeability and a high dielectric constant, and the coil portion composed of a ferrite ceramic having a large number of pores has a low permeability and a low dielectric constant.

Abstract: A semiconductor device having the thin film capacitor includes a first electrode formed on a substrate, a capacitor insulating film containing a laminated film, which is constructed by laminating an amorphous dielectric film and a polycrystalline dielectric film via a wave-like interface, on the first electrode, and a second electrode formed on the capacitor insulating film.

Abstract: A novel multi-capacitor divider network in which two capacitors are fabricated in a single package, using a common dielectric material, is disclosed. In a preferred embodiment of the present invention, the multi-capacitor network comprises a high-voltage capacitor and a low-voltage capacitor fabricated in a single monolithic package, both fabricated from a class one dielectric material having a combined tolerance of plus or minus five percent. The use of the same class one dielectric material for both capacitors assures that the temperature coefficents are similar for both capacitors and, more importantly, that the tolerance of the ratio between the high-voltage capacitor and low-voltage capacitor is within a predetermined range.

Abstract: A dielectric ceramic is obtained by the steps of obtaining a reaction product composed of a barium titanate base composite oxide represented by the general formula (Ba1?h?i?mCahSriGdm)k(Ti1?y?j?nZryHfjMgn)O3, in which 0.995?k?1.015, 0?h?0.03, 0?i?0.03, 0.015?m?0.035, 0?y<0.05, 0?j<0.05, 0?(y+j)<0.05, and 0.015?n?0.035 hold; mixing less than 1.5 moles of Ma (Ba or the like), less than 1.0 mole of Mb (Mn or the like), and 0.5 to 2.0 moles of Mc (Si or the like) with respect to 100 moles of the reaction product; and firing the mixture thus obtained. This dielectric ceramic has superior humidity resistance, satisfies the F characteristic of the JIS standard and the Y5V characteristic of the EIA standard, has a relative dielectric constant of 9,000 or more, and has superior high-temperature reliability.

Abstract: A multilayer capacitor has a multilayer body, and first and second terminal electrodes. In the multilayer body first and second internal electrode are laminated with a dielectric layer in between. The first internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The second internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The first internal electrode is electrically connected to the first terminal electrode, and the second internal electrode to the second terminal electrode.

Abstract: A method of forming a ceramic structure includes disposing substrate-forming ceramic green sheets having conductors, internal conductors, and via conductors so as to sandwich connecting member-forming ceramic green sheets having via conductors, followed by lamination and bonding thereof by pressure application, with the conductors being formed using a conductive paste primarily composed of a powdered metal, so that a ceramic laminate composed of ceramic molded bodies laminated to each other is formed. The ceramic laminate is fired at a temperature at which the substrate-forming ceramic green sheets are sintered and the connecting member-forming ceramic green sheets are not sintered and at a temperature not more than the melting point of the metal, and subsequently, the connecting member-forming ceramic green sheets are removed from the fired composite laminate, thereby forming a ceramic structure.

Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.

Abstract: A multi-layer printed wire board (PWB) structure optimized for improved drop reliability, reliable electrical connections under thermal load, and minimal thickness is provided, along with a mobile terminal, including the PWB. The PWB includes alternating conductive layers and insulative layers. The outermost three layers form an interconnect structure constructed of two conductive layers surrounding an insulative-coated conductive layer. The thicknesses of the various layers are optimized to have an increased resistance to mechanical shock resulting from, for instance, a drop onto a hard surface. In addition, the optimized PWB structure has a minimized thickness and an improved resistance to connection failures resulting from cyclical thermal loads.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: A capacitor with reduced equivalent series resistance and reduces equivalent series inductance is provided. Capacitors are provided with multiple plate assemblies that couple to a common single first polarity terminal. Capacitors are also provided with multiple plate assemblies that each couple to a respective second polarity terminal. Fan-like plate assemblies are arranged to provide increased capacitance with reduced equivalent series resistance and reduces equivalent series inductance. Capacitors are provided that mount using surface mounting technology. Capacitors are provided that conform to existing capacitor form factors.

Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

Abstract: Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: A capacitor is provided having a structure in which an insulation film is interposed between a first electrode and a second electrode. The insulation film includes SrTiO3 as a main component, and at least one of Si and Ge added thereto.

Abstract: A structure and method are provided for reducing the equivalent series resistance of a capacitor. A capacitor includes one or more conductive interconnections contacting an active region of a first conductive plate of the capacitor at a plurality of locations along a lengthwise direction, such that every portion of the active region of the first conductive plate lies within a maximum distance from one of the locations, the maximum distance being less than the lateral dimension of the active region.

Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.

Abstract: A high voltage capacitor design is provided that provides improved performance. The high voltage capacitor includes a stack of mechanically joined capacitor cells, which in one variant utilize a separator formed of two layers of paper. In one version, the high voltage capacitor may be used as a capacitative voltage divider.

Abstract: A multilayer chip varistor comprises a multilayer body and a pair of external electrodes formed on the multilayer body. The multilayer body has a varistor section and a pair of outer layer sections disposed so as to interpose said varistor section. The varistor section comprises a varistor layer developing a voltage nonlinear characteristic and a pair of internal electrodes disposed so as to interpose the varistor layer. The pair of external electrodes are connected to respective electrodes of the pair of internal electrodes. The relative dielectric constant of the outer layer sections is set lower than the relative dielectric constant of the region where the pair of internal electrodes in the varistor layer overlap each other.

Abstract: An electrical feedthrough assembly according to the invention can be used as a component of an implantable medical device (IMD) and/or or electrochemical cell. An IMD includes implantable pulse generators, cardioverter-defibrillators, physiologic sensors, drug-delivery systems, etc. Such assemblies require biocompatibility and resistance to degradation under applied bias current or voltage. In some forms of the invention, such assemblies are fabricated by using electrically common, multiply-interconnected electrical pathways including metallized vias and interlayer structures of conductive metallic material within bores and between ceramic layers. The layers are stacked together and sintered to form a substantially monolithic dielectric structure with at least one electrically common embedded metallization pathway extending through the structure.

Abstract: A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.

Abstract: In one aspect of the invention, in a thin layer capacitor element comprising a capacitor having a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.

Abstract: A method of producing a multilayer microelectronic substrate, in which: a) a number of thermally combinable films with a first compression temperature are provided; b) at least one film with a second compression temperature, which lies above the first compression temperature, is provided; c) at least one of the films with the second compression temperature is arranged between films with the first compression temperature; d) the laminated films are heated to the first compression temperature, and further to a first end-temperature until the films with the first compression temperature are completely compressed, the first end-temperature being kept below the second compression temperature; and e) the laminated films are heated to the second compression temperature and, if applicable, further to a second end-temperature in order to compress the at least one film with the second compression temperature, characterized in that at least one of the films is made from magnetodielectric material, with nickel oxide N

Abstract: A decoupling module for decoupling high-frequency signals from A power supply line, the module including a layer (30) of dielectric material which is arranged between a first and a second metallic layer (20, 22), where the first metallic layer (20) is connected as a ground electrode of the decoupling module and the second metallic layer (22) includes at least two surfaces of different size which are consecutively electrically connected between an input connection point and an output connection point, while two respective consecutive surfaces are connected to each other by only one conducting section.

Abstract: An electroceramic component includes a base body, contact layers on the base body, a dielectric layer in the base body that includes a single-phase perovskite ceramic having a composition of Ag(Nb1-xTax)O3, and an electrode layer in the base body containing a precious metal. The electrode layer is sintered with the dielectric layer.

Abstract: A capacitor has at least one plate of a first polarity and at least two plates of a second polarity, with a terminal electrically connected to the at least two plates of the second polarity such that the electrical plate connections are remote from an edge of the connected plates.

Abstract: A feedthrough terminal assembly for an active implantable medical device utilizes an insert to establish a reliable electrical connection between capacitor electrode plates, via inner surface metallization of a capacitor aperture, and an associated terminal pin 10, which passes at least partially therethrough. The inserts are preferably resiliently flexible, such as a spring, to establish this connection. The insert also serves to establish a mechanical connection between the capacitor and the terminal pin.

Abstract: An electrical component includes a ceramic base body having at least four contact surfaces. Two of the contact surfaces are on opposite sides of the ceramic base body. First protective layers are arranged on regions of the opposite sides of the ceramic base body that do not include the contact surfaces. The first protective layers have a composition that allows the first protective layers to be sintered at a higher temperature than the contact surfaces. Second protective layers are arranged on at least two opposite surfaces of the ceramic base body. The ceramic base body, the first protective layers, and the second protective layers are sintered together.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.