Abstract: A substrate has a base, an intermediate layer, a conductive layer, and conductive films. The base is a ceramic insulator. The intermediate layer is on a main surface of the base. The conductive layer is on the intermediate layer. The conductive films are on the conductive layer, covering an exposed portion of the conductive layer.

Abstract: A system for detecting tissue contact and penetration depth. The system comprises a needle sheath having a needle sheath inner diameter and a needle sheath outer diameter. A first conductive region is disposed on the needle sheath inner diameter. A needle having a needle insulation layer on the outer diameter upon which a second conductive region is disposed within the first conductive region. A dielectric layer is disposed between the first conductive tube and the second conductive tube. A capacitance sensor is coupled to the first conductive region and the second conductive region.

Abstract: A method of forming a ceramic structure includes disposing substrate-forming ceramic green sheets having conductors, internal conductors, and via conductors so as to sandwich connecting member-forming ceramic green sheets having via conductors, followed by lamination and bonding thereof by pressure application, with the conductors being formed using a conductive paste primarily composed of a powdered metal, so that a ceramic laminate composed of ceramic molded bodies laminated to each other is formed. The ceramic laminate is fired at a temperature at which the substrate-forming ceramic green sheets are sintered and the connecting member-forming ceramic green sheets are not sintered and at a temperature not more than the melting point of the metal, and subsequently, the connecting member-forming ceramic green sheets are removed from the fired composite laminate, thereby forming a ceramic structure.

Abstract: A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.

Abstract: A dielectric capacitor having self healing properties is disclosed. The capacitor includes a film made of an amorphous aromatic copolycarbonate having a weight average molecular weight of at least 10,000 and a glass transition temperature of at least 160° C. In a preferred embodiment the copolycarbonate includes structural units derived from bisphenol TMC. Also disclosed is a process for making the film.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelectricity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A capacitor structure is fabricated by forming a pattern of first dielectrics over a foil, forming first electrodes over the first dielectrics, and co-firing the first dielectrics and the first electrodes. Co-firing of the dielectrics and the electrodes alleviates cracking caused by differences in thermal coefficient of expansion (TCE) between the electrodes and the dielectrics. Co-firing also ensures a strong bond between the dielectrics and the electrodes. In addition, co-firing allows multi-layer capacitor structures to be constructed, and allows the capacitor electrodes to be formed from copper.

Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.

Abstract: The invention includes a family of miniaturized, hermetic electrical feedthrough assemblies having at least one passive electrical component electrically coupled to a conductive pathway traversing each said assembly which are adapted for implantation within a biological system. The electrical feedthrough assembly according to the invention can be used as a component of an implantable medical device (IMD) such as an implantable pulse generator, cardioverter-defibrillator, physiologic sensor, drug-delivery system and the like. Such assemblies require biocompatibility and resistance to degradation under applied bias current or voltage. Such an assembly is fabricated by interconnected electrical pathways, or vias, of a conductive metallic paste disposed between ceramic green-state material. The layers are stacked together and sintered to form a substantially monolithic dielectric structure with at least one embedded metallization pathway extending through the structure.

Abstract: A stacked capacitor includes a dielectric member, a plurality of internal electrodes, and a plurality of extraction electrodes. The dielectric member is a stacked member formed of stacked dielectric layers and having at least one side surface. The internal electrodes are stacked alternately with the dielectric layers and have first edges positioned near the side surface. Each of the extraction electrodes leads from each first edge to the side surface. Each of the extraction electrodes has a width W on the side surface in a direction orthogonal to the stacking direction and is separated from adjacent extraction electrodes by a distance G on the side surface in the direction orthogonal to the stacking direction. The width W and distance G are set such that 1.2?W/G?4.0.

Abstract: A circuit board includes two planes. A via spans the planes, and an impedance component is placed in the via. The impedance component is coupled to both of the planes. The impedance component provides an impedance between the planes without the use of traces or hand soldering of components.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A capacitor includes a first electrode and a second electrode, and a dielectric layer sandwiched between the first electrode and the second electrode, wherein the dielectric layer includes Pb(ZrxTiyM2)O3 (where M is at least one material selected from Nb, Ta, and V, and x+y+z=1).

Abstract: A capacitor with conductive layers arranged in parallel relationship. The conductive layers have nickel alloyed with a refractory metal in an amount sufficient to raise the melting temperature of said conductive layer at least 1° C. above the melting temperature of nickel. A dielectric layers is between the conductive layers. Alternating layers of said conductive layers are in electrical contact with external terminations of opposing polarity.

Abstract: An electronic component is provided which has a plurality of elements, a pair of terminal parts which are disposed on the element, and an armoring material which covers the elements and a part of the terminal parts. The electronic component has a configuration such that the plurality of elements are disposed in the armoring material at a predetermined interval, and a guiding part for guiding the armoring material toward an opposed region of the element is disposed on opposed surfaces between the elements.

Abstract: A wiring board includes a first conductor formation substrate having a first substrate and a first electrode; a second conductor formation substrate having a second substrate and a second electrode; and a dielectric sandwiched between the first conductor formation substrate and the second conductor formation substrate. The dielectric includes a dielectric film that is not melted during thermo-compression bonding, and an adherent insulator melted during thermo-compression bonding. The surface of the dielectric film is subjected to a treatment to improve wettability. Adherence of the adherent insulator in thermo-compression bonding to the dielectric film is facilitated. The distance between the first electrode and the second electrode is made uniform by interposing the dielectric film between the first and second electrodes. A wiring board ensured as to lifetime and improved in reliability, and a simple method of fabricating such a wiring board are achieved.

Abstract: A storage capacitor includes at least one first electrode adjacent to at least one second electrode, whereby a lateral capacity is formed between these electrodes. The electrodes include stacks of metal parts and connecting contact elements. The second electrodes can be arranged around the first electrodes, and at least some of the second electrodes can be used jointly with adjacent ones of the first electrodes to form adjacent storage capacitors.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: In this laminated ceramic capacitor, a heat radiation conductor is provided on a top face of a rectangular parallelepiped laminated chip where a plurality of first conductor layers and a plurality of second conductor layers are arranged alternatively through each ceramic layer with facing each other. In addition, the heat radiation conductor is connected to the upper edge of each second conductor layer. Therefore, when heat is generated in each first conductor layer and each second conductor layer which play the role of internal electrodes, the heat of each second conductor layer is directly transferred from each second conductor layer to the heat radiation conductor, and is radiated outside from the heat radiation conductor.

Abstract: A capacitive load cell apparatus includes upper and lower capacitor plates and an intermediate dielectric in the form of a synthetic knit spacer material having upper and lower fabric layers interconnected by an array of deflectable synthetic fibers. When occupant weight is applied to the seat, the synthetic fibers deflect to locally reduce the separation between the upper and lower capacitor plates, and the consequent change in capacitance is detected as a measure of the applied weight. The load cell or just the dielectric may be encased in a polymeric sheath to prevent intrusion of foreign matter, and a fluid such as silicone may be dispersed in woven dielectric.

Abstract: A capacitor includes a planar electrode layer which is mounted between a pair of dielectric layers. The electrode layer generally is placed slightly off-center with respect to the dielectric layers so that the electrode layer extends to an end portion of the dielectric layers. One layer of the pair of dielectric layers has a pair of spaced apart contact members, each having a different polarity from the other. The contact members extend onto end portions of the dielectric layers with one of the contact members forming an electrical connection with the electrode layer. The combination of the electrode layer, the dielectric layer on which the contact members are mounted, and the contact member not connected to the electrode layer, allow development of a selected value of capacitance. Providing trimmed contact members as well as controlling their size and spacing allow for convenient preselection of desired operative characteristics of the capacitor.

Abstract: Lead-free and cadmium-free glass composition that is particularly suitable for use in conductive ink applications. The invention includes a capacitor comprising a copper termination, the copper termination is made by firing an ink including a glass component, the glass component may comprise up to about 65 mole % ZnO, up to about 51 mole % SrO, about 0.1 to about 61 mole % B2O3, up to about 17 mole % Al2O3, about 0.1 to about 63 mole % Sio2, up to about 40 mole % BaO+CaO, and up to about 20 mole % MgO.

Abstract: A capacitor structure is provided that includes a substrate, a first group of conducting strips, a second group of conducting strips, a third group of conducting strips, and a fourth group of conducting strips. The capacitor structure can further include a first set of vertical vias, a second set of vertical vias, a third set of vertical vias, and a fourth set of vertical vias.

Abstract: Capacitor material for use in forming capacitors, is disclosed. More specifically, the invention is directed to capacitors formed from this material that have one or more discrete electrodes (314), each electrode (314) being exposed to at least two thicknesses of dielectric material (300). These electrodes (314) are surrounded by wider insulative material (312) such that the material can be cut, or patterned into capacitors having specific values. A single electrode can form a small value capacitor while still providing a larger conductive area for attaching the capacitor to associated circuitry. The thin dielectric (310) can be a tunable material so that the capacitance can be varied with voltage. The tunability can be increased by adding thin electrodes that interact with direct current.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Abstract: A capacitor includes a capacitor main body having a front surface on which a semiconductor device is to be mounted and a rear surface at which the capacitor main body is to be mounted on a first main surface of a circuit substrate, a plurality of internal electrodes disposed within the capacitor main body, and a plurality of via conductors penetrating the capacitor main body between the front surface and the rear surface and electrically connected to the internal electrodes, wherein the capacitor main body has a first dielectric layer located on a side of the capacitor main body closer to the front surface and a second dielectric layer located on a side of the first dielectric layer closer to the rear surface, the second dielectric layer having a higher thermal expansion coefficient and a higher dielectric constant than the first dielectric layer.

Abstract: Structures that provide decoupling capacitance to packaged IC devices with reduced capacitor and via parasitic inductance. A capacitive interposer structure is physically interposed between the packaged IC and the PCB, thus eliminating the leads and vias that traverse the PCB in known structures. A capacitive interposer is mounted to a PCB and the packaged IC is mounted on the interposer. The interposer has an array of lands on an upper surface, to which the packaged IC is coupled, and an array of terminals on a lower surface, which are coupled to the PCB. Electrically conductive vias interconnect each land with an associated terminal on the opposite surface of the interposer. Within the interposer, layers of a conductive material alternate with layers of a dielectric material, thus forming parallel plate capacitors between adjacent dielectric layers. Each conductive layer is either electrically coupled to, or is electrically isolated from, each via.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of fused quartz, an electrode layer formed on the support substrate and formed of a conductive material, a buffer layer formed on the electrode layer and formed of a dielectric material containing a bismuth layer structured compound having a composition represented by Bi4Ti3O12 and having an excellent orientation characteristic so that the bismuth layer structured compound is oriented in the c axis direction, and a dielectric layer formed on the buffer layer and formed of a dielectric material containing a bismuth layer structured compound having a composition represented by SrBi4Ti4O15 and having an excellent orientation characteristic so that the bismuth layer structured compound is oriented in the c axis direction.

Abstract: An electronic device including first, second and third conductor layers respectively arranged as the source, drain and gate electrodes of a field effect transistor, the third conductor layer being capacitively coupled with both the first and second conductor layers but with the second conductor layer to a greater degree than with the first conductor layer, wherein the electronic device is operable as a non-linear capacitor by applying an alternating voltage across the third conductor layer and the first conductor layer whilst leaving the second conductor layer at a floating potential.

Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.

Abstract: Systems and apparatuses for providing a broadband capacitor assembly. One broadband capacitor assembly includes a first capacitor operable to provide a first end of an operational band of frequencies within an operational band of a broadband capacitor assembly. The broadband capacitor assembly also includes a second capacitor coupled in parallel to the first capacitor, the second capacitor operable to provide a second end of the operational band of frequencies within the operational band of the broadband capacitor assembly. A DC block can be provided including a broadband capacitor assembly.

Abstract: A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead extended to one end of the corresponding dielectric layer; a plurality of external terminals formed on the outer surface of the capacitor main body, and respectively connected to the first and second internal electrodes through the leads; and at least one opened region, formed through the inner area of each of the first and second internal electrodes, for branching the flow of current so as to increase the offset quantity of parasitic inductances between the first and second internal electrodes.

Abstract: A storage capacitor having a scattering effect is positioned in a substrate for use in a thin film transistor array loop. The storage capacitor is characterized by having a rough layer overlapped by a medium layer and a passivation layer. The storage capacitor further has a reflective layer with high reflectivity so as to provide the storage capacitor with the scattering effect toward an external light source. A method of manufacturing the storage capacitor by two photolithography processes is also shown.

Abstract: A ceramic multilayer capacitor array having a plurality of capacitors in a surface mount compatible package. The array is constructed from a plurality of first dielectric plates, each of which has a first pattern of electrodes, and a plurality of second dielectric plates, each of which has a second pattern of electrodes. The second pattern of electrodes is substantially identical to the first pattern of electrodes, and is shifted with respect to the first pattern of electrodes. Each of the electrodes has at least one tab portion, which extends to at least one of the side faces of the package. Perpendicularly projecting first and second plates, the tab portions of the electrodes in the first plates are free from the tab portions of the electrodes in the second plates.

Abstract: A multi-layered unit according to the present invention includes a support substrate formed of a material which has conductivity and on which a dielectric material containing a bismuth layer structured compound can be epitaxially grown, at least the surface thereof being oriented in the [001] direction, and a dielectric layer formed by epitaxially growing a dielectric material containing a bismuth layer structured compound on the support substrate and formed of a dielectric material containing a bismuth layer structured compound oriented in the [001] direction.

Abstract: A high dielectric composite material obtained by subjecting submicron particles of an inorganic filler containing a metal as its essential component to an insulating treatment such as a chemical treatment, further subjecting to a surface treatment for improving their compatibility with organic resins, and then dispersing in an organic resin, has a dielectric constant of 15 or above, with its dielectric loss tangent in the frequency region of from 100 MHz to 80 GHz being 0.1 or less, and can therefore be used effectively for multilayer wiring boards and module substrates.

Abstract: Described herein is a method for producing a haze-free (Ba, Sr)TiO3 (BST) film, and devices incorporating the same. In one embodiment, the BST film is made haze-free by depositing the film with a substantially uniform desired crystal orientation, for example, (100), preferably by forming the film by metal-organic chemical vapor deposition at a temperature greater than about 580° C. at a rate of less than about 80 ?/min, to result in a film having about 50 to 53.5 atomic percent titanium. In another embodiment, where the BST film serves as a capacitor for a DRAM memory cell, a desired {100} orientation is induced by depositing the bottom electrode over a nucleation layer of NiO, which gives the bottom electrode a preferential {100} orientation. BST is then grown over the {100} oriented bottom electrode also with a {100} orientation. A nucleation layer of materials such as Ti, Nb and Mn can also be provided over the bottom electrode and beneath the BST film to induce smooth, haze-free BST growth.

Abstract: The invention relates to a thin film capacitor containing (a) a substrate, (b) a first polymeric film comprising an electrically conductive polymer located on the substrate, (c) a pentoxide layer selected from the group consisting of tantalum pentoxide, or niobium pentoxide, and mixtures thereof, (d) a second polymeric film comprising an electrically conductive polymer located on the pentoxide layer.

Abstract: A multilayer capacitor includes a multilayer body as a main body of the multilayer capacitor, in which a plurality of internal electrodes and stacked dielectric layers each interposed between the internal electrodes are disposed, being stacked in a stack direction, and dielectrics are disposed on an outer periphery side of the plural internal electrodes, wherein: a pair of upper and lower margin portions in which no internal electrode exists are disposed respectively between end faces positioned in the stack direction of the multilayer body and the internal electrodes that are the closest to the end faces positioned in the stack direction; a pair of right and left margin portions in which no internal electrode exists are disposed respectively between end faces positioned in a direction intersecting the stack direction of the multilayer body and end portions of the internal electrodes; and dimensions of the upper and lower margin portions and dimensions of the right and left margin portions are all 50 ?m to 20

Abstract: A high-capacitance capacitor having a multi-layered vertical structure for use in an RF circuit is disclosed. The capacitor includes an upper electrode, a lower electrode, and a dielectric layer interposed between the two electrodes. A plurality of electrodes is formed in parallel in the dielectric layer in a diagonal direction. First electrodes, which are half of the plurality of electrodes, are coupled to only the upper electrode, while second electrodes, which are the other half of the plurality of electrodes, are coupled to only the lower electrode. The first electrodes and the second electrodes are alternately positioned in rows and columns. The capacitor does not require additional processes, thereby reducing complexity and cost of fabrication thereof.

Abstract: An improved semiconductor capacitor and a method for fabricating the capacitor. The capacitor is located on a substrate having a first conductive section with a first outer plate connected to a first inner plate. A second conductive section having a second outer plate connected to a second inner plate is present in the capacitor. The second inner plate is located within a first hole in the first outer plate and the first inner plate is located within a second hole in the second outer plate such that a first distance is present between the second inner plate and the first outer plate and a second distance is present between the first inner plate and the second outer plate. Multiple layers of sections like the first conductive section and the second conductive section are stacked over each other and are connected to each other as part of the capacitor. Via connections may be used to connect the layers.

Abstract: A multi-layer capacitor includes first and second side-surface terminal electrodes alternately arranged on four side surfaces of a capacitor body. First and second major-surface terminal electrodes are arranged on a major surface of the capacitor body. First and second internal electrodes which are opposed to each other within the capacitor body are respectively electrically connected at ends thereof to the first and second side-surface terminal electrodes, and are also respectively electrically connected to the first and second major-surface terminal electrodes through via hole conductors. With this arrangement, the directions of the currents flowing within the multi-layer capacitor are diversified, and the lengths of current-carrying paths are shortened so as to achieve a very low ESL value.

Abstract: A shielded planar capacitor structure (202) is discussed, formed within a Faraday cage (210) in an integrated circuit device (200). The capacitor structure (202) reduces parasitic capacitances within the integrated circuit device (200). The capacitor (202) comprises a capacitor stack (102) formed between a first and second metal layers (230,232) of the integrated circuit. The capacitor stack (102) has a first conductive layer formed from a third metal layer (106) disposed between the first and second metal layers (230,232) of the integrated circuit, a dielectric isolation layer (110) disposed upon the first conductive layer (106); and a second conductive layer (112) disposed upon the dielectric isolation layer (110) and overlying the first conductive layer (106). The structure (202) further has a first and second isolation layers (104,114) disposed upon opposite sides of the capacitor stack (102).

Abstract: An intermediate laminated structure is provided including a plurality of unfired ceramic plates stacked along a laminating direction. Each of the plates has a plurality of holes formed therethrough by a punching operation. At least a first hole in one of the plurality of unfired ceramic plates has the same shape and cross-sectional area as respective first holes in the remaining plurality of unfired ceramic plates such that the first holes define a cylinder of constant cross-sectional area throughout the entire thickness of the intermediate laminated structure.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: A capacitor comprising: a thin film laminate including a plurality of dielectric thin films and a plurality of electrode conductor thin films laminated alternately; and first kind terminals and second kind terminals formed over a first main surface of said thin film laminate and isolated from each other in a DC current, wherein a first kind electrode conductor thin films electrically connecting with said first kind terminals and a second kind electrode conductor thin films electrically connecting with said second kind terminals are so alternately laminated in a laminate direction as are separated by said dielectric thin films, and a first dielectric thin film, an other kind electrode conductor thin film and a second dielectric thin film are laminated in this order between one same kind electrode conductor thin film and other same kind electrode conductor thin film adjoining in said laminate direction, and first through holes, second through holes and the like are defined herein.

Abstract: The present invention provides a circuit and method for a fringing capacitor. The fringing capacitor includes at least two conductor layers spaced apart from each other. Each conductor layer includes at least two portions. The portions include odd ones alternating with even ones. Adjacent odd ones and even ones of the portions are spaced apart. The odd ones of the portions on a first one of the conductor layers are configured to substantially overlay the odd ones of the portions on an adjacent one of the conductor layers. The even ones of the portions on the first one of the conductor layers are configured to substantially overlay the even ones of the portions on the adjacent one of the conductor layers. The odd ones of the portions on the first one of the conductor layers are electrically coupled together and to the even ones of the portions on the adjacent one of the conductor layers, thereby defining a first electrode.

Abstract: The present invention comprises the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.

Abstract: Provided is an ultrafine nickel powder suitable for a laminated ceramic capacitor electrode material. According to the ultrafine nickel powder, cracks and/or delamination are not liable to generate in the process for producing a ceramic capacitor, and its internal electrode can be made into a thinner layer, and the electric risistivity of the capacitor-can be made low. The ultrafine nickel powder has an average particle size of 0.1-1.0 ?m, having the sulfur content of 0.02-1.0% by weight, and particles thereof being spherical, thereby exhibiting excellent properties. They can be produced by vapor phase hydrogen-reducing process using nickel chloride vapor.