Abstract: Devices for storing energy at a high density are described. The devices include a solid dielectric that is preformed to present a high exposed area onto which an electrode is formed. The dielectric material has a high dielectric constant (high relative permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.

Abstract: A laminated ceramic capacitor capable of achieving both a high dielectric constant and high electrical insulation property even when the thickness of the dielectric ceramic layer is less than 1 ?m, contains a plurality of laminated dielectric ceramic layers and a plurality of internal electrodes at interfaces between the dielectric ceramic layers, where dielectric ceramic layers are made of dielectric ceramic containing a perovskite-type compound represented by ABO3 as a main ingredient, and R (R is La or the like), M (M is Mn or the like) and Si as accessory ingredients.

Abstract: The present invention provides a capacitor including: a bottom electrode; a first dielectric layer formed on the bottom electrode; a conductive polymer layer formed on the first dielectric layer; a second dielectric layer formed on the conductive polymer layer; and a top electrode formed on the second dielectric layer, and a method of manufacturing the same.

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract: A thin film capacitor includes a first electrode, second electrode opposite to the first electrode, and a dielectric layered structure disposed between the first and second electrodes and having a doped dielectric layer. The doped dielectric layer contains a dopant therein and has a doping concentration greater than 0 atoms/cm3 and not greater than 1010 atoms/cm3.

Abstract: A dielectric ceramic containing ABO3 in which A is Ba, possibly with at least one of Ca and Sr, and B is Ti, possibly with at least one of Zr and Hf as its main component, and Si as a accessory component. The dielectric ceramic includes main phase grains containing the ABO3 main component and secondary phase grains having a composition different from that of the main phase grains. The ratio of the Si content in the secondary phase grains to the total content of Si in the dielectric ceramic is 40% or more so that more Si is distributed in the secondary phase grains. It is preferable that the Si content in secondary phase grains be 30 mol% or more.

Abstract: Devices for storing energy at a high density are described. The devices include an electrode preformed to present a high exposed area onto which a dielectric is formed. The dielectric material has a high dielectric constant (high relative permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.

Abstract: A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel.

Abstract: A crystal constituting a dielectric porcelain, comprised of a first crystal group composed of crystal grains of 0.2 atomic % or less calcium concentration and a second crystal group composed of crystal grains of 0.4 atomic % or more calcium concentration, wherein the ratio of concentration of each of magnesium and a first rare earth element contained in a center portion to that contained in a surface layer portion of crystal grains constituting the first crystal group is greater than the corresponding concentration ratio of crystal grains constituting the second crystal group, and wherein on a polished surface resulting from polishing of the surface of the dielectric porcelain, when the area of crystal grains of the first crystal group is referred to as a and the area of crystal grains of the second crystal group referred to as b, the ratio of b/(a+b) is in the range of 0.5 to 0.8.

Abstract: A capacitor structure includes: a top electrode, a bottom electrode, a first capacitor dielectric layer positioned between the top electrode and the bottom electrode and a second capacitor dielectric layer positioned between the top electrode and the bottom electrode. The first capacitor dielectric layer is selected from the group consisting HfO2, ZrO2, and TiO2. The second capacitor dielectric layer is selected from the group consisting of lanthanide oxide series and rare earth oxide series.

Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Abstract: A dielectric ceramic contains a BaTiO3-based compound as a main ingredient, and can be represented by the general formula: 100AmBO3+aNiO+bROn+cMOv+dMgO+eXOw where R represents a rare earth element such as Dy, M represents a metal element such as Mn, and X represents a sintering aid component containing Si. Ni is uniformly solid-solved in crystal grains, and the solid-solution region of the rare earth element in the crystal grains is an average 10% or less in terms of a cross section ratio. 0.96?m?1.030, 0.05?a?3, 0.1?b?1.5, 0.1?c?1.0, 0.1?d?1.5, and 0.05?e?3.5 are satisfied. A laminated ceramic capacitor has dielectric layers formed of the dielectric ceramic. As a result, a dielectric ceramic, and a laminated ceramic capacitor having excellent AC voltage characteristics, capable of keeping desired dielectric characteristics and excellent temperature characteristics, and having excellent withstand voltage and capable of ensuring reliability can be realized.

Abstract: The present invention relates to borosilicate glass compositions for a sintering agent, dielectric compositions containing the borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions. Borosilicate glass compositions for a sintering agent according to an aspect of the invention include an alkali oxide, an alkaline earth oxide and a rare earth oxide, can sinter ceramic dielectrics at low temperatures and improve the hot insulation resistance of a multilayer ceramic capacitor. Correspondingly, dielectric compositions including these borosilicate glass compositions and a multilayer ceramic capacitor using the dielectric compositions can be sintered at a low temperature of 1100° C. or less and have high hot insulation resistance, thereby ensuring high levels of reliability.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: There is provided a dielectric ceramic composition that is a dielectric ceramic material used for a laminated ceramic capacitor; that can be co-fired with internal electrodes mainly composed of Ni at a temperature of 1300° C. or less; and that has a high dielectric constant, good temperature characteristics of capacitance in a range of ?55 to 175° C., and a high resistivity ? at 175° C. The dielectric ceramic composition includes a main component represented by a composition formula (1-a) (K1-xNax)(Sr1-y-zBayCaz)2Nb5O15-a(Ba1-bCab)TiO3 (where a, b, x, y, and z are all molar amounts and 0.3?a?0.8, 0?b?0.2, 0?x<0.2, 0.1?y?0.5, 0.1?z?0.5, and 0.2?y+z?0.7); and M, as an additional component, in an amount of 0.1 to 40 parts by mole relative to 100 parts by mole of the main component (where M is at least one element from the group of V, Mn, Cr, Fe, Co, Ni, Zn, Mg, and Si).

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.

Abstract: A capacitor is disclosed. The capacitor in accordance with an embodiment of the present invention includes a first electrode, a dielectric substance, which is formed on the first electrode, a second electrode, which is formed on the dielectric substance, and a magnetic layer, which is interposed between the dielectric substance and at least one of the first electrode and the second electrode. In accordance with the present embodiment, dielectric loss can be reduced while minimizing the reduction of capacitance of the capacitor.

Abstract: The use of electrical energy storage unit (EESU) technology can provide power averaging for utility grids. Such EESUs can also be used to construct a system capable of storing electrical energy over specified periods (e.g., 24 hours) to provide peak power to homes, commercial sites, and industrial sites. By charging these power averaging units during non-peak times and then delivering the energy during peak-demands times, more efficient utilization of the present utility-grid power-generating plants and the already existing power transmission lines will be accomplished. These systems also have the capability of isolating users from utility-grid power failures, transients, and AC noise.

Abstract: To provide a dielectric ceramics achieving a high insulation resistance even at a low applied voltage, and minimizing insulation resistance drop when the voltage is increased, and also provide a multilayer ceramic capacitor including the dielectric ceramics as a dielectric layer, and having excellent life characteristics in a high temperature load test. The dielectric ceramics has crystal grains composed mainly of barium titanate and containing vanadium, and a grain boundary phase existing between the crystal grains. The dielectric ceramics contains 0.0005 to 0.03 moles of vanadium in terms of V2O5, with respect to 1 mole of barium constituting the barium titanate. In the X-ray diffraction chart of the dielectric ceramics, the diffraction intensity of (004) plane indicating the tetragonal system of barium titanate is larger than the diffraction intensity of (400) plane indicating the cubic system of barium titanate.

Abstract: A structural body which includes a first dielectric layer formed on a first substrate and including first conductive particles, each surface of the first conductive particles being entirely covered with a first dielectric film; and a second dielectric layer formed on the first dielectric layer wherein a volume ratio of a dielectric in the second dielectric layer is higher than a volume ratio of a dielectric in the first dielectric layer.

Abstract: A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes a crystalline dielectric barrier layer formed in contact with the capacitor portion and having the same composition system as the dielectric thin film, and an amorphous inorganic barrier layer formed on the surface of the crystalline dielectric barrier layer and composed of silicon nitride having non-conductivity. The inorganic barrier layer prevents deterioration in the properties of the dielectric thin film by blocking diffusion of the constituent elements of the inorganic barrier layer toward the capacitor portion.

Abstract: A capacitor includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers and first and second external terminals attached to the ceramic capacitor body. The internal active electrodes within the ceramic capacitor body are configured in an alternating manner. Internal electrode shields within the ceramic capacitor body are used to assist in providing resistance to arc-over. The shields can include a top internal electrode shield and an opposite bottom internal electrode shield wherein the top internal electrode shield and the opposite bottom internal electrode shield are on opposite sides of the plurality of internal active electrodes and each internal electrode shield extends inwardly to or beyond a corresponding external terminal to thereby provide shielding. Side shields are used. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.

Abstract: An electrical component includes ceramic layers that are stacked to form a base body, electrode layers among the ceramic layers to form at least one capacitor, at least one phase gate on a ceramic layer that corresponds to a surface of the base body, contact surfaces on a top surface of the base body, and through contacts that electrically connect the electrode layers to the contact surfaces. The through contacts are inside the base body at least in part. Side surfaces of the base body are substantially free of surface metallic contacts and of metal plating.

Abstract: A dielectric ceramic comprising a barium titanate as a main component and a capacitor comprising the dielectric ceramic are disclosed. The dielectric ceramic has a high dielectric constant that is stable over temperature, and has a small spontaneous polarization. The capacitor can reduce audible noise caused by an electrically induced strain in a power supply circuit.

Abstract: Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.

Abstract: A ceramic dielectric composition suitable for preparing capacitors for use in high-temperature service conditions is disclosed. The ceramic material and capacitors made from it exhibit unique and heretofore unrealizable properties including low variation in capacitance with voltage up to high fields, low variation in capacitance with temperature over a broad temperature range, retained high permittivity at temperatures up to 200° C. and beyond, low loss, low field-induced strain and adequate capacitance to retain performance at very low service temperatures. The material is based on sodium bismuth titanate (NBT) with selected additions of substituents and dopants to broaden and flatten its dielectric response, lower loss, lower strain, lower voltage coefficient and increase resistivity.

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device.

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract: Dielectric powder and thick-film paste compositions are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. Conductive powder and paste compositions are formed having desirable electrical and physical properties. The dielectric powder and thick-film paste compositions can be used in combination with the conductive powder and paste compositions to form capacitors and other fired-on-foil passive circuit components.

Abstract: A method of manufacturing a multilayer capacitor comprises a first layer forming step, a first electrode forming step, a second layer forming step, a second electrode forming step, a separation step, an element forming step and a terminal forming step. In the first layer forming step, a first ceramic green layer is formed on a supporting body. In the first electrode forming step, a first electrode pattern is formed on the first ceramic green layer. In the second layer forming step, a second ceramic green layer is formed laminated on the first ceramic green layer. In the second electrode forming step, a second electrode pattern is formed at the second ceramic green layer. In the separation step, the support body is separated from the laminated body. In the element forming step, elements are formed by laminating a plurality of the laminated bodies.

Abstract: There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.

Abstract: Polymer-ceramic composite materials for use in the formation of capacitors, which materials exhibit very low changes in temperature coefficient of capacitance (TCC) in response to changes in temperature within the range of from about ?55° C. to about 125° C. Specifically, these capacitor materials have a change in TCC ranging from about ?5% to about +5%, in response to changes in temperature within the desired temperature range. The inventive composite materials comprise a blend of a polymer component and ferroelectric ceramic particles, wherein the polymer component includes at least one epoxy-containing polymer, and at least one polymer having epoxy-reactive groups. The inventive polymer-ceramic composite materials have excellent mechanical properties such as improved peel strength and lack of brittleness, electrical properties such as high dielectric constant, and improved processing characteristics.

Abstract: A multilayer capacitor has a laminate body in which a first internal electrode and a second internal electrode are alternately laminated with a dielectric layer in between, a first terminal electrode provided on one end side of the laminate body, and a second terminal electrode provided on the other end side of the laminate body. The first internal electrode has a first lead portion connected to the first terminal electrode. The second internal electrode has a second lead portion connected to the second terminal electrode. The first internal electrode consists of plural types of first internal electrodes and the plural types of first internal electrodes have their respective first lead portions at different positions. Distances between the first lead portions of the respective types of the first internal electrodes and the second lead portion are different from each other.

Abstract: A capacitor having improved surface breakdown voltage performance and a method for applying laser marking to capacitors which does not reduce capacitor surface breakdown voltage, can be applied using existing laser marking technologies and apparatus, and which results in a mark that is legible and clear, is disclosed. In a first exemplary embodiment a capacitor includes a laser mark which is located near one of the capacitor terminals. The exact location is not critical as long as the mark does not make physical contact with the terminal. Conventional laser marking technologies and apparatus may be used to fix the mark in the new location. In a second embodiment the laser mark is oriented so that a flat portion of the mark is is oriented closest to the adjacent terminal.

Abstract: An MIM capacitance element (capacitance lower electrode, capacitance insulation film and capacitance upper electrode) is provided on a first insulation film on a semiconductor substrate. An interlayer insulation film is provided so as to cover the MIM capacitance element and flattened. The interlayer insulation film is provided with a first connection plug connected to the capacitance upper electrode, a first wiring layer, and a second wiring layer. A second insulation film is provided on the interlayer insulation film. The second insulation film is provided with first and second openings. A wiring pull-out portion which connects the first connection plug and the second wiring layer to each other is provided on the second insulation film.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: Provided is a MLCC module used as a direct current (DC) link capacitor that is included in an inverter of a hybrid vehicle.

Abstract: A multilayer capacitor comprises a multilayer body and a plurality of terminal electrodes formed on a side face of the multilayer body. The multilayer body includes an inner layer portion in which a plurality of dielectric layers and a plurality of inner electrodes are alternately laminated, and an outer layer portion in which a plurality of dielectric layers are laminated. In the outer layer portion, a conduction path electrically connecting a plurality of different positions in at least one of the plurality of terminal electrodes to each other is arranged. A current flowing through the terminal electrode electrically connected to the conduction path is shunted into the conduction path. This lowers the equivalent series inductance of the multilayer capacitor.

Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.

Abstract: A storage battery of the present invention is a capacitor-type storage battery having a short charging time and a long life, and capable of realizing a high output voltage. The storage battery includes a metal sheet 10 connected to a first terminal 22, a first metamaterial film 13 formed on a front surface of the metal sheet 10, and a first conductive film 12 formed on the first metamaterial film 13 and connected to a second terminal 21. The first metamaterial film 13 is a polycrystalline semiconductor film, and in each of crystal grains constituting the polycrystalline semiconductor film, the inside is of a first conductivity type, and the vicinity of interface is of a second conductivity type. An oxide insulating film may be formed on a surface of the metal sheet 10.

Abstract: A first internal electrode includes a first lead portion and a second lead portion. A second internal electrode includes a third lead portion and a fourth lead portion. A third internal electrode includes a main electrode portion and a fifth lead portion. A fourth internal electrode includes a main electrode portion and a sixth lead portion. A joint portion between the main electrode portion and the fifth lead portion of the third internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from an opposing direction of the third and fourth side faces. A joint portion between the main electrode portion and the sixth lead portion of the fourth internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from the opposing direction of the third and fourth side faces.

Abstract: A method for manufacturing a multilayer chip capacitor includes: forming screen patterns on mother green sheets such that a widthwise margin is not formed on the mother green sheets, the screen patterns are spaced apart from each other in the width direction and the longitudinal direction, and a width of each screen pattern is greater than a spacing between the adjacent screen patterns; forming internal electrode patterns on the mother green sheets; forming a stack of the mother green sheets; forming a capacitor body having internal electrodes by cutting the stack of the mother green sheets along cutting lines arranged in the width direction and the longitudinal direction; forming chip-protecting side members on both sides of the capacitor body such that the chip-protecting side members contact both sides of the internal electrodes, respectively; and forming a pair of terminal electrodes on the outer surface of the capacitor body.

Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.

Abstract: A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.

Abstract: Provided is a semiconductor device including a multi-layer dielectric structure and a method of fabricating the semiconductor device. According to one example embodiment, the semiconductor device includes a capacitor comprising: first and second electrodes facing each other; at least one first dielectric layer that is disposed between the first and second electrodes, the at least one first dielectric layer comprising a first high-k dielectric layer doped with silicon; and at least one second dielectric layer that is disposed between the at least one first dielectric layer and any of the first and second electrodes, the at least one second dielectric layer having a higher crystallization temperature than that of the first dielectric layer.

Abstract: A capacitor formed in an insulating porous material.