Abstract: An assembly includes a semiconductor device having surface-connecting terminals, a substrate having surface-connecting pads, and a capacitor having an approximately plate-shaped capacitor main body having a first surface on which the semiconductor device is mounted and a second surface at which the capacitor main body is mounted on the substrate and a plurality of electrically conductive vias penetrating the capacitor main body between the first and second surfaces and connected to the surface-connecting terminals and the surface-connecting pads.

Abstract: A laminated ceramic capacitor includes a body having an inner layer portion and an outer layer portion and a plurality of terminal electrodes spaced apart from each other in a length direction of the body. The inner layer portion has a plurality of internal electrodes stacked in a height direction of the body. The internal electrodes have led-out portions led out to a side face of the body. The outer layer portion is disposed on one of opposite faces of the inner layer portion in the height direction. The terminal electrodes are each provided with a connecting portion and a spreading portion. The connecting portion extends along the height direction to cover corresponding one of the led-out portions. The spreading portion has a width gradually increasing from one of opposite ends of the connecting portion in the height direction toward an edge of the side face.

Abstract: A multilayer electronic component is composed of a ceramic body obtained by laminating a plurality of ceramic layers via a conductor layer. The conductor layer is a plated film and extracted to one end face of the ceramic body, thereby contributing to the formation of capacity. A peripheral edge portion of the conductor layer composed of the plated film is thicker than its inner region. This avoids stripping on the peripheral edge portion of the conductor layer and avoids internal defects such as delamination. A dummy conductor layer may be formed at a distance on the end opposite the end face for extraction.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A laminated capacitor includes: a dielectric body; first terminal electrodes arranged at intervals on one surface of the dielectric body; second terminal electrodes arranged at intervals on the surface of the dielectric body; first internal electrodes arranged in layers within the dielectric body; second internal electrodes arranged in layers within the dielectric body to alternate with the first internal electrodes; first outer through-hole conductors each connecting each first terminal electrode to one first internal electrode which is located closest to the surface of the dielectric body among the first internal electrodes; second outer through-hole conductors each connecting each second terminal electrode to one second internal electrode which is located closest to the surface of the dielectric body among the second internal electrodes; a first inner through-hole conductor connecting the first internal electrodes to one another; and a second inner through-hole conductor connecting the second internal elec

Abstract: A monolithic capacitor includes a main capacitor unit having first capacitor portions and a second capacitor portion arranged in a direction of lamination, with the first capacitor portion located towards at least one end in the direction of lamination, so that the first capacitor portion is located closer to a mounting surface than the second capacitor portion. The number of pairs of third and fourth lead-out portions for third and fourth internal electrodes in the second capacitor portion is less than the number of pairs of first and second lead-out portions for first and second internal electrodes in the first capacitor portion, so that the first capacitor portion contributes to decreasing ESL while the second capacitor portion contributes to increasing ESR.

Abstract: A laminated ceramic capacitor including a capacitor body where internal electrodes and a dielectric layer are alternately laminated, and external electrodes are provided on the end faces thereof. In this capacitor body, high resistance layers are provided between the internal electrodes and dielectric layer. These high resistance layers contain a ceramic material, an element including at least one selected from Mn, Cr, Co, Fe, Cu, Ni, Mo and V, and/or a rare earth element.

Abstract: A multilayer capacitor comprises a ceramic sintered body, an internal electrode disposed in the ceramic sintered body, and an external electrode disposed on an external surface of the ceramic sintered body. The external electrode has a first electrode layer formed on the external surface of the ceramic sintered body, a second electrode layer formed on the first electrode layer, and a conductive resin layer formed on the second electrode layer. The internal electrode and the first electrode layer consist primarily of a base metal. The second electrode layer consists primarily of a noble metal or a noble metal alloy. The conductive resin layer contains a noble metal or a noble metal alloy as a conductive material.

Abstract: A multilayer capacitor includes a multilayer body in which dielectric layers and inner electrodes are alternately laminated, and terminal electrodes formed on the multilayer body. The inner electrodes include first inner electrodes and second inner electrodes alternately arranged. The terminal electrodes include at least three terminal electrodes. The first inner electrodes are electrically connected to each other via a through-hole conductor. The second inner electrodes are electrically connected to each other via a through-hole conductor. At least two first inner electrodes in the first inner electrodes are electrically connected via a lead conductor to at least two respective terminal electrodes whose number is smaller than the total number of the terminal electrodes by at least 1 in the at least three terminal electrodes.

Abstract: Internal electrode layers are superimposed in a dielectric substrate 1 at intervals. Step absorption layers are respectively provided on lateral sides of the internal electrode layers. A side portion of the internal electrode layer forms an inclined surface, and the step absorption layer is superimposed so as to partially overlap the inclined surface of the internal electrode layer. This is also applied to the other internal electrode layers and step absorption layers.

Abstract: A multilayer capacitor comprises a multilayer body in which a plurality of dielectric layers and a plurality of first and second inner electrodes are alternately laminated, and a plurality of outer conductors (first and second terminal conductors, and first and second outer connecting conductors) formed on the multilayer body. Each of the outer conductors is formed on one of two side faces of the multilayer body opposing each other. Each of the first and second inner electrodes is electrically connected to the corresponding outer connecting conductor. At least one inner connecting conductor layer including a first and a second inner connecting conductors is laminated in the multilayer body. Each of the inner connecting conductors is electrically connected to the corresponding terminal and outer connecting conductors. The equivalent series resistance of the multilayer capacitor is set to a desirable value by adjusting the number or position of inner connecting conductor layer.

Abstract: An objective is to provide a multilayer filter capable of preventing an electric current rapidly flowing by virtue of varistor effect, from passing as noise, upon application of noise of a high voltage over a varistor voltage to its input. A multilayer filter has an inductor part 10 and a varistor part 20 in a laminate 2, and the inductor part 10 has the DC resistance of 4 ?-100 ?. This prevents an electric current rapidly flowing by virtue of the varistor effect, from passing as noise, upon application of noise of a high voltage over the varistor voltage to the input.

Abstract: A capacitor with conductive layers arranged in parallel relationship. The conductive layers have nickel alloyed or add mixed with a refractory metal in an amount sufficient to raise the melting temperature of said conductive layer at least 1° C. above the melting temperature of nickel. A dielectric layers is between the conductive layers. Alternating layers of said conductive layers are in electrical contact with external terminations of opposing polarity.

Abstract: The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.

Abstract: The capacitor 10 (laminated ceramic capacitor) of the invention comprises a capacitor body 11 wherein internal electrodes 12 (electrodes) and a dielectric layer 14 are alternately laminated, and external electrodes 15 are provided on the end faces thereof. The dielectric layer 14 has a site containing particles of a dielectric material which is formed of only one of these particles in its thickness direction. Regions 24 comprising at least one element selected from a group comprising Si, Li and B are scattered between the internal electrodes 12 and dielectric layer 14.

Abstract: Thin-film capacitors are formed on ceramic substrates having high capacitance densities and other desirable electrical and physical properties. The capacitor dielectrics are annealed at high temperatures.

Abstract: A semiconductor device having the thin film capacitor includes a first electrode formed on a substrate, a capacitor insulating film containing a laminated film, which is constructed by laminating an amorphous dielectric film and a polycrystalline dielectric film via a wave-like interface, on the first electrode, and a second electrode formed on the capacitor insulating film.

Abstract: A monolithic ceramic electronic component includes a low-permeability coil portion formed by stacking low-permeability ceramic green sheets, a first coil and a relatively large number of pores, and a high-permeability coil portion formed by stacking high-permeability ceramic green sheets, a second coil and a relatively small number of pores. The first coil and the second coil are electrically connected in series to form a spiral coil. The coil portion composed of a ferrite ceramic having a small number of pores has a high permeability and a high dielectric constant, and the coil portion composed of a ferrite ceramic having a large number of pores has a low permeability and a low dielectric constant.

Abstract: A dielectric ceramic is obtained by the steps of obtaining a reaction product composed of a barium titanate base composite oxide represented by the general formula (Ba1?h?i?mCahSriGdm)k(Ti1?y?j?nZryHfjMgn)O3, in which 0.995?k?1.015, 0?h?0.03, 0?i?0.03, 0.015?m?0.035, 0?y<0.05, 0?j<0.05, 0?(y+j)<0.05, and 0.015?n?0.035 hold; mixing less than 1.5 moles of Ma (Ba or the like), less than 1.0 mole of Mb (Mn or the like), and 0.5 to 2.0 moles of Mc (Si or the like) with respect to 100 moles of the reaction product; and firing the mixture thus obtained. This dielectric ceramic has superior humidity resistance, satisfies the F characteristic of the JIS standard and the Y5V characteristic of the EIA standard, has a relative dielectric constant of 9,000 or more, and has superior high-temperature reliability.

Abstract: A multilayer capacitor has a multilayer body, and first and second terminal electrodes. In the multilayer body first and second internal electrode are laminated with a dielectric layer in between. The first internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The second internal electrode includes first and second electrode portions with a dielectric region between them along the laminating direction of the multilayer body, and a connection portion for electrically connecting the first and second electrode portions. The first internal electrode is electrically connected to the first terminal electrode, and the second internal electrode to the second terminal electrode.

Abstract: A laminated ceramic capacitor (10) divided into a first laminate (11), a second laminate (12), a third laminate (13), and a fourth laminate (14). The first laminate (11) includes a ceramic layer (15) serving as a dielectric layer. The ceramic layer (15) is thicker than a ceramic layer (17) sandwiched between internal electrodes (16a) in the second laminate (12) or the fourth laminate (14), and thinner than 20 times the thickness of the ceramic layer (17). The third laminate (13) includes dielectric layers, which serve as the ceramic layers (17), and has a thickness of 5% of the total thickness of the second laminate (12) and the fourth laminate (14). Accordingly, the third laminate (13) achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate (11), portions of via electrodes (18) that extend without being electrically connected to the internal electrodes (16b) can be shortened.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract: According to some embodiments, a capacitor includes a first external capacitor plane including a first at least one terminal of a first polarity, and a first internal capacitor plane including a second at least one terminal of the first polarity. The second at least one terminal of the first polarity may be electrically coupled to the first at least one terminal of the first polarity, and a total area of the second at least one terminal of the first polarity may be less than a total area of the first at least one terminal of the first polarity.

Abstract: Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.

Abstract: A capacitor capable of being incorporated into a packaging substrate, which capacitor includes a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

Abstract: A first inner conductor, a second inner conductor, a first inner conductor, and a second inner conductor are disposed in the order mentioned from the top in the dielectric element. The first inner conductors are respectively led out to two opposing side surfaces of the dielectric element. A pair of the second inner conductors is respectively led out to two opposing side surfaces different from the two opposing side surfaces to which the first inner conductors are respectively led out. Terminal electrodes are respectively disposed on four side surfaces of the dielectric element for connection with these four inner conductors respectively.

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract: A capacitor is provided having a structure in which an insulation film is interposed between a first electrode and a second electrode. The insulation film includes SrTiO3 as a main component, and at least one of Si and Ge added thereto.

Abstract: A wiring board has a substrate, a bank disposed above the substrate and providing a plurality of regions, and a conductive layer and first and second interconnecting lines which are parallel to each other and formed between the bank and the substrate. The first interconnecting line is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the first interconnecting line is not coincide with the vertical centerline of the second interconnecting lines. The conductive layer is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the conductive layer is not coincide with the vertical centerline of the second interconnecting line. The conductive layer and first interconnecting line have portions which are not located under the second interconnecting line and extend in opposite width directions.

Abstract: A fused or high ESR ceramic capacitor for power applications has a fuse or resistor inserted between an end termination and a terminal for one set of alternating conductive plates in the capacitor. The length and thickness of the fuse allows adjustment of the current capability of the fail-open device which provides protection for the circuit in the event of short-circuiting, or the pattern created by the thick-film resistor application defining the added ESR for the capacitor.

Abstract: A decoupling module for decoupling high-frequency signals from A power supply line, the module including a layer (30) of dielectric material which is arranged between a first and a second metallic layer (20, 22), where the first metallic layer (20) is connected as a ground electrode of the decoupling module and the second metallic layer (22) includes at least two surfaces of different size which are consecutively electrically connected between an input connection point and an output connection point, while two respective consecutive surfaces are connected to each other by only one conducting section.

Abstract: Disclosed herein is a small particle oxide powder for dielectrics. The oxide powder has a perovskite structure, an average particle diameter [D50(?m)] of 0.3 ?m or less, a particle size distribution of the average particle diameter within 3%, a particle size distribution satisfying a condition D99/D50<2.5, a content of OH? groups of 0.2 wt % and a C/A axial ratio of 1.006 or more. A method of manufacturing the oxide powder comprises the steps of mixing TiO2 particles and a compound solved with at least one element represented by A of the perovskite structure of ABO3; drying and pulverizing the mixture of TiO2 and the compound; calcining the pulverized mixture; adding the oxide containing the elements of the site A to the coated TiO2 particles and wet-mixing, drying and pulverizing; primarily calcining and pulverizing the pulverized powder under vacuum; and secondarily calcining and pulverizing the powder.

Abstract: There are provides the steps of forming sequentially a first conductive film, a dielectric film, and a second conductive film on an insulating film, forming a first film on the second conductive film, forming a second film made of insulating material on the first film, forming hard masks by patterning the second film and the first film into a capacitor planar shape, etching the second conductive film and the dielectric film in a region not covered with the hard masks, etching the first conductive film in the region not covered with the hard masks up to a depth that does not expose the insulating film, removing the second film constituting the hard masks by etching, etching a remaining portion of the first conductive film in the region not covered with the hard masks to the end, and removing the first film.

Abstract: A capacitor has at least one plate of a first polarity and at least two plates of a second polarity, with a terminal electrically connected to the at least two plates of the second polarity such that the electrical plate connections are remote from an edge of the connected plates.

Abstract: An embedded multilayer printed circuit includes a first ground plane (105, 1205, 1405) of a multilayer printed circuit board and an embedded layer. The embedded layer includes a co-planar capacitor (110, 1210, 1410), a distributed inductor (125, 1215, 1415), and a capacitive plate (135, 1220, 1420) circuit. The capacitive plate is a plate of a vertical capacitor (270, 1305, 1505). The embedded layer further includes a node (111, 1225, 1425) of the embedded multilayer printed circuit that is formed by a connection of a first terminal of the co-planar capacitor and a first terminal of the first distributed inductor, and in some embodiments, the first capacitive plate is also connected to the node. A second terminal of one of the co-planar capacitor and the distributed inductor is connected to the first ground plane.

Abstract: The invention relates to a stacked capacitor (10) comprising a silicon base plate (16), a poly-silicon center plate (32) arranged above the base plate (16), a lower gate-oxide dielectric (26) arranged between the base plate (16) and the center plate (32), a cover plate (36) made of a metallic conductor and arranged above the center plate (32), and an upper dielectric (34) arranged between the center plate (32) and the cover plate (36). The cover plate (36) and the base plate (16) are electrically connected to each other and together form a first capacitor electrode. The center plate (32) forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Abstract: A semiconductor device is disclosed which has a plurality of unit capacitive elements. At least one lead-out electrode of bottom electrodes of the unit capacitive elements of the capacitive element group is disposed along a circumference going around top electrodes as a whole of the capacitive element group, and a given capacitive element is connectable to the capacitive element group, the given capacitive element having a capacitance value that is set to eliminate effects of parasitic capacitance of at least the capacitive element group. Furthermore, the given capacitive element may consist of a capacitive element group.

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract: An electrical component includes a ceramic base body having at least four contact surfaces. Two of the contact surfaces are on opposite sides of the ceramic base body. First protective layers are arranged on regions of the opposite sides of the ceramic base body that do not include the contact surfaces. The first protective layers have a composition that allows the first protective layers to be sintered at a higher temperature than the contact surfaces. Second protective layers are arranged on at least two opposite surfaces of the ceramic base body. The ceramic base body, the first protective layers, and the second protective layers are sintered together.

Abstract: In accordance with the invention there is provided a semiconductor capacitor having a first semiconductor layer which forms a first capacitor electrode and which includes silicon, a second capacitor electrode and a capacitor dielectric including praseodymium oxide between the capacitor electrodes, in which provided between the capacitor dielectric including praseodymium oxide and at least the first semiconductor layer including silicon is a first thin intermediate layer representing a diffusion barrier for oxygen. In particular the thin intermediate layer can include oxynitride.

Abstract: A base structure is formed from a green material having first and second opposing sides and having a plurality of via openings therein. The green material is then sintered so that the green material becomes a sintered ceramic material and the base structure becomes a sintered ceramic base structure having the via openings. A conductive via is formed in each via opening of the sintered ceramic base structure. First and second capacitor structures are formed on the sintered ceramic base structure, each on a respective side of the sintered ceramic base structure. The power and ground planes of the capacitor structure are connected to the vias. As such, a capacitor structure can be formed and connected to the vias without the need to drill via openings in brittle substrates such as silicon substrates. Capacitor structures on opposing sides provide more capacitance without manufacturing complexities associated with the manufacture of one capacitor structure having a large number of power and ground planes.

Abstract: A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelectricity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A laminated ceramic capacitor 10 divided into a first laminate 11, a second laminate 12, a third laminate 13, and a fourth laminate 14. The first laminate 11 includes a ceramic layer 15 serving as a dielectric layer. The ceramic layer 15 is thicker than a ceramic layer 17 sandwiched between internal electrodes 16a in the second laminate 12 or the fourth laminate 14, and thinner than 20 times the thickness of the ceramic layer 17. The third laminate 13 includes dielectric layers, which serve as the ceramic layers 17, and has a thickness of 5% of the total thickness of the second laminate 12 and the fourth laminate 14. Accordingly, the third laminate 13 achieves the function of absorbing an electrode-induced thickness differential. Also, by means of regulating the thickness of the first laminate 11, portions of via electrodes 18 that extend without being electrically connected to the internal electrodes 16b can be shortened.

Abstract: This invention relates to a process which produces flat, distortion-free, zero-shrink, low-temperature co-fired ceramic (LTCC) bodies, composites, modules or packages from precursor green (unfired) laminates of three or more different dielectric tape chemistries that are configured in an uniquely or pseudo-symmetrical arrangement in the z-axis of the laminate.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A capacitor with conductive layers arranged in parallel relationship. The conductive layers have nickel alloyed with a refractory metal in an amount sufficient to raise the melting temperature of said conductive layer at least 1° C. above the melting temperature of nickel. A dielectric layers is between the conductive layers. Alternating layers of said conductive layers are in electrical contact with external terminations of opposing polarity.

Abstract: A method to produce a distortion-free asymmetrical low-temperature co-fired ceramic structure comprising at least one layer of glass-containing internal constraining tape and at least one layer of glass-containing primary tape wherein the internal constraining tape and the primary tape are laminated to form an asymmetrical laminate and wherein a release layer is deposited on at least one surface of the laminate forming an assembly, wherein the surface is opposite the position of greatest asymmetry of the laminated layers and wherein the assembly is thermally processed producing a structure exhibiting an interactive suppression of x,y shrinkage.

Abstract: The present invention provides a barium titanate having a small particle size, containing small amounts of unwanted impurities, and exhibiting excellent electric characteristics, which can be employed for forming a dielectric ceramic thin film required for a small-sized capacitor which enables production of a small-sized electronic apparatus; and a process for producing the barium titanate. When a titanium oxide sol is reacted with a barium compound in an alkaline solution containing a basic compound, the basic compound is removed in the form of gas after completion of reaction, and the resultant reaction mixture is fired, a barium titanate having a large BET specific surface area and a high tetragonality content is produced.