Abstract: A multilayer capacitor comprises a multilayer body and a plurality of terminal electrodes formed on a side face of the multilayer body. The multilayer body includes an inner layer portion in which a plurality of dielectric layers and a plurality of inner electrodes are alternately laminated, and an outer layer portion in which a plurality of dielectric layers are laminated. In the outer layer portion, a conduction path electrically connecting a plurality of different positions in at least one of the plurality of terminal electrodes to each other is arranged. A current flowing through the terminal electrode electrically connected to the conduction path is shunted into the conduction path. This lowers the equivalent series inductance of the multilayer capacitor.

Abstract: A multilayer ceramic capacitor includes a plurality of ceramic dielectric layers, a plurality of inner electrode layers and and external electrodes. The ceramic dielectric layers includes barium titanate crystal grains having pores inside. The inner electrode layers are between the ceramic dielectric layers. The external electrodes are electrically connected to the inner electrode layers. The barium titanate crystal grains each have a core-shell structure which include a core and a shell around the core. The the pores are mainly formed in the cores.

Abstract: A first internal electrode includes a first lead portion and a second lead portion. A second internal electrode includes a third lead portion and a fourth lead portion. A third internal electrode includes a main electrode portion and a fifth lead portion. A fourth internal electrode includes a main electrode portion and a sixth lead portion. A joint portion between the main electrode portion and the fifth lead portion of the third internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from an opposing direction of the third and fourth side faces. A joint portion between the main electrode portion and the sixth lead portion of the fourth internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from the opposing direction of the third and fourth side faces.

Abstract: A method including forming a layer of a first ceramic material on a substrate; and after forming the layer, forming a second ceramic material on the layer of the first ceramic material, the formed second ceramic material including an average grain size less than a grain size of the first ceramic material. An apparatus including a first electrode; a second electrode; and a sintered ceramic material, wherein the ceramic material comprises first ceramic grains defining grain boundaries therebetween and second ceramic grains having an average grain size smaller than a grain size of the first ceramic grains. A system including a device including a microprocessor, the microprocessor coupled to a circuit board through a substrate, the substrate including a capacitor structure formed on a surface, the capacitor structure including a first electrode, a second electrode, and a sintered ceramic material disposed between the first electrode and the second electrode.

Abstract: A capacitor formed in an insulating porous material.

Abstract: A dielectric ceramic is provided having a high relative dielectric constant, and in the case in which it is used for a multilayer ceramic capacitor, high insulating properties and superior reliability can be obtained even when the thickness of a dielectric ceramic layer is decreased. The dielectric ceramic used for forming the dielectric ceramic layer of a multilayer ceramic capacitor has a composition represented by 100 (Ba1?w?x?mCawSrxGdm)k(Ti1?y?z?nZryHfzMgn)O3+a+pMnO2+qSiO2+rCuO, in which 0.995?k?1.010, 0?w<0.04, 0?x?0.04, 0?y?0.10, 0?z?0.05, 0.015?m?0.035, 0.015?n?0.035, 0.01?p?1.0, 0.5?q?2.5, and 0.01?r?5.0. In addition, a is a value selected with respect to the deviation from 3 so that the primary component is electrically neutral.

Abstract: An electric component has a base body. A surface of the base body is provided with at least one first electrically conductive material layer and the first material layer is coated with a further electrically conductive material layer on the surface facing away from the base body. The material layers form at least part of an external contact that has a closed, porous, outer surface.

Abstract: In a device including multiple metal-insulator-metal (MIM) capacitors and a method of fabricating the same, the multiple MIM capacitors comprise a lower interconnect in a substrate; a first dielectric layer on the lower interconnect; a first intermediate electrode pattern on the first dielectric layer overlapping with the lower interconnect; a second intermediate electrode pattern on the first dielectric layer and spaced apart from the first intermediate electrode pattern in a same plane of the device as the first intermediate electrode pattern; a second dielectric pattern on the second intermediate electrode pattern; and an upper electrode pattern on the second dielectric pattern.

Abstract: A monolithic ceramic capacitor includes a first same-polarity-electrode-connecting conductor and a second same-polarity-electrode-connecting conductor that are provided inside a ceramic laminate. The first same-polarity-electrode-connecting conductor is electrically connected to all of the first outer electrodes, and the second same-polarity-electrode-connecting conductor is electrically connected to all of the second outer electrodes. Preferably, a plurality of first same-polarity-electrode-connecting conductors and a plurality of second same-polarity-electrode-connecting conductors are successively disposed in the laminating direction inside the ceramic laminate.

Abstract: The present invention is directed to a thick film composition for use in low temperature co-fired ceramic circuits comprising, based on weight percent total thick film composition: (a) 30-98 weight percent finely divided particles selected from noble metals, alloys of noble metals and mixtures thereof; (b) one or more selected inorganic binders and/or mixtures thereof, and dispersed in (c) organic medium, and wherein said glass compositions are immiscible or partially miscible with remnant glasses present in the low temperature co-fired ceramic substrate glasses at the firing conditions. The present invention is further directed to methods of forming multilayer circuits utilizing the above composition and the use of the composition in high frequency applications (including microwave applications).

Abstract: The invention relates to a high-dielectric constant metal/ceramic/polymer composite material and a method for producing an embedded capacitor. As ceramic particles having a relatively small size are bound to the surface of metal particles having a relatively large size by mixing, the occurrence of percolation can be prevented without coating the metal particles, and at the same time, the capacitance of an embedded capacitor can be increased. In addition, a process for coating the surface of the metal particles can be omitted, thus contributing to the simplification of the overall preparation procedure.

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract: A multilayer capacitor is provided that includes a dielectric body, an internal layer portion, an external layer portion and a first terminal electrode and a second terminal electrode to be set at different electric potentials from each other and formed at least on a side face parallel to stacking direction Z of side faces of the dielectric body. Each of the first terminal electrodes are connected with at least one of the first internal conductor layer and a plurality of the first external conductor layers and each of the second terminal electrodes are connected with at least one of the second internal conductor layer and a plurality of the second external conductor layers. The dielectric layer positioned at the external layer portions comprises a plurality of pin hole conducting portions.

Abstract: A dielectric ceramic including a perovskite compound represented by the general formula {(Ba1-x-yCaxSny)m(Ti1-zZrz)O3} as a primary component in which the x, y, z, and m satisfy 0.02?x?0.20, 0.02?y?0.20, 0?z?0.05, and 0.99?m?1.1 and is processed by a thermal treatment at a low oxygen partial pressure of 1.0×10?10 to 1.0×10?12 MPa. Accordingly, there are provided a dielectric ceramic which can be stably used in a high-temperature atmosphere without degrading dielectric properties, properties of which can be easily adjusted, and which generates no electrode breakage even when ceramic layers and conductive films are co-fired, and a ceramic electronic element, such as a multilayer ceramic capacitor, which uses the above dielectric ceramic.

Abstract: There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units disposed in a laminated direction; first to fourth outer electrodes formed on side surfaces of the capacitor body, respectively; and at least one connecting conductor line connecting the first and third outer electrodes having identical polarity to each other and the second and fourth outer electrodes having identical polarity to each other, wherein the first capacitor body includes first and second inner electrodes, the second capacitor unit includes a plurality of third and fourth inner electrodes, the first to fourth outer electrodes are connected to the first to fourth inner electrodes, respectively, and an equivalent series resistance (R1) of the first capacitor unit and a combined equivalent series resistance (R2?) of the second capacitor and the connecting conductor line satisfy the Equation 0.7(R1)?R2??1.3(R1).

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: A printed wiring board includes an insulating layer and a capacitor including a ceramic high dielectric layer, a first electrode and a second electrode, the high dielectric layer being interposed between the first and second electrodes. A plurality of resin insulating layers are formed on the insulating layer and include an upper resin insulating layer provided on a first electrode side of the capacitor, and a lower resin insulating layer provided on a second electrode side of the capacitor. A semiconductor device mounting pad includes a first pad and a second pad, the semiconductor device mounting pad being formed on an outermost resin insulating layer of the resin insulating layers, and a first via conductor is formed in at least one of the resin insulating layers to electrically connect the first pad with the first electrode.

Abstract: A multilayer capacitor has a first inner electrode connected to a first terminal electrode, a second inner electrode connected to a second terminal electrode, and third and fourth inner electrodes connected to third and fourth terminal electrodes. The first and second inner electrodes have no overlapping area therebetween when seen in the opposing direction of the first and second main faces and are arranged at respective positions different from each other in the opposing direction of the first and second main faces and in the opposing direction of the first and second side faces. The third and fourth inner electrodes have no overlapping area therebetween when seen in the opposing direction of the first and second main faces and are arranged at respective positions different from each other in the opposing direction of the first and second main faces and in the opposing direction of the first and second side faces.

Abstract: Provided is a multilayer ceramic capacitor including external electrodes which also functions as a resistive element, and the external electrodes achieve strong bonding with internal electrodes containing Ni or a Ni alloy. The external electrodes include a resistive electrode layers contacting a ceramic laminate and internal electrodes. The resistive electrode layers contains a complex oxide which reacts with Ni or a Ni alloy contained in the internal electrodes in a proportion of 26 to 79% by weight, a glass component in a proportion of 20 to 56% by weight, and metal which reacts with Ni or a Ni alloy in a proportion of 1 to 18% by weight.

Abstract: A thin film capacitor element composition having a bismuth layered compound with a c-axis oriented substantially vertical to the substrate surface, wherein the bismuth layered compound is expressed by the formula (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3M+3, the symbol m in the formula is an odd number, at least part of the Bi and/or A of the bismuth layered compound is substituted by a rare earth element, and the number of moles substituted by the rare earth element is larger than 1.0 and 2.8 or less with respect to the number of moles (m+1) of the total of Bi and A.

Abstract: The invention aims at providing a dielectric ceramic composition including BamTiO2+m where “m” satisfies 0.99?m?1.01 and BanZrO2+n where “n” satisfies 0.99?n?1.01, an oxide of Mg, an oxide of R where R is at least one selected from Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, an oxide of at least one element selected from Mn, Cr, Co and Fe, and an oxide of at least one element selected from Si, Li, Al, Ge and B. 35 to 65 moles of BanZrO2+n, 4 to 12 moles of an oxide of Mg, 4 to 15 moles of an oxide of R, 0.5 to 3 moles of an oxide of Mn, Cr, Co and Fe, and 3 to 9 moles of an oxide of Si, Li, Al, Ge and B are included therein per 100 moles of the BamTiO2+m.

Abstract: A method of producing a multilayer ceramic electronic device, having a firing step for firing a pre-firing element body wherein a plurality of dielectric layers and internal electrode layers containing a base metal are alternately arranged, characterized in that the firing step has a temperature raising step for raising a temperature to a firing temperature, and hydrogen is continued to be introduced from a point in time of the temperature raising step. According to the method, it is possible to provide a method of producing a multilayer ceramic electronic device, such as a multilayer ceramic capacitor, wherein shape anisotropy and other structural defaults are hard to occur and electric characteristics are improved while suppressing deterioration thereof even if dielectric layers becomes thinner and stacked more.

Abstract: A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrodes. Internal and/or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the internal electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups. Each exposed portion is within a predetermined distance from other exposed portions in a given group such that termination structures may be formed by deposition and controlled bridging of a thin-film plated material among selected of the exposed internal conductive elements. Electrolytic plating may be employed in conjunction with optional cleaning and annealing steps to form directly plated portions of copper, nickel or other conductive material. Once an initial thin-film metal is directly plated to a component periphery, additional portions of different materials may be plated thereon.

Abstract: A capacitor comprising: a plurality of laminated dielectric layers; a plurality of inner electrode layers each disposed between mutually adjacent ones of the dielectric layers; and dummy electrode layers respectively disposed between the dielectric layers, disposed on sides closer to outer peripheral sides of the dielectric layers than to the inner electrode layers and disposed apart from the inner electrode layers.

Abstract: A dielectric ceramic composition for low-temperature sintering and hot insulation resistance (hot IR) is capable of carrying out low-temperature sintering, improving a hot IR characteristic, and meeting X5R characteristics, and a multilayer ceramic capacitor makes use of the dielectric ceramic composition. The dielectric ceramic composition includes a main component BaTiO3, and sub-components, based on 100 moles of the main component, MgO of 0.5 moles to 2.0 moles, Re2O3 of 0.3 moles to 2.0 moles, MnO of 0.05 moles to 0.5 moles, V2O5 of 0.01 moles to 0.5 moles, BaO of 0.3 moles to 2.0 moles, SiO2 of 0.1 moles to 2.0 moles, and borosilicate glass of 0.5 moles to 3.0 moles, where Re includes at least one selected from the group consisting of Y, Ho and Dy.

Abstract: There is provided a multilayer chip capacitor including: a capacitor body including first and second capacitor units; and first to fourth outer electrodes, wherein the first capacitor unit includes at least one pair of first and second inner electrodes, the second capacitor unit includes at least one pair of third and fourth inner electrodes, an alternate laminated portion is formed in one area within the capacitor body, the alternate laminated portion having the first to fourth inner electrodes sequentially laminated therein, and a capacitance adjusting portion is formed in another area within the capacitor body, the capacitance adjusting portion having at least one of the one pair of first and second inner electrodes and the one pair of third and fourth inner electrodes laminated repeatedly.

Abstract: This electronic component comprises a substrate; and a capacitor part provided on the substrate, the capacitor part includes a first electrode part provided on the substrate; a dielectric film covering the first electrode part; an insulating film that contacts the dielectric film and has an opening part; and a second electrode part that contacts an inner wall surface of the opening part of the insulating film and a surface of the dielectric film, and when the angle between a first interface between the dielectric film and the insulating film, and a second interface between the insulating film and the second electrode part is ?, ? is not more than 22°.

Abstract: Disclosed herein is a polymer-ceramic dielectric composition. The dielectric composition comprises a polymer and a ceramic dispersed in the polymer wherein the ceramic is composed of a material having a perovskite structure represented by ABO3 and a metal oxide dopant and has an electrically charged surface. According to the dielectric composition, the surface of the ceramic is electrically charged to induce space-charge polarization (or interfacial polarization) at the polymer/ceramic interface, resulting in an increase in dielectric constant. Since the dielectric composition has a high dielectric constant particularly in a low-frequency range, it can be suitably used to produce decoupling capacitors.

Abstract: A monolithic ceramic electronic component includes a ceramic laminate which includes a plurality of stacked ceramic layers and which has a first principal surface, a second principal surface opposed to the first principal surface, a first side surface, and a second side surface opposed to the first side surface, first external terminal electrodes arranged on the first side surface, second external terminal electrodes arranged on the second side surface, first internal electrodes arranged in the ceramic laminate, and second internal electrodes arranged in the ceramic laminate. The first internal electrodes include first opposed portions, first lead portions, and first projecting portions. The second internal electrodes include second opposed portions, second lead portions, and second projecting portions.

Abstract: A multi-segment capacitor fabricated on a semiconductor substrate includes M×N capacitor segments arranged in a matrix of M rows and N columns. Each capacitor segment includes two groups of conductive fingers preferably made of metal wires. The metal wire fingers are distributed within multiple metal layers in such a manner that two neighboring parallel metal wire fingers within a particular metal layer are electrically insulated and connected to different terminals of the capacitor. Further, at least the longitudinal axes of the parallel metal wire fingers within two different metal layers are not parallel to each other within the same capacitor segment.

Abstract: A ceramic capacitor assembly has a ceramic capacitor and a cushion. The ceramic capacitor has a body, two terminals formed respectively on the body and two legs connecting to and protruding respectively from the terminals. The cushion is a resilient material and has an upper surface corresponding to and mounted adjacent to the ceramic capacitor, a lower surface, an outer edge and two fastening detents. The detents correspond to the legs and are provided for legs to fasten to the cushion. The ceramic capacitor and the cushion are easily assembled and reduce cost and complexity of manufacture.

Abstract: Among a plurality of first inner electrodes, at least one first inner and a second inner electrode are arranged as opposed with at least one of the dielectric layers in between. Third and fourth inner electrodes are arranged as opposed with at least one of the dielectric layers in between. The first inner electrodes are electrically connected to a first external connection conductor via lead conductors. The second inner electrode is electrically connected to a second terminal conductor via a lead conductor. The third inner electrode is electrically connected to a third terminal conductor via a lead conductor. The fourth inner electrode is electrically connected to a fourth terminal conductor via a lead conductor. Among all the first inner electrodes, one to multiple first inner electrodes that are less than the total first inner electrodes are electrically connected to the first terminal conductors via lead conductors.

Abstract: A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.

Abstract: A capacitor array with a multiplicity of capacitors with terminations of alternating polarity wherein the terminations are arranged in M columns and N rows. A circuit is provided with terminations in a grid of L columns and K rows wherein the terminations are of alternating polarity with the proviso that a first terminal with L={acute over (?)}M has the same polarity as a second terminal with L={acute over (?)}M+1 wherein {acute over (?)} is an integer.

Abstract: A multi-layer ceramic capacitor including: a ceramic sintered body having cover layers provided on upper and lower surfaces thereof as outermost layers and a plurality of ceramic layers disposed between the cover layers; first and second internal electrodes formed on the ceramic layers, the first and second internal electrodes stacked to interpose one of the ceramic layers; first and second external electrodes formed on opposing sides of the ceramic sintered body to connect to the first and second internal electrodes, respectively; and anti-oxidant electrode layers formed between the cover layers and adjacent ones of the ceramic layers, respectively, the anti-oxidant electrode layers arranged not to affect capacitance.

Abstract: This disclosure relates to compositions and methods for using such compositions to provide protective coatings, particularly of electronic components. Fired-on-foil ceramic capacitors coated with a polybenzoxazole encapsulant which may be embedded in printed wiring boards are disclosed.

Abstract: A capacitor is provided. The capacitor includes a dielectric polymer film comprising a cyanoresin and at least one electrode coupled to the dielectric polymer film. The capacitor has an energy density of at least about 5 J/cc. A method of making a capacitor is provided. The method includes dissolving a cyanoresin in a solvent to form a solution and coating the solution on a substrate to form a dielectric polymer film. The dielectric polymer film has a breakdown strength of at least about 300 kV/mm.

Abstract: A method of processing a ceramic capacitor includes a first step of applying a DC voltage to a ceramic capacitor by a first DC voltage source, and a second step of applying a DC voltage by a second DC voltage source to generate in the ceramic capacitor a polarization in a direction opposite to a direction of a polarization generated by the application of the DC voltage in the first step, thereby reducing electric charge remaining in the ceramic capacitor.

Abstract: A first signal internal electrode is connected to a first signal terminal electrode and a second signal internal electrode is connected to a second signal terminal electrode. A first ground internal electrode is connected to a first ground terminal electrode and a second ground internal electrode is connected to a second ground terminal electrode. The first signal internal electrode and the first ground internal electrode have their respective opposed regions. The second signal internal electrode and the second ground internal electrode have their respective opposed regions. The first signal internal electrode and the second ground internal electrode are not opposed to each other. The second signal internal electrode and the first ground internal electrode are not opposed to each other. The first signal internal electrode and the second signal internal electrode are connected through a signal throughhole conductor.

Abstract: Disclosed are methodology and corresponding device subject matters for providing single layer ceramic capacitors through the use of significantly reduced numbers of processing steps. An aspect of present methodology resides in the early introduction of a plurality of selectively spaced through holes in an unfired ceramic wafer. Such holes provide connection points between conductive coatings on both sides of a subsequently fired wafer and eliminate the need to perform a previously employed third sputtering step to achieve connection between the layers. The present methodology also provides for end of process determination of final capacitive values for the finished devices.

Abstract: A composite electronic component has: a first multilayer section including an electrode layer; and a second multilayer section laid on the first multilayer section and including at least one ground electrode layer on which a ground electrode is formed, and at least one hot electrode layer on which a hot electrode is formed. In the second multilayer section, the hot electrode layer is interposed between the ground electrode layer nearest to the first multilayer section, and the first multilayer section and in the ground electrode on the ground electrode layer nearest to the first multilayer section, at least a part of an exposed portion exposed from the hot electrode to the first multilayer section side is a narrow portion narrower than a width of an unexposed portion not exposed therefrom.

Abstract: Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low ESL, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Furthermore, a combined ESR of the first capacitor portions is set to be less than or greater than a combined ESR of the second capacitor portion.

Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion to a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly 10. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 20 has such constitution that a first electrode layer connected with the internal electrode, a second electrode layer (electroconductive resin layer) including a hardened product of thermohardening resin containing a polyphenol compound having a side chain composed of an aliphatic group, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.

Abstract: A parallel-plate capacitor structure includes a capacitor electrode including a first resistance and an electrode tab appended to the capacitor electrode and including a second resistance. The second equivalent series resistance is greater than the first equivalent series resistance. A process of assembling a parallel-plate capacitor package is also disclosed. A computing system is also disclosed that includes the parallel-plate capacitor package.

Abstract: A multilayer chip capacitor includes: a capacitor body; internal electrodes disposed in the capacitor body, each internal electrode having one or more lead; and external electrodes disposed on first and second side surfaces of the capacitor body to be electrically connected to the internal electrodes through the leads. The average number of leads in each internal electrode is smaller than half (½) of the total number of external electrodes. The leads of the internal electrodes having opposite polarities and adjacent in the lamination direction are disposed to be adjacent to each other as seen from the lamination direction. All the internal electrodes having the same polarity are electrically connected to each other in the capacitor.

Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.

Abstract: A multilayer capacitor has a capacitor element body of a nearly rectangular parallelepiped shape in which a signal electrode layer and a GND electrode layer are laminated with a dielectric layer in between, and signal terminal electrodes and GND terminal electrodes each set of which is provided on either of two side faces along the longitudinal direction of the capacitor element body. A signal electrode is led to each of the two side faces along the longitudinal direction of the capacitor element body and connected to the signal terminal electrodes. First GND electrode and second GND electrode are arranged alongside as spaced in a direction perpendicular to the longitudinal direction of the capacitor element body. The first GND electrode is led to one side along the longitudinal direction of the capacitor element body and connected to the GND terminal electrode.