Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first to fourth terminal electrodes. Electrode parts of the first to fourth terminal electrodes cover ridges formed between first and third side faces, first and fourth side faces, second and third side faces, and second and fourth side faces. The capacitor element has an element part. The element part is formed such as to overlap the electrode parts when seen in a second and a third directions and keep away from respective areas about the electrode parts when seen in a first direction.

Abstract: One embodiment includes a method that includes positioning a first substantially planar electrode including material defining a first aperture into a capacitor stack in alignment with a second substantially planar electrode such that a first non-aperture portion of the second substantially planar electrode at least partially overlays the first aperture and joining the first substantially planar electrode to the second substantially planar electrode proximal the material defining the first aperture and the first non-aperture portion of the second substantially planar electrode.

Abstract: Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

Abstract: In a ceramic electronic component, an electrically conductive resin layer is arranged to cover a thick film layer and to extend beyond the end of the thick film layer by at least about 100 ?m and a plating layer is arranged to cover the electrically conductive resin layer except a region having a dimension of at least about 50 ?m and extending along the end of the electrically conductive resin layer. Consequently, the concentration of the stress is reduced.

Abstract: A method of manufacturing a metal-insulator-metal (MIM) capacitor that includes at least one of the following steps: Sequentially forming a bottom metal film, an insulating film, and a top metal film over a wafer. Forming a first pattern for etching the top metal film and the insulating film. Etching the top metal film and the insulating film, using the formed first pattern, and then stripping the first pattern. Conducting a heat treatment and a cooling split for the wafer. Forming a metal pattern for etching the bottom metal film. Etching the bottom metal film, using the formed metal pattern, and then stripping the metal pattern.

Abstract: The present invention has a configuration which allows manufacturing a capacitor comprising a first electrode layer, conductive first convex sections layered on a surface of the first electrode layer, a first dielectric layer formed on a surface of the first convex sections and a surface of the first electrode layer, and a second electrode layer formed so as to be superimposed on the first convex sections and the first electrode layer via the first dielectric layer.

Abstract: A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

Abstract: Material powder having a tetragonal perovskite crystal structure essentially containing BaTiO3 is provided. The material powder has a c-axis/a-axis ratio ranging from 1.009 to 1.011 and an average particle diameter not larger than 0.5 ?m. A dielectric layer is provided by mixing the material powder with additive. The dielectric layer has a tetragonal perovskite crystal structure essentially containing BaTiO3. The dielectric layer has a c-axis/a-axis ratio ranging from 1.005 to 1.009 and an average particle diameter not larger than 0.5 ?m. An electrode is formed on the dielectric layer, thus, providing a ceramic capacitor. This ceramic capacitor has a large capacitance and a small capacitance-decreasing rate.

Abstract: A multilayer electronic component has: a first capacitive electrode layer of a rectangular shape on which four capacitive electrode portions are formed at four comers; and a ground electrode layer which is laid on the first capacitive electrode layer and on which a ground electrode is formed so as to be arranged as superposed over the four capacitive electrode portions. The four capacitive electrode portions are equidistant from a first facing edge pair of the first capacitive electrode layer and equidistant from a second facing edge pair different from the first edge pair. This configuration equalizes distributions of electric fields established between the respective capacitive electrode portions and the ground electrode, which realizes uniformization of the capacitances in the four respective capacitive electrode portions.

Abstract: This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

Abstract: A highly reliable multilayer ceramic electronic device is obtained while preventing crack defects generated in a ceramic laminate by application of a heat shock in a mounting step or the like. The multilayer ceramic electronic device is constructed such that the average value of continuities of internal electrodes located in two regions (f) is lower by 5% to 20% inclusive than the average value of continuities of internal electrodes located in the central portion in a lamination direction. The two regions (f) are the regions from the topmost internal electrode and the bottommost internal electrode located in the lamination direction to the inside, respectively, within 10% of the distance (d) therebetween. Continuity is defined by (X?Y)/X in which X is the length of a cross section of an internal electrode in one direction and Y indicates the sum of gaps (g) formed by pores in the cross section of the internal electrode.

Abstract: In a multilayer capacitor including a capacitor body, first capacitor portions and a second capacitor portion are arranged in the direction of lamination. While a resonant frequency of the first capacitor portions is set to be greater than a resonant frequency of the second capacitor portion so that the first capacitor portions contribute to low impedance, an ESR per layer of the second capacitor portion is set to be greater than an ESR per layer of the first capacitor portions so that the second capacitor portion contributes to high ESR. Further, a combined ESR of the first capacitor portions is set to be substantially equal to a combined ESR of the second capacitor portion.

Abstract: A mixed dispersant which can improve the efficiency of dispersing metal powder by effectively adsorbing on the surface of the metal powder and preventing aggregation thereof, and a paste composition and a dispersion method using the same are provided. A multilayer ceramic capacitor (MLCC) is also provided. The mixed dispersant includes a basic dispersant and an acidic dispersant in accordance with the acidity and basicity of nickel metal powder and thus can achieve an optimal dispersion efficiency. An improvement in the dispersion efficiency as such can consequently suppress aggregation of the nickel metal powder during the preparation of a conductive paste composition containing a nickel metal powder, and therefore a larger amount of the nickel metal powder can be used in the paste composition. The increased amount of nickel metal powder allows producing an internal nickel electrode having improved electric properties and mechanical properties during the production of MLCCs.

Abstract: A multilayer electronic component having a ceramic substrate and a resin layer mounted on a mounting substrate. Recess portions are formed at an outside-facing major surface side of the resin layer. In the resin layer, columnar conductors are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer. End portions of the columnar conductors are located inside the recess portions further from opening faces thereof and have end surfaces exposed in the recess portions. When a multilayer electronic component is mounted on a mounting substrate, solder is provided on the end surfaces of the columnar conductors in the recess portions. The thickness of solder used in the above mounting does not interfere with a reduction in size and height of an electronic device that includes the above multilayer electronic component.

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract: A feedthrough capacitor array has first and second terminal electrodes, first and second ground terminal electrodes, first and second signal internal electrodes, and first and second ground internal electrodes. The first signal internal electrode and the first ground internal electrode are arranged so as to be opposed to each other through a part of a dielectric element body. The second signal internal electrode and the second ground internal electrode are arranged to be opposed to each other through a part of the dielectric element body, in an opposed direction of the first signal internal electrode and the first ground internal electrode. The first signal internal electrode and the second ground internal electrode are arranged so as not to overlap each other in the opposed direction of the first signal internal electrode and the first ground internal electrode.

Abstract: A multi-layer ceramic capacitor includes a plurality of dielectric ceramic layers; internal electrodes formed between the dielectric ceramic layers; and end termination electrodes electrically connected to the internal electrodes, wherein the dielectric ceramic layer is a sintered body constituted of a primary component that, when it is expressed by ABO3+aRe2O3+bMnO, satisfies 1.000?A/B?1.035, 0.05?a?0.75 and 0.25?b?2.0; and a subcomponent that includes at least one kind of B, Li or S in the range of 0.16 to 1.6 parts by mass in total in terms of B2O3, Li2O and SiO2; and the internal electrode is constituted of Cu or a Cu alloy.

Abstract: A ferroelectric capacitor including a lower electrode, a ferroelectric layer and an upper electrode. A part of at least any one of the lower and upper electrodes is formed of a material selected from the group consisting of TiOx, TaOx, ReOx, WOx, IrO2, PtO2, RuOx, PdOx, and OsOx.

Abstract: A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor construction can exhibit a lower RC time constant compared to an otherwise identical capacitor construction lacking the layer. Alternatively, or additionally, the first electrode may contain Si and the layer may limit the Si from contributing to formation of metal silicide material between the first electrode and the supporting surface. The layer may be a nitride layer and may be conductive or insulative. When conductive, the layer may exhibit a first conductivity greater than a second conductivity of the first electrode. The capacitor construction may be used in memory devices.

Abstract: A laminated ceramic capacitor has a high breakdown voltage and excellent withstand-voltage performance, and prevents cracks generated during firing even when the number of lamination layers constituted by ceramic layers and inner electrode layers is increased. The laminated ceramic capacitor includes capacitance forming layers in which ceramic dielectric layers and capacitance-forming inner electrode layers are laminated, and a stress relieving layer. The stress relieving layer is disposed between the capacitance forming layers. In the stress relieving layer, ceramic dielectric layers, dummy inner electrode layers (split electrodes) that do not contribute to the formation of electrostatic capacitance, and capacitance-formation-preventing inner electrode layers that prevent capacitance from being formed between the capacitance-forming inner electrode layers and the dummy inner electrode layers are laminated. The thickness of the stress relieving layer is in the range of about 100 ?m to about 300 ?m inclusive.

Abstract: The present invention provides a barium titanate having a small particle size, containing small amounts of unwanted impurities, and exhibiting excellent electric characteristics, which can be employed for forming a dielectric ceramic thin film required for a small-sized capacitor which enables production of a small-sized electronic apparatus; and a process for producing the barium titanate. When a titanium oxide sol is reacted with a barium compound in an alkaline solution containing a basic compound, the basic compound is removed in the form of gas after completion of reaction, and the resultant reaction mixture is fired, a barium titanate having a large BET specific surface area and a high tetragonality content is produced.

Abstract: A monolithic capacitor includes a laminate of ceramic layers, the laminate having first and second surfaces, at least one pair of first and second internal electrodes, first and second external electrodes disposed on the first surface, third and fourth external electrodes disposed on the second surface, a first via conductor that electrically connects the first external electrode to the first internal electrode and to the third external electrode and that contains a metal oxide, and a second via conductor that electrically connects the second external electrode to the second internal electrode and to the fourth external electrode and that contains a metal oxide, wherein, in each of the first and second via conductors, the metal oxide content at an end on the second surface side is higher than the metal oxide content at a center or at an end on the first surface side.

Abstract: A multilayered high performance capacitor formed of two or more conductors with a dielectric layer and one or more a dielectric-conductor interface layer sandwiched in between the conductors. The capacitor may be fabricated using many thin layers, at the nano level, providing a nanocapacitor. The capacitor may employ an interleaved structured where numerous conductor layers are interleaved with other conductor layers. The dielectric layers may be multilayered or a single layer and may consist of materials with high dielectric constants ranging from 800 to over 1 million, including materials in the perovskite-oxide family. The capacitor can be shaped, sized and the appropriate materials selected to obtain breakdown voltages within the range of 0.1 to over 11 MV/cm and to obtain specific energies and energy densities equivalent to or exceeding the power characteristics of known capacitors, fuel cells, and batteries.

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.

Abstract: An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted.

Abstract: A multi-terminal multilayer capacitor reducing an equivalent series inductance (ESL), whose design flexibility is high, in which cost of electrode material is low, and in which a structural defect hardly occurs includes lead portions of first and second internal electrodes and lead portions of third and fourth internal electrodes that are disposed along the length of each of two side surfaces so as to be alternately exposed. Preferably, the first and third internal electrodes, and the second and fourth internal electrodes are disposed so as to be arranged along the length of each side surface in a coplanar manner, with a predetermined distance provided between two internal electrodes.

Abstract: A multilayer capacitor comprises a capacitor body, a first connecting conductor arranged on a first side face of the capacitor body, first and second terminal electrodes, and a first insulator arranged between the first connecting conductor and first terminal electrode. The capacitor body has a plurality of laminated insulator layers and a plurality of first and second inner electrodes. The second terminal electrode is connected to the second inner electrode. Each of the first inner electrodes has a first lead portion exposing an end to the first side face. At least one of the first inner electrodes also has a second lead portion whose end is exposed to the first side face. The first connecting conductor continuously covers all the ends of the first lead portions of the first inner electrodes and mechanically connects with the ends of the first lead portions.

Abstract: In one aspect of the invention, a thin layer capacitor element has a capacitor with a dielectric layer made of a metal oxide and a protective insulating layer made of a resin material, and a barrier layer made of a non-conductive inorganic material is provided between the capacitor and the protective insulating layer. In another aspect of the invention, a thin layer capacitor element is constituted so that a capacitor structure is covered with at least one protective insulating layer composed of a cured resin, the cured resin being formed from at least one resin precursor selected from the group consisting of thermosetting resins, photosetting resins and thermoplastic resins.

Abstract: There are provided a capacitor and a thin film capacitor-embedded multi-layer wiring board. The capacitor includes: first and second electrodes connected to first and second polarities; a dielectric layer formed therebetween; and at least one floating electrode disposed inside the dielectric layer and having overlaps with the first and second electrodes. The wiring board includes: an insulating body having a plurality of insulating layers thereon; a plurality of conductive patterns and conductive vias formed on the insulating layers, respectively, to constitute an interlayer circuit; and a thin film capacitor embedded in the insulating body, wherein the thin film capacitor includes a first electrode layer, a first dielectric layer, at least one floating electrode layer, a second dielectric layer and a second electrode layer sequentially formed, and wherein the first and second electrode layers are connected to the interlayer circuit and the floating electrode layer is not directly connected thereto.

Abstract: A multilayer capacitor 10 of the present invention including: a dielectric body 12 formed by stacking a plurality of dielectric layers 12a; an internal layer portion 17 in which a first and second internal conductor layers 21 and 22 are stacked alternately in the dielectric body 12 via the dielectric layer 12a; external layer portions 19a and 19b in which a first and second external conductor layers 23 and 25 are stacked via the dielectric layer 12a; a first terminal electrode 31 connected with the first internal conductor layer 21 and the first external conductor layer 23, formed at least on a first side face 12A of the dielectric body 12; and a second terminal electrode 32 connected with the second internal conductor layer 22 and the second external conductor layer 25, formed at least on a second side face 12 B opposed to the first side face 12A.

Abstract: The present invention is intended to provide a laminated electronic component having a configuration in which the number of extraction electrodes is reduced to realize a high ESR, the adhesion of a terminal electrode with respect to an ECA is increased and a short-circuit defect between an internal electrode and a dummy electrode can be prevented. An electrode layer in the ECA includes the internal electrode, the extraction electrode and the dummy electrode. One end of the extraction electrode is connected with the internal electrode in the same layer, and the other end of the same is led onto a side surface of the ECA 1 to be connected with the terminal electrode. This is also applied to other extraction electrodes.

Abstract: A multilayer capacitor comprises a capacitor body; first and second inner electrodes alternately arranged in the capacitor body; and a first outer connecting conductor and first and second terminal electrodes arranged on an outer surface of the capacitor body. Each first inner electrode has a first main electrode portion and a first lead electrode portion for connecting the first main electrode portion to the first outer connecting conductor. Each second inner electrode has a second main electrode portion and a second lead electrode portion for connecting the second main electrode portion to at least one second terminal electrode. The capacitor body includes a first inner connecting conductor arranged outside of at least one set of first and second inner electrodes in the opposing direction of the first and second inner electrodes and connected to at least one first terminal electrode and the first outer connecting conductor.

Abstract: A green sheet coating material includes ceramic powder and a binder resin containing a butyral based resin as the main component, which furthermore includes a xylene based resin as a tackifier. The xylene based resin is included in a range of 1.0 wt % or less, more preferably 0.1 or more and 1.0 wt % or less, and particularly preferably more than 0.1 and 1.0 wt % or less with respect to 100 parts by weight of ceramic powder.

Abstract: The monolithic ceramic electronic component includes a first external electrode 5, a second external electrode 6, and a ceramic sintered compact 4 including internal electrodes 2 and 3, the first and second external electrodes 5 and 6 being disposed on both end faces 4a and 4b of the ceramic sintered compact 4. The first and second external electrodes 5 and 6 have a multilayer structure in which sintered electrode layers 5a and 6a, intermediate electroplated layers 5b and 6b, and plated layers 5c and 6c are arranged in that order. Exposed surface regions 7a of insulating oxides 7 are exposed from the outer faces of the sintered electrode layers 5a and 6a, the oxides 7 being derived from a glass frit contained in the sintered electrode layers. Metals 8 are deposited on the exposed surface regions 7a and the intermediate electroplated layers 5b and 6b are then formed by electroplating.

Abstract: A variable IC capacitor includes a semiconductor layer doped to contain mobile charge carriers. Capacitor electrodes C1 and C2 are disposed adjacent to each other on the layer's surface, gate electrodes G1 and G2 are disposed on opposite sides of C1 and C2, and source and sink electrodes are disposed on opposite sides of G1 and G2. Potentials are applied to the electrodes as needed to inject and then confine a finite charge into the region under C1 and C2. A drive voltage V applied between C1 and C2 causes the charge packet to move back and forth beneath them, such that the effective capacitance C seen by drive voltage V is given by C=Q/V, where Q is the magnitude of the charge packet.

Abstract: Crystal grains mainly composed of barium titanate have a mean grain size of not more than 0.2 ?m. The volume per unit cell V that is represented by a product of lattice constant (a, b, c) figured out from the X-ray diffraction pattern of the crystal grains is not more than 0.0643 nm3. Thereby, a dielectric ceramics having high relative dielectric constant can be obtained. A multilayer ceramic capacitor comprises a capacitor body and an external electrode that is formed at both ends of the capacitor body. The capacitor body comprises dielectric layers composed of the dielectric ceramics, and internal electrode layers. The dielectric layers and the internal electrode layers are alternately laminated.

Abstract: A chip-type electronic component includes a ceramic chip body incorporating an element, an external electrode formed on a side surface of the chip body, a conductive elastic resin film which is larger in width than the external electrode and formed to cover the external electrode and extend onto part of a mount surface of the chip body, and a metal plating film for soldering formed on the conductive elastic resin film.

Abstract: A capacitor has stacking capacitor elements, each of which contains a conductor plate, a first band being an insulator and disposed around the plate, a second band being an insulator and disposed around the plate so as to be substantially parallel to the first band, an insulating coating covering a region sandwiched between the first and second bands, a cathode layer formed on the insulating coating, and an anode containing the plate and formed on an outer side of at least one of the first and second bands. The cathode layers are elctrically connected to each other through paths each connecting in series the facing two cathode layers of the adjacent two elements and path(s) connecting in parallel the cathode layers to each other, and the anodes are electrically connected to each other through path(s) connecting in parallel the anodes to each other.

Abstract: An array capacitor is provided. The array capacitor includes a plurality of ground planes inside a dielectric substrate, and a plurality of ground vias. The ground vias electrically connect the ground planes together. Further, the ground vias are connected to ground terminals of the array capacitor to enable electrical coupling between the ground planes and the ground terminals. The array capacitor further includes a plurality of power planes inside the dielectric substrate. The power planes and the ground planes are arranged alternatively inside the dielectric substrate. Each power plane comprises a plurality of power-plane-sections which are mutually electrically isolated. The array capacitor also includes a plurality of power vias which electrically connect the power planes together. Further, the power vias are connected to power terminals of the array capacitor to enable electrical coupling between the power planes and power terminals.

Abstract: A green sheet coating material including ceramic powder, a binder resin including a butyral based resin as the main component, and a solvent. The solvent includes a first solvent medium having a relatively low boiling point, wherein said binder resin is easy to be dissolved, and a second solvent medium having a relatively high boiling point. The boiling point of the second solvent medium is in a range of 130 to 230° C. The second solvent medium is included by 5 to 70 wt %, and more preferably 8 to 52 wt % with respect to 100 wt % of the entire solvent.

Abstract: An apparatus and system, as well as fabrication methods therefor, may include a plurality of vertically-oriented plates separated by dielectric layers, wherein the vertically-oriented plates include a plurality of terminals coupled to a bottom side of the plates.

Abstract: A composite distributed dielectric structure includes one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further formed around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers.

Abstract: The present invention provides the steps of (a) forming a first electrode on a substrate via an adhesion enhancing layer, (b) forming a capacitor insulating film containing a laminated film, in which an amorphous dielectric film and a polycrystalline dielectric film are laminated via a wave-like interface, by forming sequentially and successively the amorphous dielectric film and the polycrystalline dielectric film made of same material on the first electrode, (c) forming a second electrode on the capacitor insulating film, and (d) a step of annealing the capacitor insulating film in an oxygen atmosphere.

Abstract: A capacitor circuit with surge protection that is selectively connected between a voltage source and a device includes a first capacitance element has one end that communicates with a first terminal of the voltage source. A first transistor has a first terminal that communicates with an opposite end of the first capacitance element and a second terminal that communicates with a second terminal of the voltage source. A control terminal of the first transistor communicates with a capacitor enable signal that provides a controlled turn-on to limit current surge and turns off the first transistor when voltage surge is detected.

Abstract: A reduction resistant lead-free and cadmium-free glass composition that is particularly suitable for use in conductive ink applications is disclosed. The invention includes a capacitor, which includes a conductive copper termination. The copper termination is made by firing an ink including a glass component, which may include ZnO, provided the amount does not exceed about 65 mole %; B2O3, provided the amount does not exceed about 61 mole %; and, SiO2, provided the amount does not exceed about 63 mole %. The molar ratio of B2O3 to SiO2 is from about 0.05 to about 3.

Abstract: A multilayer capacitor 1 has a laminated body 20 configured by laminating a plurality of dielectric substrates 2 each having a plurality of internal electrodes 3 and 5 formed on its main surface and a capacitance component is generated between the facing internal electrodes 3 and 5. The dielectric constant of the dielectric substrate located at a central portion of a lamination direction of the laminated body 20 is lower than that of the dielectric substrate 2 located at the edge of the lamination direction.

Abstract: Disclosed is a method of forming individual thin-film capacitors for embedding inside printed wiring boards or organic semiconductor package substrates, which includes removal of selective portions of the capacitor by sandblasting or other means so that the ceramic dielectric does not come in contact with acid etching solutions.

Abstract: A capacitor structure is provided. The capacitor structure is configured in a substrate. The capacitor structure includes a plurality of electrode sets, at least a first conductive plug and at least a second conductive plug. The electrode sets correspond with each other and are disposed in different layers of the substrate. Each electrode set includes a first electrode and a second electrode surrounding the former. In addition, the first conductive plug and the second conductive plug are disposed between two adjacent electrode sets. First electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the first conductive plug. Similarly, second electrodes of two adjacent electrode sets correspond with each other and are electrically connected to each other through the second conductive plug.

Abstract: An assembly includes a semiconductor device having surface-connecting terminals, a substrate having surface-connecting pads, and a capacitor having an approximately plate-shaped capacitor main body having a first surface on which the semiconductor device is mounted and a second surface at which the capacitor main body is mounted on the substrate and a plurality of electrically conductive vias penetrating the capacitor main body between the first and second surfaces and connected to the surface-connecting terminals and the surface-connecting pads.

Abstract: A laminated ceramic capacitor includes a body having an inner layer portion and an outer layer portion and a plurality of terminal electrodes spaced apart from each other in a length direction of the body. The inner layer portion has a plurality of internal electrodes stacked in a height direction of the body. The internal electrodes have led-out portions led out to a side face of the body. The outer layer portion is disposed on one of opposite faces of the inner layer portion in the height direction. The terminal electrodes are each provided with a connecting portion and a spreading portion. The connecting portion extends along the height direction to cover corresponding one of the led-out portions. The spreading portion has a width gradually increasing from one of opposite ends of the connecting portion in the height direction toward an edge of the side face.