Component Within Printed Circuit Board Patents (Class 361/761)
  • Patent number: 7221960
    Abstract: Described is a high-frequency connecting device comprising a first connecting element and a second connecting element which in the connecting position are in electrical contact without engaging into each other, forming a coaxial connection. The first connecting element and the second connecting element each have a respective plurality of separate outer conductors which are arranged at a spacing relative to each other and which are respectively arranged at a spacing around an inner conductor. In the electrical connecting position the mutually facing contact ends of the outer conductors are in touching contact. At the same time the mutually facing contact ends of the inner conductors are in touching contact.
    Type: Grant
    Filed: March 16, 2002
    Date of Patent: May 22, 2007
    Assignee: Audioton Kabelwerk GmbH
    Inventor: Thomas Schlegel
  • Patent number: 7221244
    Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: May 22, 2007
    Assignee: Motorola, Inc.
    Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
  • Patent number: 7218529
    Abstract: A circuit arrangement includes a programmable memory element mounted on a circuit board, with programming contacts of the memory element connected to conductor paths of the circuit board. Data and/or programming codes stored in the memory element determine the functions of the circuit arrangement. To prevent unauthorized reprogramming of the memory element, at least one programming contact of the memory element and each conductor path connected thereto are covered or enclosed, so it is impossible to electrically contact this programming contact or the associated conductor paths without destroying the circuit arrangement. The circuit board is adhesively bonded to a board carrier, with the memory element and conductor paths sandwiched or encased therebetween. The circuit arrangement may be an engine controller for a motor vehicle, with security against unauthorized reprogramming for altering the performance of the engine.
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: May 15, 2007
    Assignee: Conti Temic microelectronic GmbH
    Inventors: Gunther Breu, Hans-Joachim Diehm, Wolfgang Gutbrod, Friedhelm Heinke, Mathias Kuhn
  • Patent number: 7209362
    Abstract: A multilayer ceramic substrate with a cavity includes a multilayer composite member including a plurality of ceramic layers disposed one on another. A cavity is formed in the multilayer composite member such that an opening of the cavity is located in one principal surface of the multilayer composite member. A bottom-surface conductive film is disposed on the bottom surface of the cavity. A capacitor conductive film is disposed in the multilayer composite member such that the capacitor conductive film faces the bottom-surface conductive film via one of the ceramic layers, thereby forming a capacitor.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: April 24, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoya Bando
  • Patent number: 7197818
    Abstract: A method and structures are provided for implementing customizable dielectric printed circuit card traces. A void is defined near selected signal traces. The void is then filled with a dielectric material having a predefined dielectric property. The dielectric material is selected to alter at least one predefined electrical property of the selected signal traces, such as, coupling, propagation delay and attenuation. In one embodiment, an outer layer of a printed circuit card includes a plurality of signal traces and a mating circuit card layer including a plurality of matching signal traces is attached to the outer layer of the printed circuit card to create a cavity near selected signal traces. The cavity is filled with the selected dielectric material. In another embodiment, dielectric material is selectively removed near signal traces on an outer layer of the printed circuit card to define a void near selected signal traces.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Todd Arthur Cannon, William James Csongradi, Jr., Benjamin Aaron Fox, Roger John Gravrok, Mark Kenneth Hoffmeyer, David Lawrence Pease, Ryan James Schlichting
  • Patent number: 7186919
    Abstract: Disclosed herein is a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon. Also, a method of manufacturing the printed circuit board including embedded capacitors is provided.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: March 6, 2007
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Cheol Kim, Min Soo Kim, Jun Rok Oh, Tae Kyoung Kim
  • Patent number: 7180749
    Abstract: A circuit board comprises a base film that is a base layer, a first conductive circuit manufactured by hardening conductive paste material formed in a predetermined shape on the base film, a first insulating layer manufactured by hardening insulating paste material formed on the base film and the first conductive circuit, and a second conductive circuit manufactured by hardening conductive paste material in a predetermined shape on the first insulating layer, wherein an electronic part built-in by the first insulating layer and second insulating layer is connected to the second conductive circuit, and the first conductive circuit is connected to the second conductive circuit through a via hole.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: February 20, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Norihito Tsukahara, Kazuhiro Nishikawa
  • Patent number: 7173192
    Abstract: The invention relates to a position-fixing arrangement for use in printed circuit boards, preferably for mechanically determining the position of optical couplers. According to the invention, hollow cylinders are contained in a printed circuit board, parallel to the surface of the same. Said hollow cylinders are opened with a slit that is cut in from the surface and the inner wall of the cylinders fixes positioning pins of the couplers in place. The invention also relates to a corresponding production process.
    Type: Grant
    Filed: October 9, 2000
    Date of Patent: February 6, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Elmar Griese, Andreas Himmler
  • Patent number: 7167376
    Abstract: A multilayer wiring board on which multiple components are overlappingly mounted. The multilayer wiring board includes: a first surface on which a first component among the multiple components is mounted; and a second surface whose height in a thickness direction of the multilayer wiring board is smaller than that of the first surface, by which a step is provided between the first surface and the second surface, a second component among the multiple components being mounted on the second surface to partially overlap the first component in a non-contact manner, the second surface also having a light-transmitting window through which light is transmitted.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: January 23, 2007
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Mamoru Miyashita, Hiroki Ohta
  • Patent number: 7157647
    Abstract: A circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Patent number: 7157646
    Abstract: A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 2, 2007
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Patent number: 7143929
    Abstract: In the ceramic circuit board, within the through hole of the ceramic substrate is arranged the metal column which is 0 to 150 ?m shorter relative to the thickness of the ceramic substrate; the metal circuit plates are attached to both surfaces of the ceramic substrate to stop up the through hole; and the metal column and the metal circuit plate are bonded together via the brazing material. For its manufacture, the metal column with brazing material is used that is made 40 to 140 ?m longer relative to the thickness of the ceramic substrate by being formed of the metal column which is 0 to 150 ?m shorter relative to the thickness of the ceramic substrate and has its both ends coated with the brazing material.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: December 5, 2006
    Assignee: Kyocera Corporation
    Inventor: Ken Furukuwa
  • Patent number: 7133037
    Abstract: A liquid crystal display of compact size is disclosed. The liquid crystal display has a tape carrier package and a single integrated PCB for processing a gate driving signal and data driving signal. The tape carrier package includes a base substrate, a gate driver IC formed on said base substrate, an input pattern formed on said base substrate that applies gate driving signals input from an external device to the gate driver IC, a first output pattern formed on said base substrate that outputs a first gate driving signal processed in said gate driver IC, and a second output pattern formed on said base substrate, that outputs a second gate driving signal bypassing the gate driver IC among the gate driving signals.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: November 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Soo Kim, Choong-Seob Oh, Jin-Hyeok Park, Jin-Ho Park, Dong-Gyu Kim, Yong-Eun Park, Nam-Soo Kang, Gyu-Su Lee
  • Patent number: 7120077
    Abstract: A memory module includes a plurality of integrated memory components are arranged on a mounting substrate and a refresh control circuit arranged separately from the memory components on the mounting substrate. The output of the refresh control circuit is connected to the plurality of integrated memory components. The refresh control circuit receives and processes address or command signals which have been generated outside the memory module; based on the access information obtained therefrom, independently generates a refresh command or a refresh command sequence for refreshing the contents of memory cells in a selected one of the memory components; and transmits the command or command sequence to the selected memory component. Refresh commands of this type no longer have to be generated by a memory controller.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: October 10, 2006
    Assignee: Infineon Technologies AG
    Inventor: Andreas Jakobs
  • Patent number: 7115988
    Abstract: The present invention provides a heat spreader with a bypass capacitor to provide substantially instant power and/or to control simultaneous switching noise (SSN). The present invention also provides a semiconductor device package incorporating this heat spreader. In addition, fabrication methods for such heat spreaders and packages are provided. Generally, the heat spreaders and packages of the present invention include an embedded bypass capacitor that can provide decoupling capacitance in order to deliver near instant power to the die and/or minimize SSN. In a preferred embodiment, the embedded bypass capacitor is connected to terminals integrated with the heat spreader (e.g., lid; stiffener) and/or to a package plane (e.g., power plane or ground plane) in the package substrate for connection via the flip chip package's power delivery system to a power source and/or component.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: October 3, 2006
    Assignee: Altera Corporation
    Inventor: Vincent Hool
  • Patent number: 7106598
    Abstract: A method for manufacturing a modular electrical circuit includes the steps of pre-manufacturing a plurality of components having fine features such as resistors, capacitors, inductances, and conductors formed on a dielectric substrate. The pre-manufactured components are laminated each to the other in a predetermined order. Each pre-manufactured component includes one or more electrical elements of the same type coupled each to the other by conducting lines. Each dielectric substrate includes through vias filled with the conductive material which serve for cross-coupling of the elements of neighboring components. Position of the passive elements, as well as conductive lines and through vias, are pre-designed to allow precise coordination between the elements of different components in the multi-layered modular electrical circuit.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: September 12, 2006
    Assignee: Potomac Photonics, Inc.
    Inventors: David Liu, Chengping Zhang, Michael T Duignan
  • Patent number: 7102240
    Abstract: An embedded IC packaging structure is disclosed. The embedded IC packaging structure allows a micro-electro-mechanical system (MEMS) having a great number of electrodes to be bonded to another semiconductor device, such as a driver IC, using a secondary substrate, thus ensuring an easy bonding process, providing IC devices capable of executing high-speed signal processing, reducing the production costs, and improving the production yield of the IC devices.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Heung-Woo Park, Jong-Hyeong Song
  • Patent number: 7102874
    Abstract: The present invention describes an intermediate for use in a capacitive printed circuit board (PCB), which relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to reduce inaccuracy of the error compression alignment on laminates. The invention employs a plurality of different sized metal laminates stacked for a built-in capacitor to achieve a high-precise capacitor PCB. More particularly, the invention can raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides precise capacitance to regular circuit design for the need of compact package and high-precise capacitance in the future.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: September 5, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Uei-Ming Jow, Ying-Jiunn Lai, Chun-Kun Wu, Pel-Shen Wei, Chang-Sheng Chen, Ching-Liang Weng
  • Patent number: 7089657
    Abstract: A fixing holder for fixing an electronic component having wire-shaped leg portions to a printed circuit board, the holder being an almost cylindrical-shaped holder for holding the electronic component having the wire-shaped leg portions in a manner that the leg portions pass through and protrude therefrom, the fixing holder comprises: a holder main body portion for holding a main body portion of the electronic component; and a base portion continuously provided to the holder main body portion, wherein one surface of the base portion on a forward side is opened to form an opening, at least a portion of periphery of the opening is configured to form a flat surface, and a side surface of the holder main body portion on a side where the opening is formed is protruded forward to form an engagement nail portion to be engaged with the printed circuit board.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: August 15, 2006
    Assignee: Funai Electric Co., Ltd.
    Inventor: Koukichi Masumoto
  • Patent number: 7075179
    Abstract: The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: July 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Julie L. Beatty, Kalyan Doddapaneni
  • Patent number: 7057114
    Abstract: A circuit board includes two planes. A via spans the planes, and an impedance component is placed in the via. The impedance component is coupled to both of the planes. The impedance component provides an impedance between the planes without the use of traces or hand soldering of components.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Terry Dishongh, Prateek Dujari, Bin Lian, Damion Searls
  • Patent number: 7058365
    Abstract: A disposable cellular telephone and business card combination. The cellular telephone circuit is printed on a paper substrate with a conductive ink. A paper microphone diaphragm is attached to one end of the business card and a paper speaker diaphragm is attached to an opposite end of the business card. The microphone and speaker diaphragms are electrically coupled to the circuit, and are attached to the paper substrate in any suitable manner that allows them to vibrate relative thereto. A thin flexible battery cell is formed in the paper substrate at any suitable location so that it doesn't interfere with the position of the circuit, microphone or speaker. A filament antenna is formed in the business card so that it can be extracted therefrom when using the card as a cellular telephone. A switch is provided on the business card that when activated causes a predetermined number to be dialed associated with the text on the business card.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: June 6, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Brett E. Kugler
  • Patent number: 7045901
    Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: May 16, 2006
    Assignee: Megic Corporation
    Inventors: Mou-Shiung Lin, Bryan Peng
  • Patent number: 7045719
    Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: May 16, 2006
    Assignee: NCR Corp.
    Inventors: Arthur R. Alexander, James L. Knighten, Jun Fan
  • Patent number: 7034231
    Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: April 25, 2006
    Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
  • Patent number: 7006359
    Abstract: A modular electronic assembly and a method for making a modular electronic assembly are disclosed. The subject modular electronic assembly is constructed in such a way as to maximize available surface area on printed wiring boards by incorporating pretested discrete passive elements within the body of such printed wiring boards and electrically connecting the elements in a volume-efficient manner. A modular electronic assembly constructed according to the presently disclosed subject matter is formed by arranging a plurality of diverse, pretested passive components between a plurality of copper and tacky epoxy sheets, holding the passive components in place by an epoxy resin layer and electrically connecting the components together by electrical vias penetrating the tacky epoxy layers.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: February 28, 2006
    Assignee: AVX Corporation
    Inventors: John L. Galvagni, George Korony
  • Patent number: 6998861
    Abstract: A circuit board for surface mounting by solder flow an electronic component having narrow lead pitches, the board having a first solder leading land having a first side and located on the circuit board adjacent to a land for mounting an electronic component, and a second solder leading land located next to the first solder leading land and opposite the first side of the first solder leading land. A method for flow soldering a surface mounted electronic component on such a circuit board, wherein the second solder leading land is positioned at a rear end of the circuit board against a direction of a movement of the circuit board when the circuit board moves toward a solder flow.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Inc.
    Inventors: Mitsuhisa Nakai, Keiichi Kuriyama, Akihiro Kyogoku, Yoshinao Nakamoto, Koji Taniguchi, Hiroaki Higashi
  • Patent number: 6992375
    Abstract: An anchor to hold getter materials in place within a micromechanical device package substrate. First and second cavity faces define an anchor cavity and mechanically retain a getter away from a region holding the micromechanical device. The getter anchor may be formed in a substrate comprised of at least three layers. The layers form a cavity in the substrate with a wide bottom portion—formed in the middle layer and a relatively narrower top portion—formed by the top layer. The narrow portion helps to retain the getter in the cavity by creating a mechanical lock on the wide portion of getter in the bottom of the cavity.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 31, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Roger A. Robbins, Jwei Wien Liu, Jack C. Smith, Edward Carl Fisher, Joyce Wong Holton
  • Patent number: 6977820
    Abstract: An electronic circuit board having an optical wiring layer sandwiched between two electrical wiring layers. The optical wiring layer is structured to be a two-dimensional optical waveguide. An E/O device and an O/E device are provided in the optical wiring layer or at an interface between the optical wiring layer and the electrical wiring layer. A via piercing the optical wiring layer connects the two electrical wiring layers. It is possible to efficiently input and output light to and from an optical wiring layer.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: December 20, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Mamoru Uchida
  • Patent number: 6975516
    Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yasuhiro Sugaya, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani
  • Patent number: 6971162
    Abstract: An exemplary system and method for providing differential adjustment of the height of a multilayer substrate in localized areas for improved Q-factor performance of RF devices is disclosed as comprising inter alia: a multilayer substrate (200); an RF component (210) embedded in the substrate (200); a surface mounted component (220); and an RF shield (260) disposed next to the surface mounted component (220), wherein the height of the shield (260) does not extend substantially beyond the height of the surface mounted component (220). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize Q, RF performance and/or material characteristics.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: December 6, 2005
    Assignee: Motorola, Inc.
    Inventors: John C. Estes, Rodolfo Lucero, Anthony M. Pavio
  • Patent number: 6972964
    Abstract: A module board has embedded chips and components. A substrate has at least one large cavity and at least one small cavity, in which the large cavity passes through the substrate and a passive component is set in the small cavity. A heat-dissipation sheet is set at the bottom of the substrate. A first adhesion layer bonds the bottom of the substrate to the heat-dissipation sheet. At least one IC chip is fixed in the large cavity of the substrate by a second adhesion layer. A dielectric filling layer covers the entire surface of the module board and fills all gaps, in which the dielectric filling layer has a plurality of micro vias to expose partial areas of the IC chip, the passive component and the substrate. At least one wiring pattern layer is formed on the dielectric filling layer and provide electrical connection among the IC chip, the passive component, and the substrate.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: December 6, 2005
    Assignee: Via Technologies Inc.
    Inventors: Kwun-Yao Ho, Moriss Kung
  • Patent number: 6972488
    Abstract: A semiconductor device includes (a) a printed wiring board, (b) a semiconductor chip mounted on the printed wiring board, (c) a molded resin formed on the printed wiring board, covering the semiconductor chip therewith, and (d) at least one metal wiring formed on the printed wiring board and extending externally beyond the molded resin. The metal wiring is plated with a metal having a small adhesion force with the molded resin. An interfacial surface between the metal and the molded resin acts as a path through which moisture contained in the semiconductor device escapes outside when the semiconductor device is heated.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: December 6, 2005
    Assignee: NEC Compound Semiconductor Devices, Ltd.
    Inventors: Taibo Nakazawa, Hiroyuki Kimura
  • Patent number: 6973330
    Abstract: According to one embodiment of the invention, a compact wireless modem card placement in compliance with thickness requirement of type II PCMCIA standard and type II Compact Flash form factor standard is provided which includes a first side and a second side. The first side has a height clearance of approximately 2 mm. The second side, which is opposite the first side, has a height clearance of approximately 1.45 mm. In one embodiment, those components with a height greater than 1.4 mm are placed on the first side of the card. The first side of the card includes a radio-frequency transmitter (RFT) chip located at the lower left of the first side. The RFT chip performs signal processing functions to up-convert baseband signals received from a mobile station modem (MSM) chip to radio-frequency signals. The first side also includes a radio-frequency (RF) surface acoustic wave (SAW) filter located above and to the left of the RFT chip.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: December 6, 2005
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Christopher Peter Wieck
  • Patent number: 6964884
    Abstract: A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: November 15, 2005
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, John M. Lauffer
  • Patent number: 6963034
    Abstract: An inductor device having plural spiral-shaped interconnection structures connected to each other and extending in plural power source layers, the power source layers being in different levels of a multilayer printed board. The printed board having first and second current loops. The loops share part of a common current path.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: November 8, 2005
    Assignee: NEC Corporation
    Inventor: Mizuki Iwanami
  • Patent number: 6963493
    Abstract: A method of using blind via to house electronic components within an electrical device is provided. Such a method allows for the vertical orientation of various types of passive components within a layer of a printed circuit board (PCB) or an integrated passive device (IPD). One exemplary embodiment of the method provides for the passive component's electrical connection between an embedded ground and another device on the surface of the PCB. By virtue of its component positioning, such a method reduces the space demands placed upon the surface of the PCB, enhances the flexibility of circuitry design, and allows for a greater variety of passive components and integral passive devices to be utilized within the PCB itself. Another exemplary embodiment of the method provides for greater flexibility in the design and manufacture of IPDs by allowing for the vertical electrical connection of various passive components through the placement of intervening passive components into via.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: November 8, 2005
    Assignee: AVX Corporation
    Inventor: John L. Galvagni
  • Patent number: 6954362
    Abstract: A system and method for reducing an apparent height of a board system are provided. The board system may include, for example, a carrier, a component, a printed circuit board and/or a solder material. The component is mounted on a first side of the carrier. The printed circuit board has a hole that is structured to accommodate the component. The solder material solders the carrier to the printed circuit board and provides a structural bond between the carrier and the printed circuit board. At least one portion of the solder material provides an electrical coupling between the carrier and the printed circuit board and at least one portion of the component is maintained in the hole after the carrier is soldered to the printed circuit board.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: October 11, 2005
    Assignee: Kyocera Wireless Corp.
    Inventor: Paul Aurelio Martinez
  • Patent number: 6945827
    Abstract: An elongate, columnar micro-mechanical structure disposed along a central longitudinal axis; the structure is made up of laminated structural layers, each comprised of a structural material. The layers define a substantially rigid base portion at a proximal end of the structure, a resilient intermediate portion extending from the base portion along the central axis, and a contact tip extending from the resilient portion at a distal end of the structure. The resilient portion of the contact structure is comprised of resilient arms defined in the layers. Opposite ends of the resilient arms may be angularly offset with respect to one another around the central axis. Accordingly, when the contact structure is compressed in an axial direction, the contact tip will rotate around the central axis, while the base remains fixed, providing beneficial wiping action to the contact tip.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 20, 2005
    Assignee: FormFactor, Inc.
    Inventors: Gary W. Grube, Gaetan L. Mathieu, Alec Madsen
  • Patent number: 6944030
    Abstract: A substrate has an electrical wiring pattern formed thereon, one or a plurality of electrical parts provided thereon, a first contacting part and a second contacting part provided thereon and electrically connected to the electronic parts, and one or a plurality of electrical connecting bodies. The electrical connecting bodies are different from the electrical wiring pattern, and electrically connect the first contacting part and the second contacting part.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: September 13, 2005
    Assignee: Fujitsu Limited
    Inventor: Hiroshige Nakayabu
  • Patent number: 6940013
    Abstract: A power converter includes electrical contacts arranged on a first surface and a connection device. The converter has a top surface above the first surface and a bottom surface below the first surface. A border of the bottom surface is inset from a border of the second surface. The connection device includes a pair of conductive legs, each leg comprising a first end and a second end. The pair of legs lie opposite each other in a pair of evenly spaced planes that intersect the first surface. The first ends are adapted to connect to one or more of the contacts on the first surface and the second ends are adapted to connect to one or more conductive pads on a surface of a substrate. The connection device is adapted to enable the first ends of the two legs to connect to the contacts from below the first surface.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: September 6, 2005
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Jay Prager, Michael B. LaFleur
  • Patent number: 6937478
    Abstract: A low profile circuit device for the LCD module comprises a printed circuit board and an electronic device. The printed circuit board has a through hole and a plurality of pads surrounding the through hole. The electronic device is disposed within the through hole and has a plurality of leads electrically connected to and mounted on the plurality of pads of the printed circuit board.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: August 30, 2005
    Assignee: Hannstar Display Corp.
    Inventors: Chi Tien Lee, Jiunn Yau Huang
  • Patent number: 6921868
    Abstract: A cavity is formed in a multilayer substrate at the point of the structure to be trimmed. This enables the embedding of tolerance critical components inside substrates, such as printed circuit boards, modules, and sub-systems. Trimming is done through the cavity using, for example, a laser. After trimming the cavity is easy to fill in with a suitable dielectric material or to cover otherwise, e.g. by using a lid, or to leave the cavity uncovered.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: July 26, 2005
    Assignee: Nokia Corporation
    Inventors: Olli Salmela, Iipo Kokkonen
  • Patent number: 6922143
    Abstract: A serial bus type configuration recognition and alarm apparatus for a system having a plurality of various boards. The apparatus includes a plurality of first transmission units, a second transmission unit and a recognition unit. The first transmission units report board Identifications (IDs) and board failure status information through a first serial bus. The second transmission unit is connected to the first transmission units to report the board IDs, the board failure status information and an ID thereof. The recognition unit is connected to the second transmission unit to ascertain the configuration and failure status of the boards and report received board IDs and board failure status to a terminal.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: July 26, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Eui Suk Jung, Byoung Whi Kim, Hyeong Ho Lee
  • Patent number: 6918178
    Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: July 19, 2005
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shin-Hua Chao, Shyh-Ing Wu, Kuan-Neng Liao, Gin-Nan Yeh
  • Patent number: 6910894
    Abstract: A manual for teaching and/or demonstrating the assembly and/or operation of a transmittable energy circuit, wherein the manual has a base hinged to a plurality of pages for folding the pages over or away from the base, wherein at least one of the pages has conductor portions of an energy circuit thereon, and wherein the portions are provided with electrical connectors for receiving one or more electrical components adapted for completing the circuit, and wherein at least one of the pages has instructions thereon for so completing said circuit.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 28, 2005
    Inventor: Edward A. Basconi
  • Patent number: 6906411
    Abstract: In a multi-layer substrate module receiving from an external earth node supply of a reference potential for grounding, a plurality of ground lines are provided respectively corresponding to a plurality of internal circuits. Moreover, a common node for coupling the ground lines is provided in an insulating layer of the multi-layer substrate module. The common node is electrically coupled to the earth node through a ground pin terminal shared by the plurality of internal circuits. Preferably, the common node is provided in the lowest insulating layer of the multi-layer substrate module. Thus, parasitic inductance of the portion through which an earth current flows, that is, the portion common to the plurality of internal circuits, can be suppressed with a small number of ground pin terminals. Accordingly, the inflow phenomenon of the earth current between the plurality of internal circuits is prevented, enabling stable operation.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: June 14, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takatoshi Katsura, Kenji Itoh, Hiroaki Nagano, Youji Isota, Mitsuhiro Shimozawa, Tadashi Takagi, Noriharu Suematsu, Masayoshi Ono, Kenichi Maeda
  • Patent number: 6906928
    Abstract: The electronic component has a semiconductor chip mounted to a wiring board. The chip is bonded to the wiring board with adhesive strips that leave free a through-cutout, an additional cutout, and separating joints. The additional cutout provides for a plastic reservoir from which the separating joint between the adhesive strips is filled with plastic material.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: June 14, 2005
    Assignee: Infineon Technologies AG
    Inventors: Christian Hauser, Martin Reiss
  • Patent number: 6891731
    Abstract: A technique has been developed whereby crosstalk induced in a first electrical connection by current flow at an adjacent second electrical connection is at least partially cancelled by an opposing crosstalk signal induced at an inductive coupling between electrical traces extending from or toward the first and second electrical connections, respectively. Crosstalk cancellation is provided by orienting the electrical traces such that current flow through the second electrical connection and respective electrical trace induces an opposing crosstalk signal at the inductive coupling. In some configurations, an inductive coupling between electrical traces includes essentially parallel portions of the traces and an aperture in a voltage plane. In some configurations, cancellation of crosstalk induced by multiple adjacent electrical connection is provided. Crosstalk inducing electrical connections include pins, solder bumps, leads, wires, edge connectors, etc.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: May 10, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dennis James Herrell
  • Patent number: 6891239
    Abstract: An integrated sensor and electronics package wherein a micro-electromechanical sensor die is bonded to one side of the package substrate, one or more electronic chips are bonded to an opposite side of the package substrate, internal electrical connections run from the sensor die, through the package substrate, and to the one or more electronic chips, and input/output connections on the package substrate are electrically connected to one or more of the electronic chips.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: May 10, 2005
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Richard S. Anderson, James H. Connelly, David S. Hanson, Joseph W. Soucy, Thomas F. Marinis