Component Within Printed Circuit Board Patents (Class 361/761)
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Publication number: 20090086450Abstract: A printed circuit board is disclosed. The printed circuit board includes an insulation layer and a conductor layer having a GND pattern. The printed circuit board has a center portion, to which an element is to be mounted. The printed circuit board has a periphery portion and a slit pattern separating the periphery portion from the center portion. The GND pattern extends through the center portion and the periphery portion.Type: ApplicationFiled: October 2, 2008Publication date: April 2, 2009Applicant: DENSO CORPORATIONInventor: Yuusuke Matsui
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Patent number: 7511940Abstract: Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.Type: GrantFiled: August 15, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Natalie B. Feilchenfeld, Michael L. Gautsch, Zhong-Xiang He, Matthew D. Moon, Vidhya Ramachandran, Barbara Waterhouse
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Publication number: 20090080168Abstract: A printed circuit board includes a mounted a first electronic component. The printed circuit board includes a first through holes extending from a mounting surface on which the electronic component is mounted The printed circuit board includes a second through holes extending from a surface opposite the mounting surface and aligned with the first through holes. A second electronic component may be longitudinally between the first through holes and the second through holes. The first and second through holes may be electrically connected with the second electronic component.Type: ApplicationFiled: August 27, 2008Publication date: March 26, 2009Applicant: Fujitsu LimitedInventor: Shigeru SUGINO
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Patent number: 7505283Abstract: The metal-core-board reinforcing structure has a metal core board having a metal core and a resin plate having substantially the same extent as that of the metal core board and being fixedly attached to the metal core board substantially parallel to one side of the metal core board and spaced apart therefrom by a predetermined distance.Type: GrantFiled: September 28, 2007Date of Patent: March 17, 2009Assignee: The Furukawa Electric Co., Ltd.Inventors: Fumikazu Naimi, Masami Takase, Akihisa Watanabe
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Patent number: 7505282Abstract: A multilayer circuit board has a bottom and an upper multilayer circuit boards, a glue layer, multiple outer contact vias and two insulating lacquer layers. The bottom and the upper multilayer circuit boards respectively have multiple conductive wires, an insulating layer, a frame, multiple chips, a press laminate, a patterned conductive layer and at least one inner contact via. The glue layer sticks the bottom and the upper multilayer circuit boards together. The multiple contact vias are formed through the bottom and the upper multilayer circuit boards to electronically interconnect the conductive wires and the patterned conductive layers in the bottom and the upper multilayer circuit boards. The insulating lacquer layers are respectively coated under and on portions of the patterned conductive layers in the bottom and the upper multilayer circuit boards to protect the patterned conductive layers, wherein the un-coated patterned conductive layers become multiple contacts.Type: GrantFiled: October 31, 2006Date of Patent: March 17, 2009Assignee: Mutual-TEK Industries Co., Ltd.Inventor: Roger Chang
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Patent number: 7495929Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.Type: GrantFiled: September 20, 2007Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Kok-Siang Ng, King Keong Wong, Michael E. Ryan
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Publication number: 20090046418Abstract: An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, and a voltage regulator electronically connected to the first slot and the second slot. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.Type: ApplicationFiled: December 7, 2007Publication date: February 19, 2009Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: CHUN-SHENG CHEN, SHOU-KUO HSU, CHENG-SHIEN LI, DUEN-YI HO, YU-CHANG PAI
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Publication number: 20090046440Abstract: The present invention describes methods for enhancing the performance of two-capacitor low-pass filters. In certain embodiments of the invention, the capacitors are placed on opposite sides of a PCB board.Type: ApplicationFiled: August 18, 2008Publication date: February 19, 2009Inventor: Cheung-Wei Lam
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Patent number: 7491896Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.Type: GrantFiled: January 18, 2008Date of Patent: February 17, 2009Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
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Patent number: 7488897Abstract: A hybrid multilayer substrate includes a cavity in a laminate structure formed of a resin portion and a ceramic multilayer substrate, the resin portion has a protrusion portion, the ceramic multilayer substrate has a penetrating hole, and the cavity is formed by fitting the protrusion portion of the resin portion to an end portion of the penetrating hole of the ceramic multilayer substrate.Type: GrantFiled: April 12, 2007Date of Patent: February 10, 2009Assignee: Murata Manufacturing Co., Ltd.Inventors: Nobuaki Ogawa, Yoshihiko Nishizawa
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Patent number: 7488895Abstract: A component built-in module of the present invention includes: a first wiring pattern; an electronic component mounted on the first wiring pattern; a second wiring pattern; an electrical insulating sheet with the electrical component built therein, the electrical insulating sheet being disposed between the first wiring pattern and the second wiring pattern; and a via conductor formed in a via hole penetrating through the electrical insulating sheet, the via conductor connecting electrically the first wiring pattern and the second wiring pattern. A side face of the via conductor defines a continuous line in an axis direction of the via conductor. Thus, a component built-in module having excellent reliability concerning electrical connection can be provided.Type: GrantFiled: September 27, 2004Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Yoshitake Hayashi, Masayoshi Koyama, Satoru Yuhaku, Kazuo Otani, Susumu Matsuoka, Yasushi Taniguchi, Seiichi Nakatani
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Patent number: 7485489Abstract: A circuit with embedding components (13) is produced by placing the components (13) on a substrate (14) and applying sheets (15) of prepreg. The prepreg sheets (15) have apertures to accommodate the -components, the number of sheets and arrangement of apertures being chosen to accommodate a variety of component X, Y and Z dimensions. A top layer with Cu foil (16(b)) is applied. The assembly is pressed in an operation analogous to conventional multilayer board lamination pressing. This causes all of the prepreg resin to flow to completely embed the components without raids or damage. Electrical connections are made by drilling and plating vias.Type: GrantFiled: December 16, 2004Date of Patent: February 3, 2009Inventor: Sten Björbell
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Patent number: 7486525Abstract: A temporary chip attach carrier for and a method of testing an integrated circuit chip. The carrier includes: a substrate, a first array of interconnects disposed on a bottom surface and a second array of interconnects disposed on a top surface of the substrate, corresponding interconnects of the first and second arrays of interconnects electrically connected by wires in the substrate; an interposer, a first array of pads disposed on a top surface of the interposer and a second array of pads disposed on a bottom surface of the interposer, corresponding pads of the first and second arrays of pads electrically connected by wires in the interposer, and pads of the second array in direct physical and electrical contact with corresponding interconnects of the second set of interconnects; and wherein the interposer includes an interposer substrate of the same material as a substrate of the integrated circuit chip.Type: GrantFiled: August 4, 2006Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventor: John Ulrich Knickerbocker
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Patent number: 7483277Abstract: A component is mounted in a component mounting position on a component mounting-side surface of an inspection-use board which is formed from a light transmitting material and which has a reflecting surface disposed on a surface opposed to the component mounting side-surface and facing the component mounting side-surface. Light is applied to the component mounting-side surface of the inspection-use board. The applied light is transmitted through the component mounting-side surface and reflected on the reflecting surface so that an image of an outline of the component formed by reflected light coming from around the component through the component mounting-side surface is picked up. A component mounting accuracy is calculated based on the image.Type: GrantFiled: March 8, 2005Date of Patent: January 27, 2009Assignee: Panasonic CorporationInventor: Kazunobu Sakai
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Patent number: 7480150Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41.Type: GrantFiled: December 22, 2006Date of Patent: January 20, 2009Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Akira Mochida
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Patent number: 7479604Abstract: At least one flexible appliance (120) and related method (300) for orthogonal, non-planar interconnections of at least a first electronic interface (115) disposed on a substrate (110) to an associated second electronic interface (161) positioned beneath the substrate (110). The flexible appliance (120) is comprised of a planar body (121) having at least one electrical connector (122) extending from and orthogonally oriented relative to the planar body (121). In one aspect of the invention, the electrical connector (122) is four electrical connectors (122). There is at least one aperture (112) formed in the substrate (110) for allowing the first electronic interface (115) to be electrically interconnected to the associated second electronic interface (161). The flexible appliance (120) is positioned on the substrate (110) by automated means.Type: GrantFiled: September 27, 2007Date of Patent: January 20, 2009Assignee: Harris CorporationInventors: Brian Smith, Hector Deju, Scott Burri, Larry E. Crider, Joseph Kreuzpaintner, Gregory M. Jandzio, Walter M. Whybrew
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Patent number: 7480151Abstract: A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area.Type: GrantFiled: December 10, 2007Date of Patent: January 20, 2009Assignee: Dai Nippon Printing Co., Ltd.Inventor: Yoichi Miura
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Patent number: 7477523Abstract: A semiconductor device has at least a square wiring board having a board core made of an insulating material, wires made of a metal and formed on a first surface of the board core, a solder resist film formed on the first surface to cover the wires, and openings formed by partially opening the solder resist film, wherein a plurality of the elongated wires are arranged in parallel on the bottom of the openings, a semiconductor chip having electrodes flip chip connected to the wires are arranged on the bottom of the openings of the wiring board through a conductive bonding material, and an insulating resin is provided for filling an interstice between the wiring board and the semiconductor chip, wherein the wires extend along a width direction orthogonal to a longitudinal direction of the openings, the openings comprise elongated grooves which extend along at least two opposing sides of the square of the wiring board, a pair of opposing edges of the opening along the longitudinal direction define zig-zag edgesType: GrantFiled: February 23, 2007Date of Patent: January 13, 2009Assignee: Elpida Memory, Inc.Inventor: Daisuke Tsuji
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Publication number: 20090009956Abstract: A case of an electronic device and an interface card retaining assembly thereof are used for retaining interface cards in the case. A circuit board is disposed in the case, and the circuit board has at least one expansion slot. The interface card retaining assembly includes an interface card cradle and a functional expansion card. The interface card cradle is pivoted to the case, for swinging relative to the case. The functional expansion card is mounted to the interface card cradle, and when the interface card cradle leans against the circuit board, the functional expansion card is inserted into the expansion slot of the circuit board, so as to electrically connect to the circuit board.Type: ApplicationFiled: July 3, 2007Publication date: January 8, 2009Applicant: INVENTEC CORPORATIONInventor: Quie-Wau CHEN
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Patent number: 7453705Abstract: A protective layer for an electronic device and devices with a protective layer. In one exemplary embodiment, the protective layer includes two different layers which can be etched by the same etchant as which are at least one of optically or RF transparent.Type: GrantFiled: October 13, 2006Date of Patent: November 18, 2008Assignee: Alien Technology CorporationInventor: Zhidan L. Tolt
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Patent number: 7453702Abstract: A printed wiring board comprises the insulating layer 11 (12); at least one resistance element 311 (312) comprising a metal as a main component has 0.5 to 5 ?m of a roughened surface in an arithmetic means height in the one surface, in ?Z direction, and 5% to 50% of the arithmetic mean height in average thickness, which is embedded close to a surface on one side of the insulating layer 11 and a conductive pattern wired surface is composed of the one surface of the resistance element and the one side of the insulating layer 11; and the conductive pattern 351 (352), arranged on the conductive pattern wired surface, is connected to the terminal of the resistance element 311 (312). With this structure, it is provided the printed wiring board comprising the resistance element having an accurate and stable resistance value in a broader resistance value range.Type: GrantFiled: October 20, 2005Date of Patent: November 18, 2008Assignee: Ibiden Co., Ltd.Inventors: Kiyotaka Tsukada, Toshimasa Iwata, Terumasa Ninomaru, Takamichi Sugiura
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Publication number: 20080278921Abstract: Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts.Type: ApplicationFiled: May 6, 2008Publication date: November 13, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Mu-Seob SHIN, Min-Young SON, Tae-Sung YOON, Young-Hee SONG, Byung-Seo KIM
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Patent number: 7450393Abstract: A driver chip includes a base body having a driver circuit formed therein. A plurality of conductive bumps is disposed over a top face of the base body, the plurality of conductive bumps being arranged in a plurality of rows along the longitudinal direction of the base body. A plurality of conductive wirings is formed over the top face of the base body that electrically connects the driver circuit to the plurality of conductive bumps.Type: GrantFiled: June 30, 2004Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Yong Hwang, Weon-Sik Oh, Sung-Lak Choi, Chun-Ho Song, Ju-Young Yoon
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Patent number: 7450395Abstract: A circuit module includes connection electrodes on a plate-shaped board and connection electrodes on a frame-shaped board that are bonded together with conductive bonding materials there between. Circuit components are provided in portions of a surface of the plate-shaped board, the portions being located inward relative to the frame-shaped board. A sealing resin is filled and cured in a cavity, which is defined by the frame-shaped board and the plate-shaped board. Since the center of each of the connection electrodes on the frame-shaped board is inwardly displaced relative to the center of a corresponding one of the connection electrodes on the plate-shaped board by ?, a curing contraction stress of the sealing resin is mitigated by a curing contraction stress of the conductive bonding materials. Thus, deformation of the frame-shaped board is suppressed.Type: GrantFiled: April 10, 2008Date of Patent: November 11, 2008Assignee: Murata Manufacturing Co., Ltd.Inventor: Norio Sakai
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Publication number: 20080273313Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.Type: ApplicationFiled: March 28, 2008Publication date: November 6, 2008Inventors: Yung-Hui Wang, In-De Ou, Chih-Pin Hung
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Publication number: 20080266822Abstract: An electronic elements carrier includes a body, at least an electronic element and a filler. The body includes a substrate having a plate and a dam formed on the peripheral of plate, a conductive layer mounted on a surface of the dam, and at least a cavity defined by the plate and the dam of the substrate. The electronic element is disposed in the cavity of the body. The filler is received in the cavity of the substrate for encapsulating, sealing and protecting the electronic element.Type: ApplicationFiled: November 30, 2007Publication date: October 30, 2008Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: YING-CHENG WU, KUN-HSIAO LIU
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Patent number: 7441329Abstract: A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material layer is formed on the first surface. A circuit unit including second through holes is provided. Locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the circuit unit are aligned by the first through holes and the second through holes, while the first surface of the conductive layer faces the circuit unit, and the passive component material layer is between the circuit unit and the conductive layer. The conductive layer is laminated to the circuit unit. The conductive layer is patterning to form a circuit layer.Type: GrantFiled: June 3, 2005Date of Patent: October 28, 2008Assignee: Subtron Technology Co. Ltd.Inventor: Shih-Lian Cheng
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Patent number: 7440290Abstract: The present invention provides systems, devices and methods for controlling a desired output of an output device. These systems, devices and methods include connecting an electrical resistance element having a selected one of a plurality of resistance values with an electrical circuit portion having a plurality of electrical components, determining an electrical characteristic associated with the connected electrical circuit portion and the variable resistance element, and generating a control signal based on the electrical characteristic to control the desired output of the output device.Type: GrantFiled: May 17, 2004Date of Patent: October 21, 2008Assignee: QUALCOMM IncorporatedInventors: Michael G. Matthews, Kevin Cousineau, Scott C. Asbill
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Patent number: 7435912Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.Type: GrantFiled: May 14, 2002Date of Patent: October 14, 2008Assignee: Teradata US, Inc.Inventors: Arthur R. Alexander, James L. Knighten, Jun Fan
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Patent number: 7435911Abstract: Disclosed is a PCB including an embedded capacitor and a method of fabricating the same. The long embedded capacitor is formed through an insulating layer, making a high capacitance and various capacitance designs possible.Type: GrantFiled: March 31, 2005Date of Patent: October 14, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Young Woo Kim, Byoung Youl Min, Chang Myung Ryu, Woo Lim Chae, Han Kim
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Patent number: 7436678Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.Type: GrantFiled: October 18, 2004Date of Patent: October 14, 2008Assignee: E.I. du Pont de Nemours and CompanyInventor: David Ross McGregor
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Patent number: 7433202Abstract: The electronic device comprises a body (40) of electrically insulating material that is provided with a through-hole or cavity. In the cavity or through-hole an electric component (20) is present. This component is attached to the body through an attachment layer (13). The surface of this attachment layer is provided with a pattern of electrical conductors for electrically coupling the component to other components and/or contact means for external coupling. At least one of which electrical conductors extends to a surface of the body.Type: GrantFiled: October 11, 2004Date of Patent: October 7, 2008Assignee: Koninklijke Philips Electronics N.V.Inventors: Vincent Johannes Jacobus Van Montfort, Fransiscus Gerardus Coenradus Verweg, Roel Henri Louis Kusters
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Patent number: 7432816Abstract: A printed circuit board (PCB) includes an antenna for an RFID chip. An RFID chip for a tag is operable to be placed on the PCB such that the RFID chip is connected to the antenna and is operable to use the antenna to transmit data.Type: GrantFiled: October 13, 2005Date of Patent: October 7, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Joseph Ku, Geoff Lyon, Salil Pradhan
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Patent number: 7430127Abstract: An electronic circuit board having an optical wiring layer sandwiched between two electrical wiring layers. The optical wiring layer is structured to be a two-dimensional optical waveguide. An E/O device and an O/E device are provided in the optical wiring layer or at an interface between the optical wiring layer and the electrical wiring layer. A via piercing the optical wiring layer connects the two electrical wiring layers. It is possible to efficiently input and output light to and from an optical wiring layer.Type: GrantFiled: November 18, 2005Date of Patent: September 30, 2008Assignee: Canon Kabushiki KaishaInventor: Mamoru Uchida
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Publication number: 20080232074Abstract: A method for assembling a circuit card assembly includes populating a plurality of components on a top side of a component layer, performing component-level testing on at least one component of the plurality of components populated on the component layer, adhering a bonding layer to a bottom side of the component layer, the bonding layer to facilitate bonding the component layer to an interconnect layer and to provide connectivity between the plurality of components and the interconnect layer, and forming a single-sided circuit card assembly by adhering the interconnect layer to the bonding layer, the interconnect layer having a top side and a bottom side, the bonding layer adhered to the top side of the interconnect layer.Type: ApplicationFiled: March 20, 2008Publication date: September 25, 2008Applicant: VIASAT, INC.Inventors: Robert Lee Schutz, Howell B. Schwartz, Conrad Claire Grell, Angie Sheelan Ng, Gregory Scott Girkins
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Patent number: 7423884Abstract: A multilayer circuit board includes: two or more layers of electrical insulative base members; and two or more layers of conductive patterned layers. At least two of the conductive patterned layers include coil patterns that will be a part of a coil, through holes are provided at predetermined positions of the electrical insulative base members, the positions being sandwiched between the coil patterns, so as to enable communication between respective end portions of the coil patterns, and conductive paste charged in the through holes allows electrical connection to be established between the respective end portions. The coil is formed so as to be wound in a direction perpendicular to a thickness direction of the multilayer circuit board. With this configuration, a multilayer circuit board can be provided, which facilitates increasing the winding number of a coil and has excellent flexibility of circuit design.Type: GrantFiled: March 14, 2005Date of Patent: September 9, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kouhei Enchi, Yoji Ueda
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Publication number: 20080212287Abstract: A semiconductor package structure and manufacturing method thereof are provided, wherein the semiconductor package structure comprises a multi-layer circuit board, an electronic device and a slug. The multi-layer circuit board has at least one via hole, and the electronic device having a upper surface is buried in the multi-layer circuit board, wherein a portion of the upper surface is connected with the via hole. The slug is set in the via hole. One end of the slug is in contact with the upper surface of the electronic device and the other end of the slug is exposed out of the multi-layer circuit board through the via hole.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Inventors: Che-Kun Shih, Yung-Hui Wang
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Patent number: 7420128Abstract: An electronic component embedded substrate and a method for manufacturing the substrate are disclosed. The electronic component embedded substrate includes a substrate main body and an electronic component embedded in the substrate main body. The center plane of the electronic component in the thickness direction thereof and the center plane of the substrate main body in the thickness direction thereof generally match each other.Type: GrantFiled: July 27, 2005Date of Patent: September 2, 2008Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Mitsutoshi Higashi, Kei Murayama, Hiroyuki Kato
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Publication number: 20080192450Abstract: This publication discloses an electronics module and a method for manufacturing it. The electronics module includes at least one component (6) embedded in an insulating-material layer (1), which has a first contacting surface, in which there are first contact terminals (7), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. In addition, the component (6) has a second contacting surface opposite to the first contacting surface, in which there is at least one second contact terminal (7?), from which the component (6) is connected electrically to the conductor structures contained in the electronics module. With the aid of the invention, it is possible to achieve an electronic-module construction that saves space compared to the prior art.Type: ApplicationFiled: April 27, 2005Publication date: August 14, 2008Applicant: Imbera Electronics OyInventors: Risto Tuominen, Antti Iihola
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Publication number: 20080186690Abstract: A method for manufacturing an electronics package is provided that comprises forming at least one module block by providing a carrier substrate having a recess, placing at least one electronic component die in said recess, filling said recess with a molding material, and depositing a circuit layer connected with said at least one component die. It further provides an electronics package, comprising a carrier substrate having a recess, at least one electronic component die placed in said recess, a molding material filling said recess, and a circuit layer connected with said at least one component die.Type: ApplicationFiled: February 7, 2007Publication date: August 7, 2008Applicant: Nokia CorporationInventors: Jani Miettinen, Pauliina Mansikkamaki, Petri Molkkari, Matti Mantysalo, Jani Valtanen
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Patent number: 7405949Abstract: A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.Type: GrantFiled: November 22, 2006Date of Patent: July 29, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Jun Lee, Joo-Sun Choi, Kyu-Hyoun Kim, Kwang-Soo Park
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Publication number: 20080165513Abstract: It is an electronic component built-in substrate 100 configured as follows. That is, an electronic component 30 is provided between at least two boards 10 and 20. An electrode 34 of the electronic component 30 is electrically connected to at least one of the board 10. Also, the boards 10 and 20 are electrically connected to each other. Additionally, the gap between the boards 10 and 20 is sealed with a resin. The electronic component built-in substrate 100 is featured in that a solder ball 40 for electrically connecting the boards 10 and 20 to each other is provided on a surface of the electronic component 30, which faces the other board 20.Type: ApplicationFiled: December 17, 2007Publication date: July 10, 2008Inventors: Akinobu Inoue, Sadakazu Akaike, Atsunori Kajiki, Yuya Yoshino, Takashi Tsubota, Norio Yamanishi
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Patent number: 7397134Abstract: The invention provides a package type semiconductor device and a manufacturing method thereof where reliability is improved without increasing a manufacturing cost. A resin layer and a supporting member are formed on a top surface of a semiconductor substrate formed with pad electrodes. Then, openings are formed penetrating the resin layer and the supporting member so as to expose the pad electrodes. Metal layers are then formed on the pad electrodes exposed in the openings, and conductive terminals are formed thereon. Finally, the semiconductor substrate is separated into semiconductor dice by dicing. When this semiconductor device is mounted on a circuit board (not shown), the conductive terminals of the semiconductor die and external electrodes of the circuit board are electrically connected with each other.Type: GrantFiled: June 6, 2005Date of Patent: July 8, 2008Assignee: Sanyo Electric Co., Ltd.Inventor: Takashi Noma
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Publication number: 20080158838Abstract: Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.Type: ApplicationFiled: February 20, 2008Publication date: July 3, 2008Applicant: IBIDEN CO., LTD.Inventors: Yasushi INAGAKI, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
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Patent number: 7394458Abstract: A printed circuit board (PCB) assembly provides a two layer capacitive trackpad sensor in which an EMI ground grid is interposed among the sensor's capacitive elements on each of its layers. The EMI grid on each of the two layers is electrically coupled via, typically, vias. The described arrangement of sensor elements (capacitor plates) and EMI ground grid traces may be incorporated into a PCB having additional layers (e.g., a four, six or eight layer PCB). If used in this manner, additional vias are provided on the PCB which permit electrical coupling between these “additional layers” and which are electrically isolated from, and shielded by, the EMI ground grid.Type: GrantFiled: September 24, 2004Date of Patent: July 1, 2008Assignee: Apple Inc.Inventors: Benjamin Lyon, Steven P. Hotelling
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Publication number: 20080151511Abstract: Apparatus including a body as an intermediary between a device and a printed circuit board, the body including a contact area defined by a plurality of openings each to accommodate a contact therethrough and an alignment feature adjacent the contact area and protruding from a plane defined by the contact area, wherein a surface of the alignment feature includes a friction-reducing material. A method including contacting an alignment feature of a socket with a friction-reducing material. Apparatus and system including a body as an intermediary between a device and a printed circuit board; a plurality of contacts each disposed through a contact area of the body and oriented to deflect a device in a first direction; and a load plate coupled to the body and configured to apply an actuation force on a device in a different second direction. A method including inserting a device into a socket.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Inventors: Robert R. Martinson, Yupeng Li, Tieyu Zheng, Mandy G. Mistakawi, Thomas G. Ruttan
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Publication number: 20080151515Abstract: A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.Type: ApplicationFiled: May 2, 2007Publication date: June 26, 2008Applicant: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, John M. Lauffer, Vova R. Markovich
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Publication number: 20080151514Abstract: An apparatus operable to interface an electronic component with a signal input. The apparatus may generally include a low-ohm resistor and a voltage translator coupled with the low-ohm resistor. The low-ohm resistor is operable to couple with the input to receive an input signal therefrom. The voltage translator is operable to couple with the electronic component and translate the input signal from a first voltage to a second voltage for use by the electronic component. The low-ohm resistor and voltage translator may be positioned by a pick and place assembly machine such that embodiments of the present invention do not require a technician to manually couple and solder the apparatus to the input and electronic component.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventor: JERRY WILLIAM YANCEY
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Publication number: 20080151516Abstract: According to one embodiment, there is provided a printed-wiring board, includes a first base member including a component mounting face, a first electronic component with a through-electrode mounted on the component mounting face, a second base member stacked on the first base member via an insulating layer covering the first electronic component, a hole part provided in the second base member and communicating with the through-electrode of the first electronic component, and a second electronic component mounted on the second base member and circuit-connected directly to the through-electrode via the hole part.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daigo Suzuki, Minoru Takizawa, Nobuhiro Yamamoto, Hidenori Tanaka
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Publication number: 20080151517Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a mediate layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electronically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the mediate layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.Type: ApplicationFiled: February 20, 2008Publication date: June 26, 2008Applicant: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya