Abstract: A circuit board includes a dielectric layer and a signal routing layer on the dielectric layer. The signal routing layer includes chip traces, connector traces, and signal traces connected with the chip traces and the connector traces. The dielectric layer includes a signal trace area for arraying the signal traces, a chip trace area for arraying the chip traces, and a connector trace area for arraying the connector traces. The dielectric coefficient of the signal trace area is smaller than the dielectric coefficient of the chip trace area and greater than the dielectric coefficient of the connector trace area.

Abstract: The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.

Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid land pattern is described. A number of required pads is determined. A land pattern to yield the required pads is selected. A number of required perimeter routing channels is determined. A size of the land pattern to yield the required perimeter routing channels is optimized. At least one perimeter edge of the land pattern is under populated. In a further aspect, a number of layers is determined when a substrate has multiple layers.

Abstract: A semiconductor package substrate suitable for supporting a damage-sensitive device, including a substrate core having a first and opposite surface; at least one pair of metal layers covering the first and opposite surfaces of the package substrate core, which define first and opposite metal layer groups, at least one of said layer groups including at least one metal support zone; one pair of solder mask layers covering the outermost metal layers of the at least one pair of metal layers; and a plurality of routing lines; wherein the at least one metal support zone is formed so that it lies beneath at least one side of the base of the damage-sensitive device and so as to occupy a substantial portion of the area beneath the damage-sensitive device which is free of said routing lines; a method for the production of such substrate is also described.

Abstract: The invention relates to a high-voltage insulation circuit board which is used in an electric power apparatus such as an electric power converter or the like such as power semiconductor device, inverter module, or the like and provides an insulation circuit board in which electric field concentration at the end sections of a wiring pattern is reduced, partial discharging is suppressed, and a reliability is high. According to the invention, there is provided an insulation circuit board having: a metal base substrate; and wiring patterns which are formed onto at least one of the surfaces of the metal base substrate through an insulation layer, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged.

Abstract: A printed wiring board includes an outermost interlayer resin insulation layer, n outermost conductive layer formed on the outermost interlayer resin insulation layer and including multiple alignment marks, a connection wiring structure connecting the alignment marks, and a solder-resist layer formed on the outermost interlayer resin insulation layer and the outermost conductive layer. The solder-resist layer has openings exposing the alignment marks, respectively, and each of the alignment marks has an electroless plated film formed on each of the alignment marks.

Abstract: Herein disclosed are an apparatus, a system and a method, selectively linking signals between or among slots on a backplane. A backplane printed circuit board has defined slots, each of which receives a card or module. One or more arrays of solder ball mounting pads correspond to signal lines of the slots. Each of one or more signal mapping overlay printed circuit boards has at least one signal trace connected to solder ball landing pads. Selected solder ball mounting pads of the backplane printed circuit board are connected to selected solder ball landing pads of the signal mapping overlay printed circuit board by solder balls. The signal trace or traces of the signal mapping overlay printed circuit board or boards connect the corresponding selected signal lines between or among the slots of the backplane. The backplane and signal mapping overlay printed circuit boards may have mirrored connection arrays.

Abstract: Techniques are provided for electrically connecting components on a printed circuit board (PCB), semiconductor chip package, or other electronic device. More specifically, a first component, configured to generate a differential signal, is disposed on the PCB, while a second component, configured to receive the differential signal from the first component, is also disposed on the PCB. A differential conductor pair comprising first and second parallel conductors extends along a path between the first and second components. The path of the differential conductor pair comprises at least one turn that causes a change in direction of the first and second conductors. The first conductor comprises at least one localized skew compensation bend disposed at the turn such that, at the end of the turn, the first and second conductors have substantially the same length with respect to the first component.

Abstract: A lightweight radio/CD player for vehicular application includes a case and frontal interface formed of polymer based material molded to provide details to accept audio devices and radio receivers, as well as the circuit boards required for electrical control and display. The case and frontal interface are of composite structure, including an insert molded electrically conductive wire mesh screen that has been pre-formed to contour with the molding operation. The wire mesh provides shielding and grounding of the circuit boards via exposed wire mesh pads and adjacent ground clips.

Abstract: The present disclosure discloses a driving printed circuit board (PCB) for use in a display device. More particularly, a driving printed circuit board improving the bonding by preventing PCB warpage is provided. The rear surface stiffener plate includes polygonal patterns to prevent a PCB warpage of the driving printed circuit board due to different heat shrinkage from that of the board during the surface mounting technology (SMT) process.

Abstract: An integrated circuit board includes a substrate, a plurality of electronic components and at least one antenna. The substrate has a central area and two edge areas, wherein the central area is between the two edge areas. The electronic components are disposed on the central area. The antenna is disposed on at least one of the two edge areas, wherein there is predetermined distance between the antenna and the electronic components.

Abstract: A circuit package includes: electronic circuitry, electrically conductive material forming multiple leads, and multiple connections between the electronic circuitry and the multiple leads. A portion of the electrically conductive material associated with the multiple leads (e.g., low impedance leads supporting high current throughput) is removed to accommodate placement of the electronic circuitry. Each of the multiple leads can support high current. The multiple connections between the, the multiple leads provide connectivity between circuit nodes on the electronic circuitry and pads disposed on a planar surface of the electronic circuit package.

Abstract: A footprint of a printed circuit board (PCB) for a leadframe-based package includes a plurality of pads arranged within a central region on a main surface of the PCB; and an array of signal pads disposed within a peripheral region surrounding the central region.

Abstract: A microelectronic package having a radio frequency (RF) amplifier circuit and, incorporating harmonic rejection filters and matching circuits integrally formed in the package is disclosed. A harmonic rejection filter may comprise a metal-insulator-metal (MIM) capacitor serially coupled between bond pads disposed on a RF amplifier circuit die, a first wire bond coupling a first bond pad to a package output, where the first bond pad is coupled to the output of the RF amplifier, and a second wire bond coupling a second bond pad to a package ground. The harmonic rejection filter may be appropriately configured to filter one or more harmonics at different frequencies.

Abstract: To broaden a substantial area for wiring between a display portion and a driver element, and to increase the number of wirings between the driver element and the display portion. In a driving IC 100, bumps 10, 12, 14, 16, 18, 22, 24, 26 and 28 are arrayed in a first row 110 and bumps 11, 13, 15, 17, 21, 23, 25, 27 are arrayed in a second row 120, wherein the respective bumps are disposed so that the shortest distances between forward ends of the respective bumps and a side along the array, become larger gradually from the center outward in the array.

Abstract: Printed circuit boards are provided with embedded components. The embedded components may be mounted within recesses in the surface of a printed circuit board substrate. The printed circuit board substrate may have grooves and buried channels in which wires may be mounted. Recesses may be provided with solder pads to which the wires may be soldered or attached with conductive adhesive. An integrated switch may be provided in an opening within a printed circuit board substrate. The integrated switch may have a dome switch member that is mounted within the opening. A cover member for the switch may be formed from a flexible layer that covers the dome switch member. Terminals for the integrated switch may be formed from conductive structures in an interior printed circuit board layer. Interconnects may be used to electrically connect embedded components such as switches, integrated circuits, solder pads for wires, and other devices.

Abstract: A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire.

Abstract: An electronic module with excellent electrical characteristics includes an electronic component, a mount board, signal electrodes, a ground electrode, and an insulating layer. The electronic component is mounted on a first main surface of the mount board. The signal electrodes and the ground electrode are located on a second main surface of the mount board. The insulating layer is arranged so as to cover a portion of the second main surface of the mount board. The insulating layer is arranged so as not to cover end portions of the signal electrodes that face the ground electrode.

Abstract: A substrate includes: a base; and a plurality of bonding terminals arranged on at least one surface of the base, wherein the plurality of bonding terminals include a first bonding terminal and a second bonding terminal, the first bonding terminal and the second bonding terminal include, in plan view of the base, a circle contacting portion extending along the circumference of a circle tangent to the first bonding terminal and the second bonding terminal, all of the plurality of bonding terminals are arranged so as not to protrude from an area including the circle and the inside thereof, and the circle contacting portion includes at least a first circle contacting portion disposed in the first bonding terminal and a second circle contacting portion disposed in the second bonding terminal.

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Abstract: Stacked arrays of components are disclosed. In one embodiment, a first and a second layer of components are electrically and mechanically coupled to an interposer with an encapsulated third layer of components disposed between the first and second layers. The first layer can be configured to attach the stacked array to a host printed circuit board. The interposer can couple signals between the components on the first and second layers.

Abstract: A display panel includes a periphery area, an active display area adjacent to the periphery area and having two opposite sides connecting with the periphery area, a driving chip disposed at the periphery area for driving electrical elements in the active display area, and a plurality of wires electrically connecting the driving chip and the electrical elements in the active display area. The distance from a first part of the wires to the center of the driving chip is farther than the distance from a second part of the wires to the center of the driving chip, and the width of the first part of the wires on a reference line perpendicular to the opposite sides of the active display area is greater than the width of the second part of the wires on the reference line.

Abstract: An information handling system device includes a plurality of electronic components; an electric circuit including at least one trace for connecting two or more of the plurality of electronic components and transmitting data between the plurality of electronic components via at least one electric signal; and a substrate including an insulating material for serving as a base for the electric circuit, wherein each of the at least one electric signal transmitted between the plurality of electronic components is transmitted utilizing slope manipulation by manipulating each of the at least one electric signal to provide a slope substantially proportional to a discrete integer data value of n discrete integer data values, n being a positive integer greater than or equal to 3, said discrete integer data value represented by using one of n distinct slopes transmitted utilizing a particular reference voltage of n predetermined reference voltages.

Abstract: A printed wiring board has a packaging substrate having multiple pads, and a transmission substrate mounted on the multiple pads of the packaging substrate. The packaging substrate has a pad group constituted of pads which mount an electronic component, the multiple pads mounting the transmission substrate includes a first pad positioned in a peripheral portion of the packaging substrate and a second pad positioned between the first pad and the pad group, the second pad is electrically connected to a signal pad of the pads in the pad group, and the transmission substrate includes a horizontal wiring which electrically connects the second pad and the first pad and which transmits a signal between the second pad and the first pad.

Abstract: An interconnect array is described. The interconnect array comprises a pattern of adjacent interconnect tiles, each interconnect tile comprising ten interconnect locations including eight I/O signal connectivity locations forming a perimeter array having a corner I/O signal connectivity location, a center connectivity location surrounded by the eight I/O signal connectivity locations in the perimeter array being a first ground connectivity location or a power connectivity location, and a second ground connectivity location adjacent to the corner I/O signal connectivity location of the perimeter array and externally offset from the perimeter array to form an asymmetrically shaped interconnect tile. At least one interconnect tile of the pattern of adjacent interconnect tiles has a center connectivity location that is a power connectivity location.

Abstract: A motherboard assembly includes a motherboard and an expansion apparatus. The motherboard includes a first expansion slot. An edge connector is set on a bottom side of the expansion apparatus to be detachably engaged in the first expansion slot. A number of SATA interfaces and a number of second expansion slots are arranged on the expansion apparatus, and are connected to signal pins and power pins of the edge connector.

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract: The present invention discloses a compact server power supply having high power density has a casing, a main printed circuit board, a sub-printed circuit board, a power supplying circuit, a power output terminal set and a fan. The power supplying circuit has a primary side circuit unit, a transformer and a secondary side circuit unit. Electric elements of the primary and secondary side circuit units and the transformer are soldered on the main printed circuit board except parts of the electric elements of the secondary side circuit unit are soldered on the sub-printed circuit board. The sub-printed circuit board is vertically mounted and soldered on the main printed circuit board, so the length of the main printed circuit board is shortened to implement the server power supply having a compact size and high power density.

Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.

Abstract: A wireless module includes a first board (11) on which a mounting component of a wireless circuit is mounted, and a second board (12) which is laminated on the first board (11). The first board (11) and the second board (12) are electrically connected together by a connecting member (18) such as a Cu core ball. Laterally to the connecting member (18), a conductive member (23) for impedance adjustment is provided at a position at a predetermined distance from the connecting member (18), such that the signal path of the connecting member (18) has predetermined impedance.

Abstract: An apparatus including a first printed wiring board section and a second printed wiring board section. The first printed wiring board section includes a first dielectric material layer. The first dielectric material layer has a first dissipation factor. The second printed wiring board section is directly attached with the first printed wiring board section to form a unitary printed wiring board structure. The second printed wiring board section includes a second dielectric material layer and an antenna on the second dielectric material layer. The second dielectric material layer has a different second dissipation factor.

Abstract: A wiring substrate 11 includes a wiring substrate main body 31 having a semiconductor element mounting area A, a wiring pattern 33 provided on an upper surface 31A of the wiring substrate main body 31 at a portion corresponding to the semiconductor element mounting area A, a solder resist 35 provided on the upper surface 31A of the wiring substrate main body 31 and having an opening portion 43 whose size is substantially equal to the semiconductor element mounting area A when viewed from a top, and a dam 37 provided on the solder resist 35 to block an underfill resin 13 provided in a clearance between the semiconductor element 12 and the wiring substrate main body 31. A distance between an inner wall of the opening portion 43 of the solder resist 35 and an inner wall of the dam 37 is partially varied.

Abstract: The present invention provides a dual chip signal conversion device, comprising: a carrier, one side surface thereof being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact; a first chip disposed at one side surface of the carrier and electrically connected to the second and fourth contacts; a second chip disposed at one side surface of the carrier and electrically connected to the first chip; and an antenna disposed within the carrier and electrically connected to the second chip.

Abstract: A flexible circuit assembly that includes a flexible circuit substrate. A spacer is attached to a first side surface of the substrate, and a die carrier is attached to the opposite side surface of the substrate. The die carrier includes one or more photonic die mounted thereon that face an opening formed through the substrate so that the photonic die transmits and/or receives optical signals through the opening. Wire bonds electrically connect the photonic die to an electrical pad on the first side surface of the substrate. The spacer helps to space the wire bonds from an optical connector that connects to the flexible circuit assembly, so that the wire bonds do not interfere with the mechanical connection between the flexible circuit assembly and the optical connector.

Abstract: An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.

Abstract: A housing for an electronic control device includes at least two housing parts, at least one housing base, a housing lid and an electronic connection between components disposed inside the housing and components disposed outside the housing. The connection is fixed to the base of the housing. The electronic connection is either constructed as a single-component flexible printed circuit board or as at least one partial flexible printed circuit board including at least one uniform open area of a copper conductor track outside an area covered by the housing lid. The width of the uniform region is oriented to a predefined contacting type of peripheral components and is longer than necessary for the contacting type. The invention therefore provides for a variable adaptation of generic electronics housings, thereby not necessarily requiring a novel structure of the housing with corresponding expensive individual packaging.

Abstract: The present disclosure involves a semiconductor device. The semiconductor device includes a substrate. The semiconductor device includes an electronic device positioned over the substrate. The electronic device includes an opening. The semiconductor device includes a shielding device positioned over the substrate and surrounding the electronic device. The shielding device includes a plurality of elongate members. A subset of the plurality of elongate members extend through the opening of the electronic device. At least one of the electronic device and the shielding device is formed in an interconnect structure positioned over the substrate.

Abstract: A module incorporating electronic component includes a substrate, a wiring pattern located on at least one surface of the substrate, at least one electronic component electrically bonded to the wiring pattern, and bonded to the substrate, and a sealing resin arranged to cover the surface of the substrate including the bonded electronic component. The wiring pattern includes a plurality of land electrodes, and electrically bonded to the electronic component or a via conductor, and a wiring electrode arranged to connect the land electrodes, and an insulating resin is disposed on the wiring electrode except for a boundary between the land electrode and the wiring electrode, so as to cross at least one boundary between the substrate and the wiring electrode such that an adhesion strength between the insulating resin and the sealing resin is higher than an adhesion strength between the insulating resin and the wiring pattern.

Abstract: A differential transmission circuit includes a grounded conductive layer, a pair of transmission line conductors, a conductive film and a via hole which connects the grounded conductive layer to the conductive film. The differential transmission circuit further includes a straight-line region which is present in the differential transmission circuit through which a differential transmission signal output by a driving circuit is transmitted and in which the pair of transmission line conductors extends parallel so as to have a first width, and a band rejection filter region in which the pair of transmission line conductors planarly overlaps the conductive film and extends parallel so as to have a second width narrower than the first width and a common mode of the differential transmission signal is attenuated at one of the frequencies which are natural number multiples of a frequency corresponding to the predetermined bit rate.

Abstract: Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

Abstract: A substrate structure and a package structure using the same are provided. The substrate structure includes a number of traces, a substrate core and a number of first metal tiles. The substrate core has a first surface and a second surface opposite to the first surface. The first metal tiles are disposed on one of the first surface and the second surface, the minimum pitch between adjacent two of the first metal tiles is the minimum process pitch.

Abstract: A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region.

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

Abstract: A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove.

Abstract: A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A wiring substrate includes differential wirings; a first insulating layer adjacent to one side of the differential wirings, including first fiber bundles parallel to the differential wirings; a second insulating layer adjacent to another side of the differential wirings, including second fiber bundles parallel to the differential wirings and disposed by the same pitch as the first fiber bundles; a third insulating layer on the first insulating layer on a side opposite to the differential wirings, including third fiber bundles in parallel to the differential wirings; and a fourth insulating layer on the second insulating layer on a side opposite to the differential wirings, including fourth fiber bundles in parallel to the differential wirings. Intervals of the third and fourth fiber bundles are respectively narrower than intervals of the first and second fiber bundles. The differential wirings are disposed between adjacent first fiber bundles, and between adjacent second fiber bundles.

Abstract: The present invention provides a dual chip signal conversion device, comprising: a carrier, one side surface thereof being provided with at least a first contact and a second contact while the other side surface thereof being provided with at least a third contact and a fourth contact; a first chip disposed at one side surface of the carrier and electrically connected to the second and fourth contacts; a second chip disposed at one side surface of the carrier and electrically connected to the first chip; and an antenna disposed within the carrier and electrically connected to the second chip.