Plural Contiguous Boards Patents (Class 361/792)
  • Patent number: 7365272
    Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: April 29, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Shang-Wei Chen, Suo-Hsia Tang, Chao-Wen Shih
  • Patent number: 7361843
    Abstract: An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: April 22, 2008
    Assignee: Dell Products L.P.
    Inventors: Ernest Lentschke, Jeffrey C. Hailey, Raymond McCormick
  • Patent number: 7361849
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: April 22, 2008
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Yasuji Hiramatsu
  • Patent number: 7360376
    Abstract: Methods, devices and systems for coupling an HVAC controller to an HVAC system are provided. In several embodiments, a sub-base is provided allowing an HVAC controller to be coupled to a printed wire board to allow, in some cases, modification of the HVAC controller function. The sub-base may include a plurality of terminals, each terminal having a contact mating feature for receiving a pin of an HVAC controller, a terminal block location for receiving an end of a wire, and a transformation pin-out adapted to couple to a printed wire board, with the contact mating feature, the terminal block location, and the transformation pin-out being electrically coupled together. In one embodiment, an HVAC controller is modified to allow a controller adapted for use with a single fuel system to control dual fuel system.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: April 22, 2008
    Assignee: Honeywell International Inc.
    Inventors: Robert D. Juntunen, Peter E. Stolt, Guy M. Shoultz
  • Patent number: 7361848
    Abstract: Disclosed is a wiring board including: a first insulating layer made of a flexible material; a second insulating layer stacked on a partial region of the first insulating layer; a first wiring layer disposed between the first insulating layer and the second insulating layer; and a second wiring layer disposed on the second insulating layer, wherein the first insulating layer is composed of two or more insulating layers and further has a third wiring layer in each interlayer of the two or more insulating layers, wherein an electric interlayer connection between the first wiring layer and the third wiring layer has a plating layer of a hollow cylindrical shape or a hollow truncated cone shape, and inside of the hollow is filled by a material of the second insulating layer being transformed and entering therein.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: April 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiko Happoya
  • Patent number: 7358115
    Abstract: A semiconductor multi-package module has stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding, and in which the upper package is inverted. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: April 15, 2008
    Assignee: Chippac, Inc.
    Inventor: Marcos Karnezos
  • Patent number: 7358446
    Abstract: A power distribution system comprises a flexible power connector, a printed circuit board, a power supply, and a processor mounted on the printed circuit board. The flexible power connector comprises a first end electrically connected to the processor and a second end electrically connected to the power supply. The flexible power connector is configured with a length so that the power supply is in a spaced relationship relative to the processor and the flexible power connector includes a plurality of stacked layers arranged generally parallel to each other for distributed power transmission. These layers include at least two ground layers and at least one power layer. The power layer is sandwiched between two of the at least two ground layers.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: April 15, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Sachin Navin Chheda, Ricardo E. Espinoza-Ibarra, Kirk Yates
  • Patent number: 7354800
    Abstract: An integrated circuit package system including providing a base substrate, attaching a base integrated circuit on the base substrate, attaching a core substrate over the base integrated circuit, attaching a substrate electrical connector between the core substrate and the base substrate, and applying an encapsulant having the core substrate partially exposed over the base integrated circuit.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 8, 2008
    Assignee: Stats Chippac Ltd.
    Inventor: Flynn Carson
  • Patent number: 7355863
    Abstract: A high frequency multilayer integrated circuit is provided with: a multilayer board including n earth conductor layers (n: integer of two or more than two) and (n-1) dielectric layers each arranged between adjacent earth conductor layers; a first high frequency circuit disposed in one of the most outside earth conductor layers of the multilayer board; a first power-supply/control circuit disposed in this most outside earth conductor layer; a second high frequency circuit disposed in at least one of the dielectric layers and connected to the first high frequency circuit in the multilayer board; a second power-supply/control circuit disposed in another one of the most outside earth conductor layers of the multilayer board; and a third power-supply/control circuit disposed in at least one of the dielectric layers at a portion at which the second high frequency circuit does not exist, the third power-supply/control circuit being connected to the first and second power-supply/control circuits.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 8, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Suzuki, Taihei Nakada, Tsuyoshi Kumamoto, Yuusuke Yamashita
  • Patent number: 7351915
    Abstract: A printed circuit board (PCB) having at least one embedded capacitor and a method of fabricating the same is provided. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: April 1, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin-Yong Ahn, Chang-Sup Ryu, Suk-Hyeon Cho, Seok-Kyu Lee, Jong-Kuk Hong, Ho-Sik Jun
  • Patent number: 7350292
    Abstract: A method for affecting an impedance of a portion of an electrical circuit loop in an electrical circuit apparatus includes providing an electrical circuit apparatus having at least a portion of an electrical circuit loop including at least one of at least one trace and at least one via, and providing a layer of magnetic material disposed adjacent at least one of the trace and the via. The trace and the via are operatively connected together to provide electrical communication. Dielectric material is disposed in an operative relationship adjacent at least one of the trace and the via. The layer of magnetic material is disposed in operative relationship near at least one of the trace and the via to affect the impedance of at least one of the trace, the via and the portion of the circuit loop formed by the trace and the via.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 1, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Michael J. Tsuk
  • Patent number: 7348498
    Abstract: A printed circuit board comprises a conductive layer and a via transecting the conductive layer. The printed circuit board comprises a pattern of conductive material having a plurality of voids in the conductive layer near the via.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: March 25, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andew Harvey Barr, Dale John Shidla, Robert William Dobbs
  • Patent number: 7342183
    Abstract: A circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 11, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Frank D. Egitto, Voya R. Markovich, Luis J. Matienzo
  • Patent number: 7342804
    Abstract: An R-C network formed on a substrate. The capacitor includes a metal member with anodized and unanodized layers. The unanodized layer functions as one of the capacitor's electrodes. The anodized layer functions as the capacitor's dielectric layer. The resistor is formed from material on the same side of the substrate as the capacitor. In some versions of the invention, the resistor is formed on top of a substrate dielectric layer. In these versions of the invention, a conductor both functions as one of the capacitor's electrodes and connects the resistor to the capacitor. In alternative versions of the invention, the resistor is formed from a film that disposed on the undersurface a metal foil. The foil functions as the resistor to capacitor conductor. Sections of the foil that are removed expose and define the resistor. Solder balls or other connectors on the substrate surface connect the network to another component.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: March 11, 2008
    Assignee: CTS Corporation
    Inventors: Jason Langhorn, Craig Ernsberger
  • Patent number: 7342179
    Abstract: An electronic device includes a plurality of components, nanoparticles to bond the components, and a receiving layer for holding the nanoparticles, the receiving layer being disposed on at least one of the bonded components. The electronic device may further include an electrode disposed on at least one of the plurality of components. The receiving layer is disposed on the surface of the electrode. Conductive particles etc. are mixed in the receiving layer.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: March 11, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7319197
    Abstract: A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: January 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Stefano Oggioni, Michele Castriotta, Gianluca Rogiani, Mauro Spreafico, Giorgio Viero
  • Patent number: 7317165
    Abstract: An intermediate substrate comprising: an intermediate substrate body containing an insulating material, and having a first face to be mounted with an semiconductor element and a second face opposing to said first face; and a semiconductor element mounting area including a plurality of first face terminals arranged on said first face, and being surrounded by an outermost periphery of said plurality of first face terminals, wherein a center of said semiconductor element mounting area is eccentric with respect to a center of said first face.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: January 8, 2008
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hajime Saiki, Kazuhiro Urashima
  • Patent number: 7315459
    Abstract: Briefly, in accordance with one embodiment of the invention, an electromagnetic interference (EMI) reduction device may include a circuit and at least one heatsink. The circuit may include analog devices coupled to reduce EMI signals received by the heatsink. The devices may be specifically adapted to substantially invert or phase-shift by 180° the EMI signals received by the heatsink.
    Type: Grant
    Filed: October 7, 2004
    Date of Patent: January 1, 2008
    Assignee: Intel Corporation
    Inventor: Michael J. Schaffer
  • Patent number: 7312405
    Abstract: A module structure having embedded chips mainly comprises a dielectric layer, at least a semiconductor chip embedded in the dielectric layer, and at least a circuit structure formed on the surface of the dielectric layer, the circuit structure electrically connected to the semiconductor chip via a plurality of conductive structures formed in the dielectric layer, for embedding the module structure in an electronic device, and electrically connecting the electronic device via the circuit structure on the surface of the dielectric layer.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: December 25, 2007
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Shih-Ping Hsu
  • Patent number: 7307854
    Abstract: A flexible wired circuit board having a fine pitch conductor wiring pattern that can be produced with a high yield rate and improved productivity, includes a first and a second flexible wired circuit board which are disposed to be adjacent to each other on a supporting board so that a first and a second connection terminal are connected to a same electronic component. When a defect occurs in the first flexible wired circuit board in the production process in which the first conductor wiring pattern of the first flexible wired circuit board is formed into the fine pitch, only the defective first flexible wired circuit board can be screened out as a defective product. Thus, the first flexible wired circuit board having no defects can be selected for combination with the second flexible wired circuit board. Thus, the flexible wired circuit board can be produced in a high yield rate.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: December 11, 2007
    Assignee: Nitto Denko Corporation
    Inventor: Akinori Itokawa
  • Patent number: 7304863
    Abstract: An integrated circuit package can include electronic components used to enhance the performance of the integrated circuit that is part of the package. In order to reduce some adverse effects of including the electronic components, void regions are introduced into portions of the integrated circuit package interconnect layers.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: December 4, 2007
    Assignee: Lattice Semiconductor Corporation
    Inventor: Weijia Wu
  • Patent number: 7304857
    Abstract: An electronic circuit, preferable as a sensor node, has a highly sensitive radio function and is capable of performing a low-power-consumption operation. The electronic device has a board; a connector for connecting a sensor; a first signal processor circuit receiving an input of sensor data from the sensor through the connector and forming transmission data; and a second signal processor circuit converting a transmission signal from the first signal processor circuit into a high-frequency signal. The connector and the first signal processor circuit are mounted on a first surface of the board, and the second signal processor circuit is mounted on a second surface of the board.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 4, 2007
    Assignee: Hitachi, Ltd.
    Inventor: Shunzo Yamashita
  • Patent number: 7280369
    Abstract: A multi-layer printed circuit board for a keyboard has an upper and lower layers, an insolating separation positioned between the upper and lower layers, multiple thin film switches having two thin conductive element respectively formed on the upper and lower layer, and multiple spacers positioned between one of the upper and lower layer and the insolating layer. Since each spacer can be selectively formed on the upper layer, lower layer or insolating separation and corresponds to one of the through holes in the insolating separation, the spacers increase a distance between the two thin conductive elements of each thin film switch. Therefore, the sensitivity of touch of the multi-layer PCB can be adjusted by different arrangements of the spacers.
    Type: Grant
    Filed: January 17, 2006
    Date of Patent: October 9, 2007
    Inventor: Huo-Lu Tsai
  • Patent number: 7280371
    Abstract: A multi stage mounting printed circuit board system and method is presented. In one embodiment, a multi stage mounting printed circuit board system includes a first printed circuit board for mounting electrical components on. A first printed circuit board interface component is coupled to the first printed circuit board. The first printed circuit board interface component communicatively couples the first printed board to a second printed board via a second printed circuit board interface component. A plurality of printed circuit board extractors are coupled to the first printed circuit board. The plurality of printed circuit board extractors couple the first printed circuit board to card guides (e.g., a single pair of card guides in which the second printed circuit board is mounted).
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: October 9, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephan Karl Barsun, Robert William Dobbs
  • Patent number: 7280373
    Abstract: A printed board unit includes a mother board 60, and a first board unit 70-1 and a second board unit 70-2 that face each other and are vertically mounted onto the mother board 60 with connector devices 100-1 and 100-2. The first board unit 70-1 has memory mounting boards 81-1 horizontally mounted to a region near the lower end of a vertically standing daughter board 71-1. The second board unit 70-2 has memory mounting boards 81-2 horizontally mounted to a region near the upper end of a vertically standing daughter board 71-2. The memory mounting boards 81-1 of the first board unit 70-1 are arranged on the lower side, while the memory mounting boards 81-2 of the second board unit 70-2 are arranged on the upper side.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: October 9, 2007
    Assignee: Fujitsu Limited
    Inventor: Osamu Aizawa
  • Patent number: 7280372
    Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: October 9, 2007
    Assignee: Silicon Pipe
    Inventors: Kevin P. Grundy, William F. Wiedemann, Joseph C. Fjelstad
  • Patent number: 7269029
    Abstract: A test board for testing a packaged integrated circuit has a set of contacts matching counterpart contacts on a socket. The contacts are each connected to a first voltage plane containing power, a second voltage plane carrying ground, and a set of terminals that will be connected to a tester system. The number of terminals necessary to operate the circuit is identified, both power terminal and signal-carrying terminals to the affected part of the circuit, and two of the three connections to the contacts are severed; e.g. the terminal carrying signals is disconnected from the power and ground. The disconnect from the voltage planes may be performed by an automated milling machine in a short time, providing much faster turnaround than a method that forms a custom-made board.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventor: Richard W. Oldrey
  • Patent number: 7269032
    Abstract: A shielding apparatus for EMI-sensitive electronic components, especially for radio transmitting devices and/or radio receiving devices of telecommunication terminals for contactless telecommunication, such as cordless telephones and mobile telephones and similar, which can be constructed without using expensive manufacturing and assembly steps without any extra space requirement. The EMI-sensitive electronic components and/or circuits are arranged on a separate, at least double-layered printed circuit board and are embodied as a printed circuit board module.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: September 11, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventor: Matthias Lungwitz
  • Patent number: 7253504
    Abstract: An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jun Zhai, Jinsu Kwon, Richard C. Blish, II
  • Patent number: 7248482
    Abstract: A module with a built-in circuit component of the present invention includes an electric insulating layer, a pair of wiring layers provided on both principal planes of the electric insulating layer, a plurality of via conductors electrically connecting the pair of wiring layers and passing through the electric insulating layer in a thickness direction thereof, and a circuit component buried in the electric insulating layer, wherein the plurality of via conductors are disposed in a circumferential portion of the electric insulating layer in accordance with a predetermined rule. The plurality of via conductors are placed at an interval, for example, so as to form at least one straight line, in a cut surface of the electric insulating layer in a direction parallel to a principal plane thereof.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Asahi, Yutaka Taguchi, Yasuhiro Sugaya, Seiichi Nakatani, Toshio Fujii
  • Patent number: 7245506
    Abstract: A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: July 17, 2007
    Assignee: Dell Products L.P.
    Inventors: Stuart W. Hayes, Shane Chiasson
  • Patent number: 7245505
    Abstract: A laminated electronic component includes a laminated block in which a plurality of electrically insulating layers are laminated. An external conductor film is disposed on a surface of the laminated block. An additional conductor film which is at the same potential as the external conductor film is arranged such that it faces the external conductor film with an insulating layer disposed therebetween. The additional conductor film and the external conductor film are electrically connected to each other through a via-hole conductor so that they are at the same potential.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 17, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuhide Kato, Yoshikazu Chigodo, Keiji Ogawa
  • Patent number: 7242592
    Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: July 10, 2007
    Assignee: Amphenol Corporation
    Inventors: Jason J. Payne, Mark W. Gailus, Leon M. Khilchenko, Huilin Ren
  • Patent number: 7236373
    Abstract: A recess for fully receiving an electronic component and a window opened from the bottom of the recess to the bottom surface of a metal substrate are formed in the metal substrate. A wiring board is bonded to the underside of the metal substrate, and the electronic component is fixed to the bottom of the recess. Input and output terminals of the electronic component are connected to electrode pads of the wiring board exposed within the window using wire bonding. A metal lid is bonded to the top surface of the metal substrate to close the opening of the recess. Electromagnetic waves generated by the electronic component are confined to the electronic device because the electronic device is surrounded by the metal substrate, the metal lid, and a ground electrode disposed on the wiring board. Heat dissipation performance is assured because the electronic component is connected to the metal substrate.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 26, 2007
    Assignees: NEC Electronics Corporation, Hitachi Cable, Ltd.
    Inventors: Kenji Uchida, Koki Hirasawa, Tatsuya Ohtaka, Kazuhisa Kishino, Sachio Suzuki
  • Patent number: 7224046
    Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 29, 2007
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani
  • Patent number: 7215557
    Abstract: An assembly that includes two or more microelectronic modules in a self-sustaining structure that is adapted to be installed in a housing. The microelectronic modules are affixed to supports that are attached to ribs and arranged in parallel-spaced relationship. When the assembly is received in a housing, the ribs engage the inner wall of the housing to securely position the assembly. Also, the ribs space the microelectronic modules apart from the housing to facilitate coolant gas flow through the housing and thereby improve thermal dissipation during operation.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Andrew Z. Glovatsky, Vladimir Stoica
  • Patent number: 7202419
    Abstract: A multi-layered integrated RF/IF circuit board is provided. The board is fabricated beginning with a center layer of material. In a first preferred embodiment, the center layer is a rigid core material. In a second preferred embodiment, the center layer is a pliable non-conductive material. For every layer added to the upper surface of the stack-up structure of the board, a corresponding layer of the same material is added to the lower surface of the stack-up structure. Thus, during the lamination process, both the upper and lower surfaces are primarily soft, pliable non-conductive material. These non-conductive layers absorb any stresses introduced during the lamination process. Thus, when cooled, the board has large area flatness. Standard manufacturing processes can be used for each individual step in the fabrication of the board. Therefore, a multi-layered integrated RE/IF circuit board in accordance with the present invention can be fabricated inexpensively.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: April 10, 2007
    Assignee: DragonWave Inc.
    Inventors: Michael Cooper, Robert A. Leroux
  • Patent number: 7200011
    Abstract: A method of selectively assembling a printed circuit board (PCB) module intended for attachment to another structure, such as another larger PCB. A plurality of different mounting hardware for a PCB are provided for enabling the selective enhancement of the thermal characteristics of the module. One embodiment provides a conversion kit comprising a PCB having a circuit mounted thereon, lead frames, a baseplate, and open frame and baseplate mounting hardware that, when selectively attached to the PCB, result in an open frame or a baseplate module. The manufacturer of power conversion or other modules can thus manufacture and pretest the board's electronics before assembly into either an open frame or baseplate module, while also providing a conversion kit that includes inexpensive mounting hardware to enable a user to select between assembling a module as either an open frame or a baseplate module.
    Type: Grant
    Filed: May 2, 2003
    Date of Patent: April 3, 2007
    Assignee: Astec International Limited
    Inventor: Karl T. Fronk
  • Patent number: 7197820
    Abstract: A circuit board is provided in which peeling strength is prevented from decreasing and a connection resistance to a conductive material is prevented from increasing, though the contact area decreases when the circuit board has a copper foil. This circuit board has a metal film for covering a through hole on at least one surface of an insulating substrate having the through hole filled with the conductive material. An uneven layer with a thickness of 5 ?m or more is formed on a surface of the metal film, and a metal layer is formed on the opposite surface to the uneven layer.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: April 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Sugawa, Yoshihisa Takase
  • Patent number: 7196274
    Abstract: A multi-layered integrated RF/IF circuit board is provided. The board is fabricated beginning with a center layer of material. In a first preferred embodiment, the center layer is a rigid core material. In a second preferred embodiment, the center layer is a pliable non-conductive material. For every layer added to the upper surface of the stack-up structure of the board, a corresponding layer of the same material is added to the lower surface of the stack-up structure. Thus, during the lamination process, both the upper and lower surfaces are primarily soft, pliable non-conductive material. These non-conductive layers absorb any stresses introduced during the lamination process. Thus, when cooled, the board has large area flatness. Standard manufacturing processes can be used for each individual step in the fabrication of the board. Therefore, a multi-layered integrated RF/IF circuit board in accordance with the present invention can be fabricated inexpensively.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: March 27, 2007
    Assignee: DragonWave Inc.
    Inventors: Michael Cooper, Robert A. Leroux
  • Patent number: 7186920
    Abstract: The flexible wiring board has a first wiring film and a second wiring film. Because the first wiring film has a larger thickness than the second wiring film, the sectional area and electrical resistance of the first wiring film can be enlarged because of the larger film thickness even in a case where the first and second wiring films have almost the same width. Therefore, a high current can flow through the first wiring film, although the wiring film has a small width. As a result, a high density of the flexible wiring board can be easily achieved.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: March 6, 2007
    Assignees: Sony Chemical & Information Device Corporation, Sony Corporation
    Inventor: Masanori Takeuchi
  • Patent number: 7180751
    Abstract: An input/output transition board system for collecting and distributing input/output signals between a backplane board and an I/O board while allowing for additional electronic devices. The input/output transition board system includes a transition board having at least one front connector and at least one rear connector. The front connector is connectable to a corresponding rear panel connector within a backplane board. The rear connector is connectable to a corresponding front I/O connector of an I/O board. The transition board collects and passes the signals between the I/O board and the backplane board. The transition board is also preferably active with additional electronic devices connected to the transition board.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: February 20, 2007
    Assignee: Isothermal Systems Research, Inc.
    Inventors: Gregory S. Geschke, William C. Gustafson, Alan B. Roberts
  • Patent number: 7176384
    Abstract: In a stack-type piezoelectric device, a separator made of a material capable of preventing solder leaching is buried in a terminal electrode so as to block the whole of an aperture of a through hole. For this reason, it is feasible to securely prevent an electroconductive member in the through hole from dissolving into a molten solder, during connection of a lead wire to an outside layer of the terminal electrode by the solder, and to securely prevent breakage of electrical connection in the through hole.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: February 13, 2007
    Assignee: TDK Corporation
    Inventor: Satoshi Sasaki
  • Patent number: 7173193
    Abstract: A method and structure are provided for implementing enhanced interconnection performance of an electrical connector, such as a land grid array (LGA) module, and a printed wiring board. A multi-layer printed wiring board includes a plurality of predefined ground and power layers. At least one of the predefined ground and power layers includes a thickness variation minimizing structure for minimizing thickness variation. The thickness variation minimizing structure includes a perforated pattern within a selected area of the at least one of the predefined ground and power layers. The selected area is proximate to predefined module sites, such as land grid array (LGA) module sites, in the ground and power layers. The selected area can include regions surrounding each predefined module site, and also can include a region within the module site.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: February 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: William Louis Brodsky, Mark Kenneth Hoffmeyer, James R. Stack
  • Patent number: 7149090
    Abstract: A recording apparatus that has a recording head and a flexible printed circuit board. The recording head, which performs recording on a recording medium, has a plurality of recording elements. One end of the flexible printed circuit board has plurality of feeder wires that connect to one of the terminal lands of each of the recording elements. A first common voltage wire connects the other terminal lands of each of the recording elements to a common potential. A drive circuit is attached to the flexible printed circuit board to drive the recording head via the feeder wires. The other end of the flexible printed circuit board is connected to another circuit board used by the recording apparatus.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: December 12, 2006
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Shigeru Suzuki, Yasuhiro Kato, Tomoyuki Kubo, Koji Imai
  • Patent number: 7149093
    Abstract: The coupling apparatus couples two circuit cards to fit into a larger chassis. A coupling element can connect two similar sized circuit cards or two different sized circuit cards together by coupling the first circuit card and the second circuit card to effectively form a combined circuit card of a larger size. The larger size may allow for more features, may make it easier to dissipate heat, may make the circuit cards easier to shield, and/or may allow for the use of larger and less expensive components on the circuit cards.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: December 12, 2006
    Assignee: National Instruments Corporation
    Inventor: Craig M. Conway
  • Patent number: 7149092
    Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: December 12, 2006
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Daisuke Iguchi
  • Patent number: 7130194
    Abstract: A transceiver module including a primary printed circuit board and a secondary printed circuit board in an enclosure is presented. The primary printed circuit board is coupled to the secondary printed circuit board by a connector pin that protrudes out of a critical surface of the enclosure. The printed circuit boards may be positioned substantially parallel to the critical surface of the enclosure. When a transmitter is electrically connected to the primary printed circuit board and a receiver is electrically connected to the secondary printed circuit board, the transmitter and the receiver may be positioned in a plane that is also substantially parallel to the plane of the critical surface.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 31, 2006
    Assignee: Finisar Corporation
    Inventors: Chris K. Togami, Stephan C. Burdick, Stephen C. Gordy
  • Patent number: RE39766
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates disposed sequentially one above the other; first, second, third and fourth signal wiring layers; first, second and third ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 7.5 mil. Each of the second and sixth insulating substrates has a thickness ranging from 3 to 13 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 15 mil. The fourth insulating substrate has a thickness ranging from 2 to 6 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first and second ground wiring layers. The third signal wiring layer has a third resistance with respect to the third ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: August 14, 2007
    Assignee: Mitac Technology Corp.
    Inventor: Yu-Chiang Cheng
  • Patent number: RE40068
    Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: February 19, 2008
    Assignees: Mitac Technology Corp., Mitac International Corp.
    Inventor: Yu-Chiang Cheng