Abstract: An electronic device can include a first die having a first terminal at a first front side, and a second die having a second terminal at a second front side and a through via. In one aspect, a process of forming the electronic device includes supplying a second substrate including a die location of the second die. The process can also include attaching the second substrate to a handling substrate and singulating the second die from the second substrate before removing the handling substrate. In another aspect, the handling substrate can include a rigid substrate. The process can include orienting the front side of the first die and a back side of the second substrate front-to-back with respect to each other. In yet another aspect, the first terminal is electrically connected to the through via and the second terminal. In one embodiment, the electronic device can include a third die.

Abstract: A method of forming a suspension object on a monolithic substrate is provided. A silicon base layer of the monolithic substrate has a circuit layer composed of at least one wet etching region, at least one circuit region, and at least one microstructure region. The wet etching region is used to partition the circuit region and the microstructure region, and extends downwards to a surface of the silicon base layer, so as to form an etching path for etching the silicon base layer from above the substrate. Next, an upper surface and a lower surface of the silicon base layer are respectively etched through dry etching, such that the microstructure region is suspended.

Abstract: An integrated circuit package system is provided in which an interposer of predetermined thickness including a central cavity is formed. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.

Abstract: A method of manufacturing a light emitting device includes: a first step of forming on a supporting substrate made of a stainless steel, a plurality of conductive members each including a first region containing Au and a second region containing a metallic member having a diffusion coefficient with respect to a metal in the stainless steel smaller than a diffusion coefficient of Au with respect to the metal in the stainless steel, a second step of forming a base member made of a light-blocking resin on the supporting substrate between the conductive members, a third step of bonding a light emitting element on an upper surface of a conductive member through an adhesive member, a fourth step of covering the light emitting element with an optically transmissive sealing member, and a fifth step of removing the supporting substrate and individually separating the light emitting devices.

Abstract: A method of manufacturing a semiconductor device, including the following steps, forming a resin layer on a surface of a semiconductor chip, the surface is provided with a bump formed thereon, the resin layer having photosensitivity and adhesiveness, exposing an upper surface of the bump by removing a part of the resin layer right above the bump by exposing and then developing the resin layer, and bonding the semiconductor chip provided with a resin film formed of the resin layer face-down to a substrate, the bump of the semiconductor chip and a conductive section of the substrate being electrically connected by the resin film functioning as an adhesive.

Abstract: An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads. The relocated bond pads are positioned near an inner edge of the first die that is adjacent to an inner edge of the second die. Each relocated bond pad is coupled to a corresponding bond pad on the second die through a respective bonding wire. The first die further includes a plurality of original bond pads. The redistribution layer further includes at least one intermediate bond pad electrically interconnected through a respective conductive trace to a corresponding original bond pad. Each intermediate bond pad is electrically connected to a corresponding relocated bond pad through a respective bond wire.

Abstract: A method is disclosed for attaching an interconnection plate to semiconductor die within leadframe package. A base leadframe is provided with die pad for attaching semiconductor die. An interconnection plate is provided for attachment to the base leadframe and semiconductor die. Add a base registration feature onto base leadframe and a plate registration feature onto interconnection plate with the registration features designed to match each other such that, upon approach of the interconnection plate to base leadframe, the two registration features would engage and guide each other causing concomitant self-aligned attachment of the interconnection plate to base leadframe. Next, the interconnection plate is brought into close approach to base leadframe to engage and lock plate registration feature to base registration feature hence completing attachment of the interconnection plate to semiconductor die and forming a leadframe package.

Abstract: A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.

Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.

Abstract: A method for producing semiconductor components and a component obtainable by such a method is disclosed. The method comprises the following steps: fixing a conductive film on a carrier; adhesively bonding semiconductor chips onto the conductive film using an adhesive layer, wherein active surfaces of the semiconductor chips, the active surfaces having connection contacts, are situated on that side of the chips which faces the film; overmolding the chips adhesively bonded onto the conductive film with a molding compound; and releasing the conductive film with the overmolded chips from the carrier. In this case, the adhesive layer is structured in such a way that at least connection contacts of the semiconductor chips are free of the adhesive layer and are kept free of the molding compound.

Abstract: In this manufacturing method of a semiconductor device, a metal plate having a plurality of projection electrodes in each of a plurality of semiconductor device formation areas is prepared. Next, the projection electrodes of each of the semiconductor formation areas are aligned corresponding to external connection electrodes of each semiconductor construction, and each semiconductor construction is separately arranged on the projection electrodes in the semiconductor device formation areas. Next, an insulating layer formation sheet is arranged on the metal plate, and the metal plate and the insulating layer formation sheet are joined by heat pressing. Then, the metal plate is patterned and a plurality of upper layer wirings that connect to the projection electrodes is formed.

Abstract: A method for manufacturing of a stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer; and mounting a top integrated circuit package over the intermediate integrated circuit package.

Abstract: The present invention relates to a manufacturing process of a sub-module having an electromagnetic shield. Initially, a meta-module having circuitry for two or more sub-modules is formed. An overmold body is placed over the circuitry for all of the sub-modules. The overmold body of the meta-module is sub-diced to expose a metallic layer grid around each of the sub-modules. Next, an electromagnetic shield is applied to the exterior surface of the overmold body of each of the sub-modules and in contact with the metallic layer grid. The meta-module is then singulated to form modules having two or more sub-modules.

Abstract: The disclosure is directed to method for manufacturing an electro-optical device. In one example, a method comprises forming a plurality of scribe lines in a substrate; forming cracks in the substrate which pass from the scribe lines through the substrate; and forming a plurality of dicing lines in the substrate along the scribe lines and the cracks. In one example, the dicing lines are formed at a depth that is less than a thickness of the substrate. This abstract is intended only to aid those searching patents, and is not intended to be used to interpret or limit the scope or meaning of the claims in any manner.

Abstract: A semiconductor device has a plurality of similar sized semiconductor die each with a plurality of bond pads formed over a surface of the semiconductor die. An insulating layer is formed around a periphery of each semiconductor die. A plurality of conductive THVs is formed through the insulating layer. A plurality of conductive traces is formed over the surface of the semiconductor die electrically connected between the bond pads and conductive THVs. The semiconductor die are stacked to electrically connect the conductive THVs between adjacent semiconductor die. The stacked semiconductor die are mounted within an integrated cavity of a substrate or leadframe structure. An encapsulant is deposited over the substrate or leadframe structure and the semiconductor die. A thermally conductive lid is formed over a surface of the substrate or leadframe structure. The stacked semiconductor die are attached to the thermally conductive lid.

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.

Abstract: A method for cutting a semiconductor substrate having a front face formed with functional devices together with a die bonding resin layer. A wafer having a front face formed with functional devices is irradiated with laser light while positioning a light-converging point within the wafer with the rear face of the wafer acting as a laser light incident face, so as to form a starting point region for cutting due to a modified region within the wafer along a cutting line. When an expansion film is attached to the rear face by way of a die bonding resin layer after forming the starting point region and then expanded, a fracture can be generated from the starting point region which reaches the front face and rear face, consequently, the wafer and die bonding resin layer can be cut along the cutting line.

Abstract: A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The method includes compressing the at least two conductive elements so that the remote surfaces thereof lie in a common plane, and after the compressing step, providing an encapsulant material around the at least two conductive elements for supporting the microelectronic package and so that the remote surfaces of the at least two conductive elements remain accessible at an exterior surface of the encapsulant material.

Abstract: A method of fabricating a packaging structure includes cutting a panel of packaging substrate into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting and packaging a semiconductor chip on each of the packaging substrate unit to form package blocks each having multiple packaging structure units; and cutting package blocks to form a plurality of package units. In the method, the alignment difference between the packaging structure units in each package block is minimized by appropriately cutting and forming substrate blocks to achieve higher precision and better yield, and also packaging of semiconductor chips can be performed on all package units in the substrate blocks, thereby integrating fabrication with packaging at one time to improve production efficiency and reduce the overall costs as a result.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: Disclosed are a light emitting diode package and a manufacturing method thereof. According to an embodiment of the present invention, the method includes: manufacturing a package main body having a plurality of cavities, the cavities being formed in a line on one surface, through molding by putting thermoplastic polymer into a previously produced mold; forming an electrode passing through the package main body; mounting a light emitting diode chip on a basal surface of the each cavity formed in the package main body; connecting electrically the light emitting diode chip and the electrode by using a bonding means; and sealing the light emitting diode chip and the bonding means by using a molding resin.

Abstract: A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball.

Abstract: A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

Abstract: A semiconductor method comprises a method for making a device comprising: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and a plurality of side surfaces between the surface of the surface protecting film and the second main surface; an insulating extension portion formed so as to surround the side surfaces of the semiconductor chip; a plurality of wiring patterns electrically connected to the electrode pads, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed on the wiring patterns such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the extension portion.

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved by forming different height first and second conductive layer above a substrate. A first patterned photoresist layer is formed over the substrate. A first conductive layer is formed in the first patterned photoresist layer. The first patterned photoresist layer is removed. A second patterned photoresist layer is formed over the substrate. A second conductive layer is formed in the second patterned photoresist layer. The height of the second conductive layer, for example 25 micrometers, is greater than the height of the first conductive layer which is 5 micrometers. The first and second conductive layers are interposed between each other close together to minimize pitch and increase I/O count while maintaining sufficient spacing to avoid electrical shorting after bump formation. An interconnect structure is formed over the first and second conductive layers.

Abstract: A capped micro-electro-mechanical systems (MEMS) device is formed using a device wafer and a cap wafer. The MEMS device is located on a frontside of the device wafer. A frontside of a cap wafer is attached to the frontside of the device wafer. A first stressor layer having a tensile stress is applied to a backside of the cap wafer after attaching the frontside of the cap wafer to the frontside of the device wafer. The first stressor layer and the cap wafer are patterned to form an opening through the first stressor layer and the cap wafer after applying the first stressor layer. A conductive layer is applied to the backside of the cap wafer, including through the opening to the frontside of the device wafer.

Abstract: Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, using a release member having a phase change material. Specifically, IC elements/components can be selectively received, stored, inspected, repaired, and/or released in a scalable manner during the assembly of IC chips by inducing phase change of the phase change material. The release member can be glass with the IC elements grown on the glass. In some embodiments, the release member can be used for a low cost placement of the IC elements in combination with an intermediate transfer layer.

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

Abstract: A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.

Abstract: Embodiments of the present invention provide an LED having a Wavelength Shift Layer (WSL) and method of manufacture. Specifically, under embodiment of the present invention, a WSL layer is applied over an LED chip. The WSL itself typically comprises two layers: an adhesion layer applied over a set (at least one) of LED chips, and a conformal coating over the adhesion layer. The adhesion layer provides improved adhesive effect of the conformal coating to the LED chip(s). The conformal coating is comprised of a particular phosphor ratio that is determined based on a wavelength measurement of the underlying LED chip(s). Specifically, under the present invention, a wavelength of a light output by an LED chip(s) (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Typically, the phosphor ratio of is comprised of at least one of the following colors: yellow, green, or red. Regardless, this conformal coating is applied over a glue layer that itself is applied over the LED chip.

Abstract: A method fabricates a packaging structure, including cutting a complete panel of packaging substrates with a large area into a plurality of packaging substrate blocks each having a plurality of packaging substrate units; mounting a semiconductor chip on each of the packaging substrate units and securing the semiconductor chip to the packaging substrate unit with a molding material, to form a plurality of packaging structure blocks each having a plurality of packaging structure units; and cutting the packaging structure block into a plurality of packaging structure units. Accordingly, each of the packaging structure unit has a moderate area, the alignment difference between the packaging structure units in each of the packaging structure blocks can be reduced, and the semiconductor chips for all the packaging substrate units in each of the packaging substrate blocks can be packaged at one time. Therefore, the yield is increased and the overall cost is reduced.

Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.

Abstract: A method for the separation of multiple dies during semiconductor fabrication is described. On an upper surface of a semiconductor wafer containing multiple dies, metal layers are deposited everywhere except where a block of stop electroplating material exists. The stop electroplating material is obliterated, and a barrier layer is formed above the entire remaining structure. A sacrificial metal element is added above the barrier layer, and then the substrate is removed. After the semiconductor material between the individual dies is eradicated, any desired bonding pads and patterned circuitry are added to the semiconductor surface opposite the sacrificial metal element, a passivation layer is added to this surface, and then the sacrificial metal element is removed. Tape is added to the now exposed barrier layer, the passivation layer is removed, the resulting structure is flipped over, and the tape is expanded to separate the individual dies.

Abstract: A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a step of covering a plurality of base plates in which respective semiconductor chips are mounted, by means of a sealing resin such that a plurality of base plates are spaced apart from each other, and a step of cutting the sealing resin between a plurality of base plates.

Abstract: A method for manufacturing a semiconductor device includes forming a first opening in a substrate to expose an interconnect structure, forming a seed film on the substrate, forming a first projecting electrode buried inside the first opening protruding outward from the substrate, forming a first metal film on the first projecting electrode, attaching a first supporting substrate to the substrate with a first adhesion layer, forming a second opening in the substrate to expose the interconnect structure, forming a second projecting electrode buried inside the second opening and protruding outward from the substrate, forming a second metal film on the second projecting electrode, attaching a second supporting substrate to the substrate with a second adhesion layer, removing the first supporting substrate, the first adhesion layer, and an exposed part of the seed film, removing the second supporting substrate and the second adhesion layer, and cutting the substrate into the plurality of chips.

Abstract: A method for packaging a semiconductor die or assembling a semiconductor device that includes a heat spreader begins with attaching the heat spreader to a film and dispensing a mold compound in granular form onto the film such that the mold compound at least partially covers the film and the heat spreader. The film with the attached heat spreader is placed in a first mold section. A substrate having a semiconductor die attached and electrically coupled to it are placed in a second mold section and then the first and second mold sections are mated such that the die is covered by the heat spreader. The granular mold compound is then melted so that the mold compound covers the die and sides of the heat spreader. The first and second mold sections then are separated. The film, which adheres to the substrate, is removed to expose a top surface of the heat spreader, and thus a semiconductor device is formed.

Abstract: A method and system for providing energy assisted magnetic recording (EAMR) heads including EAMR transducers are described. The method and system include aligning a laser bar to the EAMR heads on a substrate. The laser bar includes lasers in locations corresponding to a portion of the EAMR transducers. The method and system also include bonding the laser bar to the substrate and removing a portion of the laser bar to separate the plurality of lasers. The substrate is separated into the EAMR heads.

Abstract: A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable.

Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.

Abstract: A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body.

Abstract: A description is given of a device, including a semiconductor chip, a first metal layer laterally extending over the semiconductor chip, the first metal layer having a first thickness. A dielectric layer laterally extends over the first metal layer, and a second metal layer laterally extends over the dielectric layer, the second metal layer having a second thickness that is at least four times larger than the first thickness.

Abstract: An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end, and is connected to the second end of the first sidewall at its first end and connected to the first side of the semiconductor device at its second end. The thickness of the first tab is less than the thickness of the bar and the thickness of the first sidewall.

Abstract: A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.