Abstract: A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.

Abstract: A method of manufacturing a semiconductor device involves the steps of: forming a plurality of product formation areas each having a circuit and a plurality of first electrode pads over a main surface of a semiconductor wafer; arranging a plurality of second electrode pads with larger pitches than the first electrode pads in each of the product formation areas; segmenting the semiconductor wafer to separate the plural product formation areas and provide a plurality of semiconductor devices each having the circuit, the plural first electrode pads and the plural second electrode pads on a first surface; and cleaning foreign matter off the first surface of the semiconductor device after the step of segmenting the semiconductor devices.

Abstract: A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of the semiconductor device into the recess of the adhesive layer; adhering the semiconductor device to the adhesive layer with the semiconductor device positioned on the support body; setting the supporting body having the semiconductor device in a resin sealing mold; supplying a resin into a cavity of the resin sealing mold; sealing the semiconductor device with the resin on the support body while using the dummy bump to inhibit displacement of the semiconductor device caused by a flow of the resin supplied into the cavity of the resin sealing mold; and removing the support body, the adhesive layer, and the dummy bump from the semiconductor device sealed with the resin.

Abstract: A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.

Abstract: Some embodiments of a chip module comprise a substrate, a semiconductor chip on the substrate, and a first layer between the substrate and the semiconductor chip, the first layer having high reflectivity for electromagnetic waves. Methods of protecting a chip module from electromagnetic radiation by interposing a protective layer between the chip and the substrate are also disclosed.

Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.

Abstract: Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.

Abstract: The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first capacitor, a first protective layer, a first metal layer and a second protective layer. The substrate has at least one via structure. The first capacitor is disposed on a first surface of the substrate. The first protective layer encapsulates the first capacitor. The first metal layer is disposed on the first protective layer, and includes a first inductor. The second protective layer encapsulates the first inductor. Whereby, the first inductor, the first capacitor and the via structure are integrated into the semiconductor package, so that the size of the product is reduced.

Abstract: A laser processing apparatus has one laser light source that simultaneously radiates laser beams with two wavelengths. Depth positions of focusing points for laser beams are gradually changed in a wafer. Three sets of modifying region groups, i.e., six layers of modifying region groups, are successively formed. One set of modifying region groups constitutes two layers and is formed at a time. The modifying region groups are separated, adjoined, or overlapped with each other along an estimated cut line of the wafer in a depth direction from a surface thereof.

Abstract: A semiconductor package system is provided including providing a cavity substrate having a cavity provided therein, attaching a metal die pad to the cavity substrate, attaching a semiconductor die in the cavity to the metal die pad, and attaching solder connectors to the cavity substrate for connection on the system board with the metal die pad on the system board.

Abstract: A method for forming a semiconductor device can include providing a patterned layer of mold compound having a plurality of individual mold compound structures overlying a base film. The plurality of mold compound structures are aligned with a plurality of semiconductor dice to interpose the individual mold compound structures between the plurality of semiconductor dice. A pressure is applied to the individual mold compound structures to fill spaces between each of the plurality of semiconductor dice with the mold compound. The mold compound structures can be formed on the base film using a photosensitive mold compound. The mold compound structures can also be formed through the use of a patterned mask and a screen printing process.

Abstract: A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.

Abstract: The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package.

Abstract: An electronic package structure and method use a conductive strip to bond die-to-die, die-to-lead, chip carrier-to-lead, or lead-to-lead. A conductive strip may carry greater current than a bonding wire, and thus may replace several bonding wires. The bonding of the conductive strip may be carried out by an SMT process, and thus requires lower cost than wire bonding processes. A conductive strip may be bonded to more than two dice or leads to save more bonding wires. A conductive strip is stronger than a bonding wire, and thus lowers the possibility of being broken.

Abstract: A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.

Abstract: A Conductive Epoxy Coating (“CEC”) process is provided for assembling semiconductor devices. The CEC process includes application of a conductive epoxy coating prior to wafer dicing and instead of dispensing epoxy/solder when performing die bonding. The CEC process generally begins with a silicon wafer. Processing of the silicon wafer includes coupling a conductive epoxy layer to a first side of the semiconductor wafer to form a coated wafer. The process cures the coated wafer and forms die from the coated wafer. The process further couples an exposed side of the conductive epoxy layer of the die to a lead frame to form a semiconductor device, and cures the semiconductor device.

Abstract: A microelectronic assembly that includes a first microelectronic element having a first rear surface. The assembly further includes a second microelectronic element having a second rear surface. The second microelectronic element is attached to the first microelectronic element so as to form a stacked package. A bridging element electrically connects the first microelectronic element and the second microelectronic element. The first rear surface of the first microelectronic element faces toward the second rear surface of the second microelectronic element.

Abstract: A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas. The solder balls are disposed on the ball-placement areas.

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

Abstract: In a semiconductor device comprising a ceramic substrate, a surface mount component, and sealing resin and obtained by division into pieces, the ceramic substrate is composed of a multiple piece substrate provided with dividing grooves for the division into pieces on both front and rear surfaces in advance, a plurality of the surface mount components are mounted on the multiple piece substrate and sealed collectively by the sealing resin, and the substrate is divided along the dividing grooves. Further, when the shortest distance from an end on the front surface of the ceramic substrate to an end of the surface mount component is set to “a” ?m, a thickness of the ceramic substrate is set to “b” ?m, and sum of depths of the dividing grooves on the front and rear surfaces of the ceramic substrate is set to “c” ?m, a relationship of a?269×c/b+151 is established.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A semiconductor device includes a semiconductor chip having a plurality of electrode pads, and a rewiring pattern having a plurality of interconnects which are connected to the electrode pads and extend over an insulation film. The semiconductor device also includes a plurality of columnar electrodes each of which has a main body section and a protrusion section, and a sealing section which has a top face having a height the same as the top faces of the protrusion sections. The semiconductor device also includes solder balls formed on the protrusion sections. The semiconductor device also has a plurality of trenches in the sealing section. Each trench has a depth which reaches the boundary between the main body and protrusion of the electrode. The side faces of the protrusion section are exposed face defined by the trenches. Each solder ball is electrically connected to the top face and side faces of the protrusion section of each electrode.

Abstract: An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by stacking a conductive film 11, a resin film 13, an integrated circuit 12, and a resin film 14 are rolled so that the resin film 14 is outside. Then, the laminated body is integrated in a roll form by softening the resin films 13, 14 by applying heat. By slicing the rolled laminated body along with the direction in which the rolled conductive film 31 appears in the cross section, an IC chip with antenna formed by the rolled conductive film 11 is formed.

Abstract: A uniform layer of non-conductive material, e.g., epoxy, is screen printed onto the backside of an integrated circuit wafer to a required thickness, and then heated until it is hard cured (C-stage). The integrated circuit wafer having the hard cured coating is then sawn apart to separate the individual integrated circuit dice. A non-conductive adhesive is dispensed onto mating faces of die attach paddles of leadframes. The dice are placed into the non-conductive adhesive and then the die and die attach paddle assembly are heated to hard cure the adhesive between the mating faces of the die and die attach paddle. This provides long term electrical isolation of the integrated circuit die from the die attach paddle, and effectively eliminates silver migration from the die attach paddle which causes conductive paths to form that increase unwanted leakage currents in the die and ultimately cause failure during operation thereof.

Abstract: A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.

Abstract: In a method of manufacturing an electronic component package, first, there is fabricated a wafer incorporating a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages, and a retainer for retaining the plurality of sets of external connecting terminals, the wafer including a plurality of pre-base portions that will be separated from one another later to be bases of the electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chips are connected to the external connecting terminals. Next, the electronic component chips are sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.

Abstract: A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening.

Abstract: An integrated circuit package system includes: providing a lower interposer substrate with lower exposed conductors; attaching a die over the lower interposer substrate; applying a stack encapsulant over the die and the lower interposer substrate having the lower exposed conductors partially exposed adjacent the stack encapsulant; and attaching an upper interposer substrate having upper exposed conductors over the stack encapsulant and with the upper exposed conductors substantially exposed.

Abstract: A method and apparatus for coating a plurality of semiconductor devices that is particularly adapted to coating LEDs with a coating material containing conversion particles. One method according to the invention comprises providing a mold with a formation cavity. A plurality of semiconductor devices are mounted within the mold formation cavity and a curable coating material is injected or otherwise introduced into the mold to fill the mold formation cavity and at least partially cover the semiconductor devices. The coating material is cured so that the semiconductor devices are at least partially embedded in the cured coating material. The cured coating material with the embedded semiconductor devices is removed from the formation cavity. The semiconductor devices are separated so that each is at least partially covered by a layer of the cured coating material.

Abstract: A phosphor coating method for fabricating a light-emitting semiconductor is provided. The phosphor coating method comprises the steps as follows: First a light emitting semiconductor wafer having a plurality of die units formed thereon is provided, and a photoresist is then formed on the light emitting semiconductor wafer to cover the die units. A pattern process is conducted to form a plurality of openings associated with the die units, whereby each die can be exposed via one of the openings. Subsequently, a compound mixed with phosphor is filled into the openings.

Abstract: A lead frame and a method of making a lead frame for a semiconductor package. The lead frame is formed by stamping a lead frame material into a desire configuration. The stamped lead frame is then affixed to a support material. When assembling a semiconductor package using the lead frame, during saw singuation, the saw does not have to cut through much lead frame material. Thus, the saw blade does not wear quickly.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing two parts (13, 14) comprising electrically insulating material such as plastic; providing members (21, 22, 23) comprising electrically conductive material; providing a microelectronic device (30); positioning the electrically conductive members (21, 22, 23) and the microelectronic device (30) on the electrically insulating parts (13, 14); and placing the electrically insulating parts (13, 14) against each other, wherein microelectronic device (30) and portions of the electrically conductive members (21, 22, 23) are sandwiched between the electrically insulating parts (13, 14). The electrically conductive members (21, 22, 23) are intended to be used for realizing contact of the micro-electronic device (30) arranged inside the package (1) to the external world.

Abstract: A shielded semiconductor device is made by embedding a ground shield between layers of a substrate. Semiconductor die are mounted to the substrate over the ground shields. An encapsulant is formed over the semiconductor die and substrate. The encapsulant is diced to form dicing channels between the semiconductor die. A plurality of openings is drilled into the substrate along the dicing channels down through the ground shield on each side of the semiconductor die. A top shield is formed over the semiconductor die. The openings in the substrate are filled with a shielding material to electrically and mechanically connect the top shield to the ground shield. The substrate is singulated to separate the semiconductor die with top shield and ground shield into individual semiconductor devices. IPDs in the semiconductor die generate electromagnetic interference which is blocked by the respective top shield and ground shield.

Abstract: A package substrate having a semiconductor component embedded therein and a method of fabricating the same are provided, including: providing a semiconductor chip with electrode pads disposed on an active surface thereof; forming a passivation layer on the active surface and the electrode pads; forming on the passivation layer metal pads corresponding in position to the electrode pads, respectively, so as for the semiconductor chip to be fixed in position to an opening of a substrate body; forming a first dielectric layer on the semiconductor chip and the substrate body; forming dielectric layer openings by laser and preventing the electrode pads from being penetrated by the metal pads; removing the metal pads and the passivation layer in the dielectric layer openings so as to expose the electrode pads therefrom; and forming a first wiring layer on the first dielectric layer for electrical connection with the electrode pads.

Abstract: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

Abstract: This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.

Abstract: To a transparent substrate (20) on which a plurality of spacers (5) are formed, an infrared cut filter (IRCF) substrate (27) is attached. The IRCF substrate (27) has a coefficient of thermal expansion smaller than the transparent substrate (20) and approximately equal to a wafer (31). Next, the transparent substrate (20) is diced into plural pieces to form a plurality of cover glasses (6). Then heat cure adhesive (32) is coated on each spacer (5) and the spacers (5) are attached on the wafer (31) on which a plurality of light receiving section (3) and pads (10) are previously formed. Finally, the heat cure adhesive (32) is heated to be cured.

Abstract: A stacked microelectronic assembly is fabricated from a structure which includes a plurality of first microelectronic elements having front faces bonded to a carrier. Each first microelectronic element may have a first edge and a plurality of first traces extending along the front face towards the first edge. After exposing at least a portion of the first traces, a dielectric layer is formed over the plurality of first microelectronic elements. After thinning the dielectric layer, a plurality of second microelectronic elements are aligned and joined with the structure such that front faces of the second microelectronic elements are facing the rear faces of the plurality of first microelectronic elements. Processing is repeated to form the desirable number of layers of microelectronic elements. In one embodiment, the stacked layers of microelectronic elements may be notched at dicing lines to expose edges of traces, which may then be electrically connected to leads formed in the notches.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of bumps is formed on the semiconductor wafer. The bumps are electrically connected to contact pads on an active surface of the die. The bumps can also be pillars or stud bumps. A first encapsulant is deposited over the bumps. The semiconductor wafer is singulated to separate the die by cutting channels partially through the wafer and back grinding the wafer down to the channels. A second encapsulant is deposited over the die. A first interconnect structure is formed over a first surface of the second encapsulant. The first interconnect structure is electrically connected to the bumps. A second interconnect structure is formed over a second surface of the second encapsulant. Secondary semiconductor components can be stacked over the second interconnect structure. A third encapsulant is deposited over the stacked secondary components and second interconnect structure.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Abstract: A semiconductor device has a first semiconductor chip 10 molded with a resin 12, a first metal 14 provided in the resin 12 in a circumference of the first semiconductor chip 10, and being exposed on a lower surface of the resin 12, a second metal 16 provided in the resin 12 over the first metal 14, and being exposed on an upper surface of the resin 12, and a first wire 18 coupling the first semiconductor chip 10 to the first metal 14 and the second metal 16. The first wire 18 is coupled to the first metal 14 and the second metal 16 so as to be sandwiched therebetween.

Abstract: Techniques for dicing wafer assemblies containing multiple metal device dies, such as vertical light-emitting diode (VLED), power device, laser diode, and vertical cavity surface emitting laser device dies, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, such techniques are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.

Abstract: A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.

Abstract: A chip package structure is provided, includes a chip that having a plurality of pads and an adhesive layer on the back side; an encapsulated structure is covered around the four sides of the chip to expose the pads, and the through holes is formed within the encapsulated structure; a patterned first protective layer is formed on the portion surface of encapsulated structure, the portion of active surface of the chips, and the pads of the chip and the through holes are to be exposed; a metal layer is formed on the portion surface of the patterned first protective layer and formed to electrically connect the pads and to fill with the through holes; the patterned second protective layer is formed on the patterned first protective layer and the portion of metal layer, and the portion surface of metal layer is to be exposed; a patterned UBM layer is formed on the exposed surface of the metal layer and the portion surface of the patterned second protective layer; and the conductive elements is formed on the patter

Abstract: The method comprises providing multiple chips attached to a first carrier, stretching the first carrier so that the distance between adjacent ones of the multiple chips is increased, and applying a laminate to the multiple chips and the stretched first carrier to form a first workpiece embedding the multiple chips, the first workpiece having a first main face facing the first carrier and a second main face opposite to the first main face.

Abstract: A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.

Abstract: An antenna web can include an RFID antenna on a first side of a substrate. An adhesive can be laminated on a second side of the substrate. The antenna web can then be cut into individual segments for use in constructing an RFID label.

Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.