Abstract: An electronic device substrate is provided with a thin-plate core substrate; a metal electrode provided on the core substrate and electrically connected to an electrode of an electronic component to be packaged thereon; and an electrical insulation layer on which is mounted the electronic component, and which is provided to surround the metal electrode.

Abstract: A method for manufacturing a microelectronic package (1) comprises the steps of providing two parts (13, 14) comprising electrically insulating material such as plastic; providing members (21, 22, 23) comprising electrically conductive material; providing a microelectronic device (30); positioning the electrically conductive members (21, 22, 23) and the microelectronic device (30) on the electrically insulating parts (13, 14); and placing the electrically insulating parts (13, 14) against each other, wherein the microelectronic device (30) and portions of the electrically conductive members (21, 22, 23) are sandwiched between the electrically insulating parts (13, 14). The electrically conductive members (21, 22, 23) are intended to be used for realizing contact of the microelectronic device (30) arranged inside the package (1) to the external world.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate; and forming integrated passive devices in the plurality of dielectric layers. The semiconductor substrate is then removed from the plurality of dielectric layers. A dielectric substrate is bonded onto the plurality of dielectric layers.

Abstract: The present invention provides an LED and method of manufacture in which white light is produced. Specifically, under the present invention, a wavelength of a light output by an LED (e.g., blue or ultra-violet (UV)) is measured (e.g., at the wafer level). Based on the wavelength measurement, a conformal coating is applied to the LED. The conformal coating has a phosphor ratio that is based on the wavelength. Moreover, the phosphor ratio is comprised of at least one of the following colors: yellow, green, or red. The light output of the LED is then converted to white light using the conformal coating. In a typical embodiment, these steps are performed at the wafer level so that uniformity and consistency in results can be better obtained. However, it should be understood that the same teachings could be applied at the chip level. Moreover, several different approaches can be implemented for isolating the coating area. Examples include the use of a paraffin wax, a silk screen, or a photo resist.

Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.

Abstract: A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Abstract: In a method of manufacturing an optical device, a whole substrate is first prepared which has a plurality of regions corresponding to substrates constituting a plurality of optical devices, respectively. A plurality of chips are then mounted to the plurality of regions, respectively. A whole sealing member having a plurality of sealing members is integrally attached to the whole substrate to form an intermediate body. The intermediate body is divided into the above-described regions. Thus, the optical device having a substrate, a chip as an optical element mounted to the substrate and a sealing member with transparency provided at the substrate for the purpose of sealing the chip is manufactured. This manufacturing method improves the efficiency of manufacturing an optical device.

Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Abstract: A semiconductor device includes a substrate for transmitting light, a wiring layer provided on the substrate, a semiconductor chip formed on the wiring layer, a columnar electrode, a sealant, and an external connection terminal electrically connected to the semiconductor chip via the wiring layer and protruding electrode. The device includes a cut surface formed by dicing and constituted by only the substrate and the sealant. Since the cut surface has a single-layer structure as a result of forming the sealant in a single step, moisture cannot infiltrate through the sealant, hence a device resistant to corrosion and operational defects is provided.

Abstract: Provided is a semiconductor package and method of manufacturing same. The method includes: forming a plurality of semiconductor chips which have the same pattern direction on a semiconductor substrate, each of which includes a memory cell region, a peripheral region and a pad region, and in each of which the pad region is disposed in an edge region; separating the semiconductor chips, which are formed on the semiconductor substrate, from one another; and disposing semiconductor chips, which are selected from the separated semiconductor chips, on a package substrate by changing the pattern directions of the selected semiconductor chips and arranging pad regions of the selected semiconductor chips in a center region of the package substrate.

Abstract: An intermediate structure for semiconductor devices includes a wiring board, a plurality of semiconductor chips mounted on the wiring board, and a sealing body for collectively sealing the plurality of semiconductor chips and having a region with a different thickness.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract: A fabricating method includes adhering an exposed surface of a first solid adhesive film to a first substrate. The second surface of the first solid adhesive film is exposed and adhered to a second substrate. A third substrate is adhered to a second substrate via a patterned second solid adhesive film, and a diaphragm layer is adhered to the third substrate via a patterned third solid adhesive film. A fourth solid adhesive film with a removable release film is adhered to the first substrate covered, followed by slicing to form wafer level lens modules.

Abstract: The invention relates to a transponder inlay (11) for manufacturing a layered structure (40) for a personal document with a substrate layer (12) for arranging a transponder unit (15) that includes an antenna coil (13) and a chip module (14) and which is situated on a contact surface (17) of the substrate layer, wherein the chip module (14) is accommodated in a window opening (30) formed in the substrate layer (12) in such a way that a chip carrier (23) of the chip module rests with its circumferential edge on a compressed peripheral shoulder (24) of the window opening (30); the invention also relates to a method for manufacturing the transponder inlay. In addition, the present invention relates to a layered structure for a personal document, which is provided with such a transponder inlay, and an identification document having such a layered structure.

Abstract: A circuit board and a method of manufacturing the circuit board are provided. The method includes forming at least one protruded bump on a first side of a conductive board, forming a dielectric layer on the first side of the conductive board where the at least one bump is formed so as to cover the at least one bump; and etching a second side of the conductive board so as to partially remove the board to form a pattern.

Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A method for production of a plurality of semiconductor chips (6) in a wafer composite. A semiconductor layer sequence (2) is grown on a growth substrate (1), metallization (3) is applied to the semiconductor layer sequence (2), a metal layer (4) is electrochemically deposited onto the metallization (3), and the semiconductor layer sequence (2) is then structured and separated to form individual semiconductor chips (6). The electrochemically applied metal layer (4) is particularly suitable for use as a heat spreader, for dissipation of the heat produced by the semiconductor chips (6).

Abstract: A method of making finger sensor packages may include advancing a flexible circuit tape along a predetermined path of travel. The flexible circuit tape may include a flexible layer and conductive traces thereon defining individual flexible circuits. The method may include, as the flexible circuit tape is advanced along the path of travel, securing a respective finger sensing integrated circuit (IC) and surrounding sensor package frame to each flexible circuit, applying at least one fluid fill material adjacent each finger sensor IC while using the corresponding sensor package frame as a dam to thereby define finger sensor packages, and stamping out the finger sensor packages from the flexible circuit tape to form at least one flush common edge of each sensor package frame and individual flexible circuit.

Abstract: This application relates to a method of manufacturing a semiconductor device comprising: providing multiple chips each comprising contact elements on a first main face of each of the multiple chips, and a first layer applied to each of the first main faces of the multiple chips; placing the multiple chips over a carrier with the first layers facing the carrier; applying encapsulation material to the multiple chips and the carrier to form an encapsulation workpiece embedding the multiple chips; and removing the carrier from the encapsulation workpiece.

Abstract: A method of manufacturing an integrated circuit packaging system includes: providing an inner lead and an outer lead, the inner lead having an inner peripheral side with a non-linear contour; forming a bump contact, having a groove in and a mesa from the inner lead or the outer lead, the groove adjacent to the mesa; mounting a first device adjacent to the inner lead; connecting a second device to the mesa; and forming an encapsulation material over the first device, the inner lead, and the outer lead and covering the second device.

Abstract: Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plurality of leads disposed adjacent to the aperture. The package further comprises a semiconductor disposed in the aperture of the leadframe with its top surface substantially flush with the leadframe's first surface, and at least one gap between at least one side surface of the semiconductor die and at least one lead of the leadframe. A body of electrically insulating material is disposed in the at least one gap. A plurality of conductive members interconnect leads of the leadframe with conductive regions on the die's top surface, with at least one conductive member having a portion disposed over at least a portion of the body of insulating material.

Abstract: A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices.

Abstract: A method of manufacturing an array type semiconductor laser device. The method includes forming first and second electrodes on lower and upper surfaces of a wafer comprising a plurality of semiconductor laser arrays having a plurality of laser emission regions, and forming a metal bonding layer on the second electrode of the wafer. The method also includes dicing the wafer into the semiconductor laser arrays and mounting each of the individually separated semiconductor laser arrays on a base with the surface of the metal bonding layer in contact with the base. The method further includes melting the metal bonding layer to fix the mounted semiconductor laser array on the base.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: A semiconductor-chip exfoliating device for exfoliating a semiconductor chip 1 from an adhesive sheet 6 is provided. The device includes a backup holder 28 for holding the adhesive sheet 6 so that semiconductor chips 1 turn upward, a pair of needle pins arranged on a backside of the holder 28 to lift off the adhesive sheet 6 from the holder 28 through through-holes 31a, 31b in the holder 28 and a sliding unit 33 arranged on the backside of the holder 28 to slide one needle pin 30b in a direction to depart from the other needle pin 30a. By the sliding unit 33, the interval between the needle pins 30a, 30b can be changed so as to cope with a variation of semiconductor chips 1, 1A.

Abstract: In a semiconductor device, corner portions of a inner insulating film are chamfered, and hence a damage is less likely to reach the corner portion of the inner insulating film, though the corner portion of an outer insulating film is damaged. Therefore, a hermeticity of a semiconductor element can be effectively maintained, and the yield of semiconductor pellets can be improved. Moreover, since it is not necessary to chamfer the corner portion of the outer insulating film, the structure remains simple and the productivity can be improved.

Abstract: A method of through substrate via (TSV) die assembly includes positioning a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated to form a plurality of singulated stacked die assemblies.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.

Abstract: Methods for integrating quartz-based resonators with electronics on a large area wafer through direct pick-and-place and flip-chip bonding or wafer-to-wafer bonding using handle wafers are described. The resulting combination of quartz-based resonators and large area electronics wafer solves the problem of the quartz-electronics substrate diameter mismatch and enables the integration of arrays of quartz devices of different frequencies with the same electronics.

Abstract: A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps.

Abstract: A packaged microchip has a base, at least one spacer coupled to the base, and first and second microchips mounted to the at least one spacer. The at least one spacer is configured to substantially prevent leakage current between the first and second microchips.

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) preparing a wafer including a first circuit formation region and a first surrounding region, (b) laminating a first chip on the first circuit formation region, (c) pouring a first underfill into a first space between the first circuit formation region and the first chip from the first surrounding region, (d) hardening the first underfill, (e) forming a laminated structure comprised of a first chip block that includes a second chip including the first circuit formation region, the first chip, and the first underfill by conducting dicing with respect to the wafer; and (f) laminating the laminated structure on a substrate.

Abstract: A semiconductor wafer includes a plurality of semiconductor die. Contact pads are formed on an active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. Solder bumps are formed on the contact pads in both the active area of the semiconductor die and non-active area of the semiconductor wafer between the semiconductor die. The I/O terminal count of the semiconductor die is increased by forming solder bumps in the non-active area of the wafer. An encapsulant is formed over the solder bumps. The encapsulant provides structural support for the solder bumps formed in the non-active area of the semiconductor wafer. The semiconductor wafer undergoes grinding after forming the encapsulant to expose the solder bumps. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a package substrate with solder paste or socket.

Abstract: A method includes providing an integral array of first carriers, arranging first semiconductor chips on the first carriers, and arranging an integral array of second carriers over the semiconductor chips.

Abstract: In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed.

Abstract: In a semiconductor module where a metal sheet, an insulating layer and a circuit element are stacked in a manner that the insulating layer is penetrated with a bump structure, the connection reliability of the bump structure and the circuit element is enhanced. A semiconductor wafer is prepared where a semiconductor substrate having electrodes and protective film on the surface are arranged in a matrix shape. On the surface of the semiconductor substrate, an insulating layer is held between the substrate and a copper sheet, integrally formed with bumps, having grooves in the vicinity of the bumps. The semiconductor substrate, the insulating layer and the copper sheet are press-bonded by a press machine into a single block. The bump penetrates the insulating layer, and the bump and the electrode are electrically connected together. An extra part of the insulating layer pushed out by the bump flows into the groove.

Abstract: Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion extending continuously through an aperture in two or more such elements. Computer systems include such semiconductor device assemblies. Fasteners for securing together such elements include an elongated portion, a first end piece, and a second end piece. Methods of securing together a plurality of semiconductor devices include inserting an elongated portion of a fastener through an aperture in a first semiconductor device and an aperture in at least one additional semiconductor device. Circuit boards include a plurality of apertures disposed in an array corresponding to an array of apertures in a semiconductor device assembly. Each aperture is sized and configured to receive a fastener for maintaining an assembled relationship between the semiconductor device assembly and the circuit board.

Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.

Abstract: One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method.

Abstract: A method of manufacture of an integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract: A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Abstract: A semiconductor device has a TSV wafer and semiconductor die mounted over the TSV wafer. A channel is formed through the TSV wafer. An encapsulant is deposited over the semiconductor die and TSV wafer. Conductive TMV are formed through the encapsulant over the conductive TSV and contact pads of the semiconductor die. The conductive TMV can be formed through the channel. A conductive layer is formed over the encapsulant and electrically connected to the conductive TMV. The conductive TMV are formed during the same manufacturing process. An insulating layer is formed over the encapsulant and conductive layer. A plurality of semiconductor die of the same size or different sizes can be stacked over the TSV wafer. The plurality of semiconductor die can be stacked over opposite sides of the TSV wafer. An internal stacking module can be stacked over the semiconductor die and electrically connected through the conductive TMV.

Abstract: A chip multiprocessor die supports optional stacking of additional dies. The chip multiprocessor includes a plurality of processor cores, a memory controller, and stacked cache interface circuitry. The stacked cache interface circuitry is configured to attempt to retrieve data from a stacked cache die if the stacked cache die is present but not if the stacked cache die is absent. In one implementation, the chip multiprocessor die includes a first set of connection pads for electrically connecting to a die package and a second set of connection pads for communicatively connecting to the stacked cache die if the stacked cache die is present. Other embodiments, aspects and features are also disclosed.

Abstract: The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages.

Abstract: A submount wafer, having mounted on it an array of LEDs with a phosphor layer, is positioned with respect to a mold having an array of indentions. A mixture of silicone and 10%-50%, by weight, TiO2, is dispensed between the wafer and the indentions, creating a molded substantially reflective material. The molded mixture forms a reflective wall covering the sidewalls of the LED. The reflective material is then cured, and the submount wafer is separated from the mold such that the reflective material covering the sidewalls contains light emitted from the LED. The submount wafer is then diced. A piece (e.g., a reflector, support bracket, etc.) may then be affixed to the submount so the LED protrudes through a center hole in the piece. The inner edge of the piece is easily formed so that it is located at any height above or below the top surface of the LED.

Abstract: A low-cost wafer-level packaging (WLP) method for attaching glass to optical image-sensor devices on a semiconductor wafer in order to increase the yield of image-sensor modules during later steps of assembly. One embodiment relates to applications with image-sensors (and microlenses) fabricated on a wafer. A glass wafer is singulated, aligned to mirror the die pattern on an image-sensor wafer, and then bonded to the image-sensor wafer such that optical adhesive forms a layer between the each image-sensor and its glass cover. Another embodiment applies cavity walls to singulated glass covers, which are then attached to image sensors which may be formed on a single wafer. The wafer can then be singulated and a plurality of image sensor packages is formed.

Abstract: In the fabrication of an integrated circuit, a trench with a sidewall is formed along the periphery of the integrated circuit and the substrate is back-lapped to a thickness smaller than the trench depth to separate the integrated circuit from other integrated circuits on the same substrate. Increased protection against contaminant diffusion into the integrated circuit through the sidewall at the periphery is obtained with one or more protective layers. The substrate area useful for integrated circuit fabrication is also increased.