Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Abstract: The present invention provides an LOC package wherein the lead frame is in direct contact with the semiconductor device. The lead frame, which includes openings, is positioned directly on the semiconductor device. An adhesive material is applied in the opening in the lead frame. This adhesive material contacts both the lead frame and the semiconductor device. The lead frame is therefore securely held to the semiconductor device. Wires can then be bonded to contact pads on the semiconductor device and to the lead frame.

Abstract: The central region of a leadframe (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201), is selectively etched to leave upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204). Subsequently, during the packaging process, an integrated circuit (3) is located on the central region of the leadframe, and wires (107) are formed between the upright portions of the leadframe and contacts (5) of the integrated circuit (3), which are to be grounded. Subsequently, the wires and upright portions of the leadframe are encased in resin (116). Since the upright portions of the leadframe are encased in resin, the resin (116) is mechanically locked to the leadframe. Furthermore, any delamination that occurs between the resin (116) and the leadframe cannot propagate easily up the sides of the upright portions as far as the wires (107), so the wires (107) are unlikely to be torn from the upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204).

Abstract: A process for fabricating a leadless plastic chip carrier includes providing a leadframe including a plurality of contacts circumscribing a void; fixing a heat sink to the contacts of the leadframe using an intermediate non-electrically conductive adhesive such that the heat sink spans the void; mounting a semiconductor die to the heat sink in the void; wire bonding ones of the contacts to the pads of the semiconductor die; encapsulating the semiconductor die and the wire bonds in a molding material and singulating the leadless plastic chip carrier.

Abstract: This invention is directed to preventing deformation, breakage, and the like of leads in a semiconductor device, reducing the fraction of defects, and making the semiconductor device smaller and thinner. In order to accomplish these objects, in a carrier including a base having a device hole and a plurality of leads for bonding a chip, the leads are provided with thin heat-resistant films.

Abstract: A non-leaded resin-sealed semiconductor device is manufactured by the steps of providing a metal substrate having a front surface, a rear surface, a chip fixing partition part, partition parts arranged around the chip fixing partition part, and grooves defined between the partition parts; providing a semiconductor chip having a front surface, a rear surface, electrodes formed on the front surface; fixing the semiconductor chip on the chip fixing partition part of the front surface of the metal substrate; electrically connecting the electrodes of the semiconductor chip with the front surface of the partition parts of the metal substrate by conductive wires, respectively; and forming a resin body which seals the semiconductor chip, the conductive wires, and the front surface of the partition parts of the metal substrate.

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved.

Abstract: Carrier structure embedded with semiconductor chips and method for manufacturing the same are disclosed. The carrier structure comprises a metal plate and pluralities of semiconductor chips. An adhesive material is disposed on both surfaces of the metal plate, and pluralities of cavities are formed through the metal plate. The semiconductor chips are embedded in the cavities and mounted in the metal plate. The semiconductor chips each have an active surface on which pluralities of electrode pads are disposed. A built-up structure is formed on the surface of the carrier structure and the active surfaces of the semiconductor chips, which has pluralities of conductive vias therein to conduct the semiconductor chips, and has pads thereon. Besides, the metal plate has an etching cavity between the semiconductor chips, and the etching cavity is filled with the adhesive material. The present invention solves the problem of metal burrs being formed when cutting.

Abstract: An integrated circuit package lead frame, comprising a plurality of leads and a spine electrically connected to said plurality of leads, said spine comprising indentations between a pair of said leads. The indentations prevent the pair of leads from becoming electrically connected to each other after a singulation process.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A method for making a semiconductor die package is disclosed. In some embodiments, the method includes using a leadframe structure including at least one lead structure having a lead surface. A semiconductor die having a first surface and a second surface is attached to the leadframe structure. The first surface of the semiconductor die is substantially planar to the lead surface and the second surface of the semiconductor die is coupled to the leadframe structure. A layer of conductive material is formed on the lead surface and the first surface of the semiconductor die to electrically couple the at least one lead structure to the semiconductor die.

Abstract: A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured by an active surface thereof to the die paddle, a second semiconductor die secured by a backside thereof to the die paddle, wire bonds extending from the first semiconductor die and the second semiconductor die to lead fingers of the plurality, and an encapsulant extending over the first semiconductor die, the second semiconductor die, the die paddle, the wire bonds and portions of the lead fingers. A method of fabricating the semiconductor die assembly and an electronic system incorporating the semiconductor die assembly are also disclosed.

Abstract: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract: In some example embodiments, an integrated circuit, electronic assembly and method provide a current path for supplying power to a processor. As an example, the integrated circuit includes a base having power contacts that extend from an upper surface of base. The integrated circuit further includes a substrate that is mounted to the upper surface of the base to electrically couple the substrate to the base. A die is mounted on a substrate such that the die is electrically coupled to the substrate. The power contacts on the upper surface of the base engage a daughterboard so that the die is able to receive power from a voltage source mounted on the daughterboard through the power contacts on the upper surface of the base.

Abstract: The present invention provides a semiconductor device tape carrier formed of an insulative tape 1 of a thin film, which becomes a semiconductor device by conducting a plurality of wire patterns 11 on its surface to a bump 23 of a semiconductor element 21 and being sealed by an insulative resin 22, wherein: an outer dimension of the semiconductor device in a carriage direction of the insulative tape 1 is greater than an integral multiple X (X=1, 2, 3, 4, 5, . . . ) of a pitch interval of sprocket holes 2, which are openings formed to carry the insulative tape 1, and not more than: the integral multiple X+a decimal Y (0?Y?1), and the tape pitch for a single semiconductor device is set to the integral multiple X+a decimal Y (0?Y?1).

Abstract: Provided is a method for fabricating a semiconductor package with a lead frame and the semiconductor package provided thereof. The method includes supplying a lead frame with a plurality of molding regions for molding a plurality of semiconductor packages, and attaching tape to at least one surface of the lead frame to prevent a molten molding material from contacting the lead frame on that surface. The tape comprises a plurality of vacant regions corresponding to the boundary of each molding region. This method distributes the tension and expansion stress of the tape caused by a heating roller when laminating the tape on the lead frame, thereby preventing bending of the strip.

Abstract: A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.

Abstract: A partly finished product of a semiconductor device includes a resin body encapsulating a semiconductor chip, first and second leads extended outwardly from the resin body, a dam bar connected between said first and second leads, and an excess resin portion protruding from the resin body between the first and second leads and the dam bar. The excess resin portion is cut off at two limited portions, and thereby two groove portions are formed in the excess resin portion. An apparatus for cutting the dam bar includes a punch having a cutting edge for cutting connection portions between the first and second leads and the dam bar and for cutting off the two limited portions of the excess resin portion. Since the cut region of the excess resin portion becomes smaller, a stress imparted to the resin body and/or the semiconductor chip through the excess resin portion can be smaller.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof, in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; punching through from a surface side having the terminals in the wiring substrate, thereby cutting the terminals along a boundary between the first region and the second region; and punching through from the surface side having the reinforcing member in the wiring substrate, thereby continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A method of making a semiconductor device including a semiconductor chip having a plurality of pads, and a lead frame having a plurality of leads. Each of the plurality of leads has a mounting surface for mounting the semiconductor device, a wire connection surface having a thick portion, and a thin portion whose thickness is thinner than the thick portion. The length of each wire connection surface was furthermore formed shorter than the mounting surface, by arranging so that the thin portion of each lead dives below the semiconductor chip, securing the length of the mounting surface of each lead, a distance from the side face of the semiconductor chip to the side face of a molded body of the semiconductor device being shortened as much as possible, and the package size is brought close to chip size, with miniaturization of QFN.

Abstract: A semiconductor module includes a power semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side a large-area contact, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the large-area contacts. The electrode of the passive component is electrically connected with one of the large-area contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the power semiconductor chip or an electrode of a further semiconductor chip.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; cutting the terminals along a boundary between the first region and the second region; and continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A method of making a packaged electrical device comprises the steps of (a) connecting one end of a wire to a first point (e.g., a first electrical node) in the package, and (b) connecting the other end of the wire to a second point (e.g., a second electrical node) in the package, characterized by (c) causing energy from an external source to heat at least one predetermined segment of the wire to a temperature that is below its melting point (MP) but not below its recrystallization temperature (RCT), and (d) cooling the heated segment to a temperature below its RCT [e.g., to room temperature (RT)], thereby to increase the stiffness modulus of the segment. In one embodiment, the external source is a laser whose optical output is absorbed by the segment. In another embodiment, the heated segment is rapidly cooled (i.e., quenched) to RT.

Abstract: A leadframe strip production process provides encapsulated semiconductor chips with more than two annular rows of exposed leads by utilizing two types of frames, a leadframe to which IC devices are mounted, and a ring frame strip that is attached to the leadframe with a non-conductive adhesive. The leadframe includes die pads that receive the IC chip devices, and each die pad is positioned within multiple rows of connecting pads for connection with bonding pads of the device to be encapsulated. The connecting pads of the leadframe are arranged in an annular fashion, with inner rows being closer to the die pad and outer rows being farther from the die pad.

Abstract: A wiring pattern is provided on an insulating tape. Part of the wiring pattern is a connection section. An insulating resin is provided so that the connection section is coated with the insulating resin. A protrusion electrode of a semiconductor element is so positioned on the connection section so that the protrusion electrode will push away the insulating resin and be connected with the connection section. Then, the semiconductor is pressed in Direction D1. Heat is applied while pressing in Direction D1. In this way, the connection section intrudes into the protrusion electrode, thereby causing the connection section and the protrusion electrode to be connected with each other.

Abstract: A method for fabricating a semiconductor device including forming a depression in a front surface of a semiconductor substrate, forming an electrode pad within the depression, forming structures including circuit devices and metal wires on the front surface of the semiconductor substrate, and exposing the electrode pad by removing a rear surface of the semiconductor substrate.

Abstract: A lead frame of the present invention includes a plurality of tie bars including tie bars each having deformable portions that protect opposite outside frames from deformation. The outside frames each are formed with positioning holes. Element loading portions to be loaded with semiconductor elements are connected to the outside frames by such tie bars. The lead frame is therefore free from deformation during lead forming while promoting the miniaturization of the semiconductor devices.

Abstract: Arrangements and methods of packaging integrated circuits in leadless leadframe packages configured for maximizing a die size are disclosed. The package is described having an exposed die attach pad and a plurality of exposed contacts formed from a common substrate material. The contacts, however, are thinned relative to the die attach pad. In one embodiment, an inner region of the contacts is thinned. In another embodiment, an outer region of the contacts is also thinned. A die is mounted on the die attach pad and wire bonded to the contacts. Since the inner region and sometimes together with the outer region of the contact are lower than the die attach pad being wire bonded to, the size of the die can be relatively increased to overhang over the contact, thereby maximizing the die size in the package. A plastic cap is molded over the die, contacts, and bonding wires while leaving the bottom surface of the contacts exposed.

Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip so as to create unique design features such as power and/or ground ring surrounding the die attach pad, interlocking rivet head construction for the contact pads, and an interlocking pattern for the die attach pad. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip is then performed by saw singulation or die punching.

Abstract: The principles described herein relate to methods for soldering electrode terminals, pins or lead-frames of commercial electric components for high temperature reliability. In one embodiment, prior to soldering the electric components, a pre-plated solder layer is removed from the lead frame or pins, and nickel and/or gold films are formed with electroless plating. The removal of the pre-plated solder layer avoids excess pre-plated Sn with high-Pb solder that lowers the melting point to between 180° C. and 220° C. and weakens solder joints. The nickel layer formed with an electroless plating acts as a barrier to the interdiffusion of tin from solder with copper of the lead frame material, which may otherwise occur at high temperatures. Interdiffusion forms an intermetallic compound layer of copper and tin and degrades solder joint strength. The novel soldering processes improve high temperature reliability of solder joints and extend electronics life-time.

Abstract: In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the die-pad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30-50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.

Abstract: A process for fabricating an integrated circuit package. At least a first side of a leadframe strip is selectively etched to define portions of a die attach pad and at least one row of contacts adjacent the die attach pad. A carrier strip is laminated to the first side of the leadframe strip and a second side of the leadframe strip is selectively etched to thereby define a remainder of the die attach pad and the at least one row of contacts. A semiconductor die is mounted to the die attach pad, on the second side of the leadframe strip and the semiconductor die is wire bonded to ones of the contacts. The second side of the leadframe strip is encapsulating, including the semiconductor die and wire bonds, in a molding material. The carrier strip is removed from the leadframe strip and the integrated circuit package is singulated from a remainder of the leadframe strip.

Abstract: A semiconductor device X1 comprises: a first conductor 110 including a first terminal surface 113a; a second conductor 120 placed by the first conductor 110 and including a second terminal surface 123a facing a same direction as does the first terminal surface 113a; a third conductor 130 connected with the first conductor 110; a semiconductor chip 140 including a first surface 141 and a second surface 142 away from the first surface, and bonded to the first conductor 110 and to the second conductor 120 via the second surface 142; and a resin package 150. The first surface 141 of the semiconductor chip 140 is provided with a first electrode electrically connected with the first conductor 110 via the third conductor 130. The second surface 142 is provided with a second electrode electrically connected directly with the second conductor 120.

Abstract: An electrode that includes an electrically conductive, substantially planar body having a first thickness and a junction area, wherein the junction area is configured to receive a solid state power cell having a second thickness. The electrode also includes an arcuate terminal electrically coupled to the body and configured to position a wire bond terminus at a perpendicular distance from the body, the distance being not substantially less than the sum of the first and second thicknesses.

Abstract: A process for fabricating a leadless plastic chip carrier includes laminating a first metal strip to a second metal strip to form a leadframe strip, selectively etching the first metal strip to define at least a row of contact pads, mounting a semiconductor die to either a die attach pad or the second metal strip and wire bonding the semiconductor die to ones of the contact pads, encapsulating a top surface of the leadframe strip in a molding material, removing the second metal strip, thereby exposing the die attach pad and the at least one row of contact pads, and singulating the leadless plastic chip carrier from the leadframe strip.

Abstract: A method of encapsulating a plurality of IC chips attached to a lead frame strip that includes an outer frame and a plurality of vertical and horizontal connecting bars attached to the outer frame in a manner that defines a plurality of inner frames arranged in a matrix pattern within the outer frame, each inner frame including an area where an IC chip from the plurality of IC chips is attached.

Abstract: A method for fabricating leadless packages with mold locking characteristics is disclosed. A provided leadless leadframe has a plurality of units in a matrix, each unit includes an improved die pad with a plurality of indentations, such as semi-vias in the sidewall thereof and a plurality of leads around the die pad. After chip attachment and electrical connection, a plurality of package bodies for semiconductor packages are individually formed on the corresponding units and covered the indentations in order to enhance the horizontal mold locking capability of the die pad. Using punching, connecting bars of the leadless leadframe are removed to isolate the leadless packages.

Abstract: A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact and a plurality of source contacts, patterning a lead frame with target dimple areas, creating dimples in the lead frame corresponding to the gate contact and source contacts, printing a conductive epoxy on the lead frame in the dimples, curing the lead frame and semiconductor die wafer together, and dicing the wafer to form the semiconductor device packages.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (11) in which an IC is formed and which has a number of connection regions (1) for the IC on its surface, including at least two connection regions (1A) for a supply connection, the lower side of the semiconductor body (11) being provided with a number of further connection regions (2) which are connected to a connection region (1) by means of an electric connection (3) which is present on a side face of the semiconductor body (11) and electrically insulated therefrom, and the semiconductor body (11) being attached to a lead frame (4) and wire connections (5) being formed between leads (4A) of the frame (4) and connection regions (1) .

Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.

Abstract: A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.

Abstract: A method of fabricating a micro-array IC package is recited. A wafer has a B-stageable adhesive applied, and the wafer is diced. The individual dice are applied to a lead-frame via their adhesive, and wirebonded to associated leads. The lead-frame is then encapsulated, and solder connectors are applied. The lead-frame is then singulated to produce a plurality of lead-frame based micro-array packages. The process thus allows lead-frame based manufacturing methods to be employed in the production of BGA-type packages, allowing such packages to be produced faster and more efficiently.

Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.

Abstract: A method of fabricating a semiconductor device comprising: a step (a) of attaching a plurality of semiconductor chips to a tape; a step (b) of cutting the tape; and a step (c) of providing a plurality of external terminals on an insulating film cut from the tape, wherein the steps (a) and (b) are carried out in a reel-to-reel transport system.