Abstract: A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured.

Abstract: The general field of the invention is that of display systems comprising an image projector and an associated display screen, the said display system being designed to be used by an observer situated at a given location, the said display screen comprising two transparent and substantially parallel faces, the said display screen comprising, on at least one of its transparent faces, a plurality of regularly distributed light-scattering patterns. The image projector according to the invention illuminating the screen under a plurality of angles of incidence determined by the position and the size of the display screen, the said angles of incidence being centered on a mean angle of incidence, the scattering patterns comprise a diffractive structure in order to diffract the light rays having at least the mean angle of incidence in one or more directions corresponding to the said given location of the observer.

Abstract: Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described.

Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure.

Abstract: A method for producing an image pickup apparatus includes: a process of fabricating a plurality of image pickup chips by cutting an image pickup chip substrate where light receiving sections and electrode pads are formed; a process of fabricating a joined wafer by bonding the image pickup chips to a glass wafer; a process of filling a gap between the plurality of image pickup chips with a sealing member; a process of machining the joined wafer to reduce a thickness; a process of forming through-hole vias; a process of forming an insulating layer that covers the image pickup chips; a process of forming through-hole interconnections; a process of forming external connection electrodes, each of which is connected to each of the through-hole interconnections; and a process of cutting the joined wafer.

Abstract: One embodiment relates to a method of detecting a buried defect in a target microscopic metal feature. An imaging apparatus is configured to impinge charged particles with a landing energy such that the charged particles, on average, reach a depth within the target microscopic metal feature. In addition, the imaging apparatus is configured to filter out secondary electrons and detect backscattered electrons. The imaging apparatus is then operated to collect the backscattered electrons emitted from the target microscopic metal feature due to impingement of the charged particles. A backscattered electron (BSE) image of the target microscopic metal feature is compared with the BSE image of a reference microscopic metal feature to detect and classify the buried defect. Other embodiments, aspects and features are also disclosed.

Abstract: A method and a system for detecting defects of a transparent substrate are provided.

Abstract: A method for predicting a reliable lifetime of a SOI MOSFET device including: measuring a relationship of a gate resistance of the device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the device under a bias.

Abstract: A method for classifying defect images is provided. Defect images are processed through an automatic optical detection. The present invention integrates image analysis and data mining. Defects are found on the images without using human eye. The defects are classified for reducing product defect rate. Thus, the present invention effectively enhances performance on finding and classifying defects with increased consistency, correctness and reliability.

Abstract: In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer.

Abstract: The present disclosure provides methods and systems for providing a similarity index in semiconductor process control. One of the methods disclosed herein is a method for semiconductor fabrication process control. The method includes steps of receiving a first semiconductor device wafer and receiving a second semiconductor device wafer. The method also includes a step of collecting metrology data from the first and second semiconductor device wafers. The metrology data includes a first set of vectors associated with the first semiconductor device wafer and a second set of vectors associated with the second semiconductor device wafer. The method includes determining a similarity index based in part on a similarity index value between a first vector from the first set of vectors and a second vector from the second set of vectors and continuing to process additional wafers under current parameters when the similarity index is above a threshold value.

Abstract: An interface board of a testing head for a test equipment of electronic devices is described. The testing head includes a plurality of contact probes, each contact probe having at least one contact tip suitable to abut against contact pads of a device to be tested, as well as a contact element for the connection with a board of the test equipment. Suitably, the interface board comprises a substrate and at least one redirecting die housed on a first surface of that substrate and a plurality of contact pins projecting from a second surface of that substrate opposed to the first surface. The redirecting die includes at least one semiconductor substrate whereon at least a first plurality of contact pads is realized, suitable to contact a contact element of a contact probe of the testing head, the contact pins being suitable to contact the board.

Abstract: In vapor deposition applications, especially OLED mass production, where it is necessary to measure and/or control the deposition rate of evaporation sources within specific tolerances, a measurement system is adapted to use robust and accurate optical thickness measurement methods at high and low rate sources, so that the thickness of a layer deposited on a substrate can be measured and controlled. A first evaporation source (11) deposits a layer of material on a substrate (20). A mobile element (41) is provided, On which a film is deposited from a second evaporation source (12b) in a deposition location (D1). Subsequently the mobile element is conveyed to a measurement location (D2) where the thickness of the film is measured by a thickness detector (45). The measurement apparatus is arranged to control the deposition of the first evaporation source in dependence on the thickness of the film deposited on the mobile element.

Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.

Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

Abstract: A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.

Abstract: Methods for characterizing relative film density using spectroscopic analysis at the device level are provided. One such method includes obtaining a composition of materials at preselected areas of a workpiece using energy dispersive X-ray spectroscopy, obtaining an electron energy loss spectrum-imaging data at each of the preselected areas using electron energy loss spectroscopy, removing, for each of the preselected areas, a preselected noise component of the electron energy spectrum-imaging data to form a plasmon energy spectrum-imaging data, generating, for each of the preselected areas, a plasmon energy map based on the respective plasmon energy spectrum-imaging data, determining, for each of the preselected areas, an average plasmon energy value from the respective plasmon energy map, and calculating a relative mass density of the preselected areas based on the average plasmon energy value, a number of valence electrons per molecule, and a molecular weight for each of the preselected areas.

Abstract: A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits.

Abstract: A method and apparatus are provided for improving the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention is particularly useful for step-and-scan system and the CD of two features in each exposure field are measured in fields exposed at varying focus to form at least two Bossung curves. Exposure focus instructions are calculated based on the intersection point of the curves and the wafer is then scanned and imaged based on the calculated exposure focus instructions. In another aspect of the invention, when multiple wafers are being processed operational variances may cause a drift in the focus. The focus drift can be easily corrected by measuring the critical dimension of each of the features and comparing the difference to determine if any focus offset is needed to return the focus to the original calculated focus value.

Abstract: A laminated structure which can reduce defect by preventing deposition failure or holes of an insulating film, manufacturing method, and a display unit that employ same are provided. The laminated structure as an anode for organic light-emitting devices is provided on a flat surface of a substrate. In the laminated structure, an adhesive layer made of ITO, a reflective layer made of silver or an alloy containing silver, and a barrier layer made of ITO are layered in this order from the substrate side. A cross sectional shape of the laminated structure in the laminated direction is a forward tapered shape. A sidewall face of the adhesive layer, the reflective layer, and the barrier layer is totally covered by an insulating film, and deposition failure or holes of the insulating film is prevented. A taper angle made by the sidewall face and the flat surface is preferably from about 10° to about 70°.

Abstract: In a disclosed embodiment, a method for tiling selected vias in a semiconductor device having a plurality of vias comprises generating a layout database for the semiconductor device; creating zones around the plurality of vias; measuring density of covering metal in each zone; selecting a low density zone as being a zone that has a metal density less than a threshold metal density; and adding at least one tiling feature on a metal layer above the plurality of vias in the low density zone so that metal density of the low density zone increases to at least the same as the threshold metal density.

Abstract: Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold.

Abstract: A method of manufacturing an organic light-emitting display device is provided. An alignment master member is loaded on a moving unit. An organic layer deposition assembly is pre-aligned to the alignment master member. After the pre-aligning of the organic layer deposition assembly, a substrate is loaded on the moving unit. The organic layer deposition assembly is aligned to the substrate positioned as is after the loading of the substrate. An organic layer is formed on the substrate while the moving unit is moving along the moving direction. While the moving unit is moving along the moving direction, the organic layer deposition assembly is adjusted so that an interval between the organic layer deposition assembly and part of the substrate is maintained as substantially constant. The part of the substrate receives a deposition material emitted from the organic layer deposition assembly to form the organic layer.

Abstract: Described herein are methods and systems for providing corrective maintenance using global knowledge sharing. A method to provide corrective maintenance with a CM system includes performing a query to generate a ranking of fixable causes based on factors (e.g., symptoms, configuration, test). The ranking may be determined based on a fixable cause percent match with the factors. The ranking of fixable causes may be associated with one or more solutions for each fixable cause. The ranking can be updated based on performing tests or solutions.

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.

Abstract: A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark disposed on a substrate; and obtaining a compensation parameter by performing asymmetry compensation calculation on at least one of a first directional component of the misalignment data, which is associated with a first direction, and a second directional component of the misalignment data, which is associated with a second direction.

Abstract: A gas supply device for intermittently supplying raw material gas into a film forming process unit that includes a raw material container for accommodating a raw material, a carrier gas supply unit for supplying carrier gas to evaporate the raw material, a raw material gas supply path for supplying the raw material gas and the carrier gas into the film forming process unit, a flow rate detector, a flow rate regulating valve, a raw material supply and block unit for supplying and blocking the raw material gas into the film forming process unit, and a control unit for outputting a control signal for intermittently supplying the raw material gas into the film forming process unit.

Abstract: The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.

Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which the film for flip chip type semiconductor back surface contains a black pigment.

Abstract: A method for detecting an endpoint during removal of material from an electronic device includes while removing material from an electronic device-under-test (DUT) using a tip driven by a spindle, applying an input signal to the DUT via the tip and using an output signal received from one of the DUT and a mounting plate to which the DUT is attached to determine an endpoint for removal of material.

Abstract: Some embodiments provide methods, process, systems and apparatus for use in testing multi-axis Micro Electro Mechanical Systems (MEMS) devices. In some embodiments, methods of testing are provided, comprising: selecting, according to a test specification and a test program, at least a first MEMS device on a substrate comprising a plurality of MEMS formed relative to the substrate and applying one or more electrical probes to the first MEMS device; providing power to the first MEMS device through the one or more electrical probes; measuring output signals of the first MEMS device; applying a force to the first MEMS device using a force actuator; measuring a set of output signals of the first MEMS device based on the applied force; and processing test data and generating output test results according to the test specification and test program.

Abstract: A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Abstract: Production of a silicon wafer coated with a passivation layer. The coated silicon wafer may be suitable for use in photovoltaic cells which convert energy from light impinging on the front face of the cell into electrical energy.

Abstract: Methods for forming a semiconductor layer, such as a metal1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Abstract: The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units.

Abstract: An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.

Abstract: An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiOX (X>2)) is used for a base insulating layer of a top-gate structure or for a protective insulating layer of a bottom-gate structure. By using the oxygen-excess silicon oxide, oxygen is discharged from the insulating layer, and oxygen deficiency of an oxide semiconductor layer and the interface state density between the oxide semiconductor layer and the base insulating layer or the protective insulating layer can be reduced, so that the highly-reliable semiconductor device in which change of electrical characteristics is small can be manufactured.

Abstract: First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C.

Abstract: A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Abstract: A polishing apparatus capable of monitoring an accurate progress of polishing is disclosed. The polishing apparatus includes: a polishing table for supporting a polishing pad; a table motor configured to rotate the polishing table; a top ring configured to press a substrate against the polishing pad to polish the substrate; a dresser configured to dress the polishing pad while oscillating on the polishing pad during polishing of the substrate; a filtering device configured to remove a vibration component, having a frequency corresponding to an oscillation period of the dresser, from an output current signal of the table motor; and a polishing monitoring device configured to monitor a progress of polishing of the substrate based on the output current signal from which the vibration component has been removed.

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract: A plasma processing apparatus and a temperature measuring method that may measure a temperature of an object in a processing chamber by a low-coherence interferometer without forming a hole in a holding stage or an upper electrode of the plasma processing apparatus, thereby performing a plasma process of a substrate with high precision and uniformity. The plasma processing apparatus is implemented by disposing a light source collimator outside of a light source window, disposing a light-receiving collimator outside of a light-receiving window, allowing a measurement light emitted from the light source collimator to pass through the light source window to be obliquely emitted to a surface of the object to be measured, and allowing the reflected measurement light to pass through the light-receiving window to be incident on the light-receiving collimator. The temperature of the object in the processing chamber may be measured by the low-coherence interferometer.

Abstract: An apparatus and method of manufacturing a light emitting diode (LED) device, and more particularly, an apparatus and method of manufacturing an LED device by dispensing a fluorescent solution prepared by mixing a fluorescent material with a liquid synthetic resin, onto an LED chip. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution simultaneously in consideration of several factors, such as characteristics of an LED chip and viscosity of the fluorescent solution may be dispensed onto the LED chip, is provided. An apparatus and method of manufacturing an LED device, whereby an appropriate amount of fluorescent solution may be calculated actively in consideration of viscosity of the fluorescent solution, a change in characteristics of an LED chip, or the like, and the appropriate amount of fluorescent solution may be dispensed onto the LED chip, is provided.

Abstract: A layer is deposited onto a semiconductor wafer by CVD in a process chamber having upper and lower covers, wherein the wafer front side temperature is measured; the wafer is heated to deposition temperature; the temperature of the upper process chamber cover is controlled to a target temperature by measuring the temperature of the center of the outer surface of the upper cover as the value of a controlled variable of an upper cover temperature control loop; a gas flow rate of process gas for depositing the layer is set; and a layer is deposited on the heated wafer front side during control of the upper cover temperature to the target temperature. A process chamber suitable therefor has a sensor for measuring the upper cover outer surface center temperature and a controller for controlling this temperature to a predetermined value.

Abstract: An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps.

Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

Abstract: A metal-to-metal leakage and breakdown testing structure for semiconductor structures and method of using the testing structure is disclosed. The testing structure includes plurality of resistor bridges connected to respective two terminal devices. The testing structure further includes a plurality of switches each having a voltage node provided between resistors of a respective one of the plurality of resistor bridges. The voltage node is read at a circuit pad when a respective one of the plurality of switches is in an on state. The testing structure further includes a device turning on and off each of the plurality of switches, individually.