Abstract: A semiconductor device and method for fabricating the same which improves reliability of the semiconductor device is disclosed. The semiconductor device includes: a first insulating film and a gate electrode sequentially formed on a part of a semiconductor substrate; a first insulating spacer formed at both sides above the gate electrode; a second insulating spacer formed at both sides below the gate electrode; and a cobalt silicide film formed on a surface of the gate electrode at a predetermined depth.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to annealing of the implants for dopant diffusion/activation and lattice damage relaxation. Lightly- or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: A method of fabricating a semiconductor device having a gate structure comprising SiO2 and Si3N4 that exhibits reduced hydrogen diffusion during low temperature chemical vapor deposition of silicon nitride. In the method, a silicon dioxide (SiO2) layer is deposited on a wafer after a gate structure is fabricated. A barrier layer is formed on the silicon dioxide (SiO2) layer. Then a silicon nitride layer is formed over it by low temperature chemical vapor deposition. The barrier layer reduces, and may even altogether prevent, diffusion of the hydrogen absorbed by the silicon nitride layer into the gate oxide and channel during the low temperature chemical vapor deposition of silicon nitride.

Abstract: A semiconductor process is provided that creates fully-salicided transistors. in a first region and partially-salicided transistors in a second region. Each of the fully-salicided transistors includes a salicided gate electrode and salicided active regions. Each of the partially-salicided transistors includes a salicided gate electrode and active regions that are free from salicide. A silicide blocking layer prevents the formation of salicide in the active regions of the partially-salicided transistors. The silicide blocking layer is deposited over the first and second regions, and then removed over the first region. The remaining portion of the silicide blocking layer over the second region is then etched back until the upper surfaces of the gate electrodes in the second region are exposed. The remaining portions of the silicide blocking layer covers the active regions in the second region. A refractory metal is then deposited over the resulting structure and reacted.

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon and germanium material. The polysilicon and polysilicon and germanium materials are manufactured by utilizing amorphous semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Abstract: The present invention provides a method and apparatus for providing a polysilicon type-1 ESD transistor in a flash memory chip. The method and apparatus include providing a select gate transistor that includes a gate, a floating gate, a medium doped junction, and a source and drain. The method and apparatus further include forming the source and drain by performing a lightly doped drain (LDD) mask and etch, performing a LDD spacer deposition and LDD spacer etch, and performing a N+ implant mask and a N+ implant.

Abstract: A fabrication method for a metal oxide semiconductor transistor is described. A source/drain implantation is conducted on a substrate beside the spacer that is on the sidewall of the gate to form a source/drain region in the substrate beside the spacer. A self-aligned silicide layer is further formed on the gate and the source/drain region. A portion of the spacer is removed to form a triangular spacer with a sharp corner, followed by performing a tilt angle implantation on the substrate to form a source/drain extension region in the substrate under the side of the gate and the spacer with the sharp corner. A thermal cycle is further conducted to adjust the junction depth and the dopant profile of the source/drain extension region.

Abstract: In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers.

Abstract: The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectric layer, forming a nitrided surface layer on the polysilicon layer; selectively removing portions of the nitrided surface layer and the polysilicon layer stopping on the gate dielectric layer, while leaving a patterned stack of the nitrided surface layer and the polysilicon layer on the gate dielectric layer; forming sidewall spacers on at least exposed vertical sidewalls of polysilicon layer; removing portions of the gate dielectric layer not protected by the sidewall spacers; and growing an epi silicon layer on exposed horizontal surfaces of an underlying semiconductor substrate.

Abstract: A semiconductor device having a multi-layered spacer and a method of manufacturing the semiconductor device include gate electrodes each comprising a gate oxide layer, a gate conductive layer, and a capping dielectric layer formed on a semiconductor substrate, a gate polyoxide layer formed on sidewalls of the gate conductive layer and the gate oxide layer and being in contact with a predetermined portion of the semiconductor substrate, a silicon nitride layer being in contact with sidewalls of the capping dielectric layer and the gate polyoxide layer, an oxide layer being in contact with the silicon nitride layer, and an external spacer being in contact with the oxide layer.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A method of fabricating a SOI semiconductor device with an implanted ground plane in the silicon substrate to increase the doping concentration underneath the channel region for suppressing short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL). For a N-channel MOSFET, the implanted ground plane is P+ type such that if a P-type underlying substrate is used, the ground plane is automatically connected to ground potential (the substrate potential). For a SOI-type CMOS semiconductor device with two spaced-apart implanted ground planes each self-aligned to be underneath a corresponding channel region of the CMOS, two SOI-type MOSFET semiconductor devices of opposite conductivity types are formed on a same semiconductor substrate.

Abstract: A boron difluoride plasma doping method to form an ultra-shallow junction. A semiconductor substrate is put inside a reaction chamber and then a boron difluoride ions (BF2+) containing plasma is generated inside the chamber. A negative voltage is applied to the semiconductor substrate so that the boron difloride ions (BF2+) accelerate and bombard against the semiconductor substrate to form an ultra-shallow junction on a superficial layer of the substrate. A rapid annealing operation is conducted to repair any defects in the crystal lattice that results from the formation of the ultra-shallow junction.

Abstract: A method of fabricating a CMOS transistor to construct shallow drain extenders (30) using a replacement gate design. The method involves forming epitaxial layers (30) and (220) the will later function as shallow drain extensions. The etching of the replacement gate (220) and the formation of inner sidewalls (90) serve to define the transistor gate length.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: A method of forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed structures; providing insulating regions in selected portions of the structure; forming a second layer of a second reactive material over the insulating regions and the first layer of first reactive material; reacting the first and second reactive materials to form silicide layers; removing any un-reacted reactive material; forming structures that are located on the silicide layers; and metallizing the device.

Abstract: In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate. Among many other advantages, such method provides a means of accurately controlling the cell channel length.

Abstract: A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.

Abstract: A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of said transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic.

Abstract: The present invention provides a semiconductor diffusion region structure of a first conductivity type in an upper region of a semiconductor substrate of a second conductivity type, wherein the semiconductor diffusion region structure comprises: a main portion, at least a part of which is electrically connected to an electrically conductive film structure; and an extending portion which underlies a gate insulating film underlying a gate electrode layer which is also electrically connected to the electrically conductive film structure, so that an adjacent potion of the semiconductor substrate to an edge of the extending portion of the semiconductor diffusion region structure is distanced from the electrically conductive film structure whereby the semiconductor diffusion region structure is electrically isolated from the semiconductor substrate.

Abstract: A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of the process to produce layers, spacers, memory units, and gates is also disclosed, as well as the structures so produced.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.

Abstract: A major object is to provide an improved semiconductor device capable of preventing occurrence of a crystal defect in a substrate.

Abstract: Self-aligned contacts in integrated circuits can be formed on an integrated circuit substrate having an active region. A groove can be formed in the insulating layer and a conductive material can be formed in the groove to a level that is recessed in the groove. An insulating material can be formed in the groove on the conductive material that has an etch selectivity with respect to the insulating layer. A contact that is self-aligned to the active region can be then be formed.

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). In the case of a P-channel MOSFET, a nitrogen barrier is formed in the P-channel gate prior to p+ doping. Annealing the gate conductor is done in a step separate from the source/drain region annealing step.

Abstract: A semiconductor structure is provided along with a corresponding method of producing such a structure. The method and structure may include providing a semiconductor substrate, a gate insulator over the semiconductor substrate, a conductor comprising intrinsic polysilicon over the gate insulator, a silicide layer over the polysilicon and an insulating cap over the silicide layer. Insulating spacers may be provided along sides of the silicide layer and the insulating cap. The polysilicon may be doped with a first conductive type dopant. The first conductive type dopant may be spread over the polysilicon to form a doped polysilicon layer. A gate sidewall layer may be formed on sides of the doped polysilicon layer. A bird's beak of the gate sidewall layer may also be formed in a corner of the polysilicon.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: An enlarged contact area (62, 162) is formed for a gate structure (14, 114) by providing a substrate (12, 112) having at least one gate electrode (22, 122) thereon. An implant sidewall (42, 142) is formed outwardly from the gate electrode (22, 122) and defines an implant area (44, 144) in the substrate (12, 112). A terminal (50, 150) is formed for the gate electrode (22, 122) by implanting dopants (46, 146) into the implant area (44, 144) in the substrate (12, 112). The implant sidewall (42, 142) is removed and an insulative sidewall (60, 160) is formed outwardly from the gate electrode (22, 122). The insulative sidewall (60, 160) has a thickness less than that of the implant sidewall (42, 142) to define an enlarged contact area (62, 162) for the terminal (50, 150).

Abstract: A transistor 10 is formed on an outer surface of a substrate 12. The transistor comprises a floating gate 18 and a control gate 20. An outer encapsulation layer 22 and sidewalk bodies 26 and 28 comprise silicon nitride that is deposited in such a manner such that the material is transmissive to ultraviolet radiation. In this manner, the sidewalk bodies 26 and 28 and the layer 22 can be used as an etch stop during the formation of a drain contact 38. These layers will also permit the transmission of ultraviolet radiation to the floating gate 18 to enable the erasure of floating gate 18.

Abstract: A method of fabricating a MOS transistor having SEG Si. After the formation of a gate and a spacer and before a source/drain region is formed, a selective epitaxial growth (SEG) Si is deposited over the substrate. The spacer is then removed to form an ultra shallow junction in the exposed substrate covered by the spacer after the formation of the SEG Si.

Abstract: A method is described for forming gate sidewall spacers having different widths. The variation in spacer width allows for optimization of the MOSFET characteristics by changing the dimensions of the lightly doped source/drain extensions. The process is achieved using a method where the gate structure, comprising the gate electrode and gate oxide, is formed by conventional techniques upon a substrate. Lightly doped source drain extensions are implanted into the substrate not protected by the gate structure. The exposed substrate and gate structure are then covered with an insulating liner layer. This is followed by an etch stop layer deposition over the insulating liner layer. A first spacer oxide layer is then deposited over the etch stop layer. Areas where thicker spacers are desired are masked, and the unmasked spacer oxide layer is removed. The mask is then stripped away and additional spacer oxide is grown over the entire surface.

Abstract: A method for adjusting Vt while minimizing parasitic capacitance for low voltage high speed semiconductor devices. The method uses shadow effects and an angled punch through prevention implant between vertical structures to provide a graded implant. The implant angle is greater than or equal to arc tangent of S/H where S is the horizontal distance between, and H is the height of, such vertical structures.

Abstract: A method of forming a metal gate structure, on a high k gate insulator layer, for NMOS devices, and simultaneously forming a metal-polysilicon gate structure, on the same high k gate insulator layer, for PMOS devices, has been developed. The method features forming openings in a composite insulator layer, via removal of silicon nitride dummy gate structures that were embedded in a composite insulator layer, with the openings exposing regions of the semiconductor substrate to be used for subsequent NMOS and PMOS channel regions. Deposition of a high k gate insulator layer is followed by deposition of an in situ doped polysilicon layer. After removal of a portion of the in situ doped polysilicon layer located in the NMOS region, a metal layer is deposited on the underlying high k gate insulator layer in the NMOS region, and on the in situ polysilicon layer in the PMOS region.

Abstract: There is disclosed a method of manufacturing a CMOS transistor, by which ion implantation process is selectively performed to the gate formed region of a polysilicon film after a NMOS transistor region and a PMOS transistor region are defined in the process of manufacturing a CMOS transistor. Thus, it can obtain a reliable device by solving the problem occurring when polysilicon films doped with different impurities are simultaneously etched and the problem that a tungsten film is oxidized due to a selective oxidization process after forming a tungsten gate electrode.

Abstract: An improved method of fabricating a MOS transistor on a semiconductor wafer is disclosed. A pre-amorphization implant (PAI) process is used to dope the silicon substrate adjacent to the gate. The dopants formed in the silicon substrate during the first ion implantation process are driven into the substrate to form the HDD via a salicide process. A conventional annealing process is skipped in the present invention, which significantly reduces the thermal budget of the manufacturing process.

Abstract: A process for forming salicided CMOS devices, and non-salicide CMOS devices, on the same semiconductor substrate, using only one silicon nitride layer to provide a component for a composite spacer on the sides of the salicided CMOS devices, and to provide a blocking shape during metal silicide formation, for the non-salicided CMOS devices, has been developed. The process features the use of a disposable organic spacer, on the sides of polysilicon gate structures, used to define the heavily doped source/drain regions, for all CMOS devices. A silicon nitride layer, obtained via LPCVD procedures, at a temperature between 800 to 900° C., is then deposited and patterned to provide the needed spacer, on the sides of the CMOS devices experiencing the salicide process, while the same silicon nitride layer is used to provide the blocking shape needed to prevent metal suicide formation for the non-salicided CMOS devices.

Abstract: A method for forming a self-aligned silicide (or called salicide) structure in IC fabrication is described. This method is characterized by the step of making the top surface of a polysilicon-based structure into a rugged surface, which allows the subsequently formed salicide structure over the rugged surface of the polysilicon-based structure to have an increased surface area and thus have a reduced sheet resistance when compared to the prior art. By this method, the first step is to prepare a semiconductor substrate, after which an oxide layer is formed over the substrate. Next, a polysilicon-based structure is formed over the oxide layer, and then the exposed surface of the polysilicon-based structure is reshaped into a rugged surface. Subsequently, a silicide layer is formed over the rugged surface of the polysilicon-based structure, which serves as the intended salicide structure.

Abstract: A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.

Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

Abstract: A semiconductor substrate having an n-well region, a p-well region and shallow trench isolation (STI) regions is provided. Poly-gates are formed over the n-well region and p-well region respectively. First, nitrogen oxide (such as NO, N2O) layer are formed on surface of the aforesaid structure by furnace or rapid thermal oxidation (RTO). A photoresist layer is formed over the p-well region, and then BF2 or boron ion implantation is carried out to form a nitrogen oxide (such as NO, N2O) layer having boron ion in the n-well region. Another photoresist layer is formed over the n-well region after removing the photoresist layer. Arsenic ion implantation is then carried out to form a nitrogen oxide (such as NO, N2O) layer having arsenic ion in the p-well region. Next, spacer is formed on the sidewall of gates after removing the photoresist layer. Finally, deep source/drain implantation are carried out once again.

Abstract: Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film into a desired shape with a first sidewall and a second and opposite sidewall. A passivating oxide film is formed with a preselected thickness on the first and second sidewalls by oxidizing the silicon structure with a heated aqueous solution of ammonium hydroxide and hydrogen peroxide. Gate electrode formation with an oxide coating film of known thickness is provided. Linewidth metrology accuracy may be improved.

Abstract: A transistor and a transistor fabrication method for forming an LDD structure in which the n-type dopants associated with an n-channel transistor are formed prior to the formation of the p-type dopants is presented. The n-type source/drain and LDD implants generally require higher activation energy (thermal anneal) than the p-type source/drain and LDD implants. The n-type arsenic source/drain implant, which has the lowest diffusivity and requires the highest temperature anneal, is performed first in the LDD process formation. Performing such a high temperature anneal first ensures minimum additional migration of subsequent, more mobile implants. Mobile implants associated with lighter and less dense implant species are prevalent in LDD areas near the channel perimeter. The likelihood of those implants moving into the channel is lessened by tailoring subsequent anneal steps to temperatures less than the source/drain anneal step.

Abstract: A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed.

Abstract: A floating gate electrode 11 has: a conductive side wall 23 located above a tunnel window 13a, a main part electrode 9 located in the vicinity of the tunnel window 13a and above a channel region 10, and a connecting part 25. The connecting part 25 is located between the conductive side wall 23 and the main part electrode 9 to interconnect the conductive side wall 23 and the main part electrode 9. The region that substantially functions as the tunnel window is determined with the width W1 of the conductive side wall 23.