Abstract: A process for economical and efficient fabrication of gate electrodes no larger than 50 nm, which is beyond the limit of exposure, is characterized by gate-electrode trimming and mask trimming with high resist selectivity which are performed in combination. The process is also preferably characterized by performing trimming and drying cleaning in a vacuum environment and may also include steps of inspecting dimensions and contamination in a vacuum environment.

Abstract: A method of manufacturing semiconductor devices. A gate structure is formed over a substrate. A dopant implantation is carried out to form a lightly doped region in the substrate on each side of the gate structure. An insulation layer is formed over the substrate. A portion of the insulation is later removed so that a portion of the insulation layer is retained over the substrate on each side of the gate structure. A spacer is formed on each sidewall of the gate structure. Another ion implantation is carried out such that the dopants penetrate through the insulation layer on the substrate on each side of the gate structure to form a heavily doped region in the substrate.

Abstract: A MOS transistor including a gate poly oxide layer formed to have different thicknesses over the entire surface of a semiconductor substrate and a method for forming the MOS transistor are provided. A gate oxide layer pattern and a gate conductive layer pattern are formed on a semiconductor substrate. A mask layer pattern is formed on the semiconductor substrate and the gate conductive layer pattern so that the gate conductive layer pattern is completely covered with the mask layer pattern. The semiconductor substrate is made to be amorphous using the mask layer pattern. The mask layer pattern is removed and then a gate poly oxide layer is deposited over the entire surface of the semiconductor substrate. A gate spacer layer is deposited on the gate poly oxide layer and gate spacers are formed by anisotropically etching the gate spacer layer and the gate poly oxide layer. A source/drain region is formed on the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device in which an increase in a parasitic resistance can be prevented, resulting in prevention of a deterioration in a current driving capability and a reduction in an operating speed of a semiconductor integrated circuit in consideration of an influence of etching of a semiconductor substrate on an NMOS transistor. By using a gate electrode as an implantation mask, an arsenic or phosphorus ion is implanted into a silicon substrate to form a pair of extension layers in a surface of the silicon substrate. Then, a protective insulating film having a thickness of 1 to 20 nm is formed with a silicon oxide film by a CVD method over the whole surface of the silicon substrate. Thereafter, a boron or BF2 ion is implanted into the silicon substrate from above the protective insulating film by using a gate electrode as an implantation mask. Thus, a pair of extension layers are formed in the surface of the silicon substrate.

Abstract: A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.

Abstract: A semiconductor device fabricated on a silicon-on-insulator substrate and having an active well scheme as well as methods, including a non-self-aligned and self-aligned, of fabricating such a device are disclosed herein. The semiconductor device includes field effect transistor 124 comprising at least body region 127 and diffusion regions 132; buried interconnect plane 122 optionally self-aligned to diffusion regions 132 and in contact with body region 127; isolation oxide region 118 between diffusion regions 132 and buried interconnect plane 122; and buried oxide layer 104 present beneath buried interconnect plane 122.

Abstract: A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

Abstract: The present invention provides a method for fabricating a semiconductor device with ultra-shallow super-steep-retrograde epi-channel that is able to overcome limitedly useable energies and to enhance manufacturing productivity than using ultra low energy ion implantation technique that has disadvantage of difficulties to get the enough ion beam current as well as that of prolonged processing time.

Abstract: The invention discloses methods of fabricating a semiconductor device structure having low source/drain junction capacitances and low junction leakage currents. The low source/drain junction capacitances are obtained by implementing in a self-aligned manner the major portions of the heavily-doped source and drain regions of a device over the trench-isolation region using highly-conductive silicided polycrystalline- or amorphous-semiconductor and the junction leakage currents resulting from the generation/recombination current in the depletion regions of the heavily-doped source and drain junctions due to the implant-induced defects can be much reduced or eliminated. Moreover, the contacts are made on the silicided heavily-doped source and drain regions over the trench-isolation regions, the traditional contact-induced leakage current due to the shallow source/drain junction can be completely eliminated by the present invention.

Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.

Abstract: Methods for forming ultrashallow junctions in semiconductor wafers include introducing into a shallow surface layer of a semiconductor wafer a dopant material that is selected to form charge carrier complexes which produce at least two charge carriers per complex, and short-time thermal processing of the doped surface layer to form the charge carrier complexes. The short-time thermal processing step may be implemented as flash rapid thermal processing of the doped surface layer, sub-melt laser processing of the doped surface layer, or RF or microwave annealing of the doped surface layer.

Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Abstract: In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline silicon layer with one mask, a gate electrode has a high melting point metal/metallic nitride barrier/polycrystalline silicon structure. The boron is pre-doped in the polycrystalline silicon layer. The phosphorus or arsenic is doped in an n-channel area. Then, the annealing in a hydrogen atmosphere with vapor added therein is performed. As a result, the boron is segregated on the interface of the metallic nitride film and the phosphorus is segregated on the interface of the gate oxide film, for forming an n+ gate.

Abstract: A semiconductor device has first and second active regions defined on the principal surface of a silicon substrate, a first n-channel MOS transistor formed in the first active region and having first extension regions and first pocket regions being deeper than the first extension regions and being doped with indium at a first concentration, and a second n-channel MOS transistor formed in the second active region and having second extension regions and second pocket regions being deeper than the second extension regions and being doped with indium at a second concentration lower than the first concentration. Boron ions may be implanted into the second pocket regions. The pocket regions can be formed by implanting indium ions and an increase in leak current to be caused by indium implantation can be reduced.

Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).

Abstract: A method is taught for forming shallow LDD diffusions using polysilicon sidewalls as a diffusion source. The polysilicon sidewalls are formed along side squared-off silicon nitride sidewall spacers which have an essentially rectangular cross section and are in direct contact with the subjacent silicon wherein the shallow LDD elements are formed. The method is applied to the formation of a p-channel MOSFET with salicide contacts wherein the polysilicon sidewalls can be made full size because the essentially flat tops of the nearly rectangular silicon nitride sidewalls provide ample gate-to-source drain spacing to prevent silicide bridging and thereby reduce gate-to-source/drain shorts. In addition, the squared-off silicon nitride sidewalls are formed with parallel vertical sides. This permits improved control of their width, reduced lateral encroachment of boron dopant under the gate, and reduced gate-to-source drain silicide bridging.

Abstract: Gate electrodes in an inverter section and a transfer section are formed only on element areas, and connected to each other by means of local interconnection layers. As a result, a memory cell of a very small size but a large capacity can be formed without considering a gate fringe or shortening phenomenon problem.

Abstract: A method for making CMOQ transistors and associated devices. The method is used to make transistors of a first type and a second type in CMOS technology in an active layer. The method etches regions of the active layer or making them inactive so as to define active islands designed to form sources, channels of determined width, and drains of the transistors of the first type and second type respectively, covers at least two active islands with an insulating layer and covers the insulating layer with a conductive layer, and sequentially etches all the gates of the transistors of the first type and then all the gates of the transistors of the second type. The associated devices includes CMOS transistor devices obtained by the method. Such a method may particularly find application to devices for the addressing and control of active matrix liquid crystal displays.

Abstract: A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology.

Abstract: A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type.

Abstract: A dose of arsenic for an extension region in an NMOS transistor is in a range from 5×1014 to 2×1015 ions/cm2 and preferably in a range from 1.1×1015 to 1.5×1015 ions/cm2. Also, in addition to arsenic, a low concentration of phosphorus is doped into the extension region by ion implantation. Consequently, with a semiconductor device of the CMOS structure, it is possible to prevent unwanted creeping of silicide that occurs often in the shallow junction region depending on a concentration of an impurity having a low diffusion coefficient as represented by arsenic. Further, not only can the resistance in the shallow junction region be lowered, but also an amount of overlaps can be optimized in each transistor.

Abstract: Provided is a method of manufacturing a semiconductor device having an n-type FET and a p-type EFT each formed over a semiconductor substrate, which comprises (a) forming, over the n-type FET and p-type FET, a first insulating film for generating a tensile stress in the channel formation region of the n-type FET so as to cover gate electrodes of the FETs, while covering, with an insulating film, a semiconductor region between the gate electrode of the p-type FET and an element isolation region of the semiconductor substrate; (b) selectively removing the first insulating film from the upper surface of the p-type FET by etching; (c) forming, over the n-type and p-type FETs, a second insulating film for generating a compressive stress in the channel formation region of the p-type FET so as to cover the gate electrodes of the FETs; and (d) selectively removing the second insulating film from the upper surface of the n-type FET.

Abstract: A process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions. After a gate is formed on the substrate on which an N well region and a P well region are separated from each other by shallow trench isolation, a silicon nitride is formed as a diffusion source layer. Subsequently, a P type ion implantation is performed in the N well region by using boron ions to form a P type diffusion source layer in the N well region. An N type ion implantation is performed in the diffusion source layer of the P well region by using arsenic ions to form a N type diffusion source layer on the P well region. Spacers are formed at the sidewalls of the gate by deposition and etching back. Heavy ion implantation is performed in the N well region and the P well region, respectively. Finally, a rapid thermal process is carried out to form a source/drain region and ultra shallow junctions in the complementary metal oxide semiconductor device.

Abstract: A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the c

Abstract: A method of fabricating a CMOS transistor using a silicon germanium disposable spacer (114) for the source/drain implant. After gate etch, silicon germanium disposable spacers (114) are formed. A NMOS resist pattern (116) is formed exposing the NMOS regions (120) and the n-type source/drain implant is performed. The disposable spacers (114) in the NMOS regions are removed and, with the NMOS resist mask (116) still in place, the LDD/MDD implant is performed. The process may then be repeated for the PMOS regions (122).

Abstract: Retrograde wells are formed by implanting through nitride films (40). Nitride films (40) are formed after STI (20) formation. By selectively masking a portion of the wafer with photoresist (47) after portions of a retrograde well are formed (45, 50, 55, and 60) the channeling of the subsequent zero degree implants is reduced.

Abstract: The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13) formed on a main surface of a silicon substrate (1), and as another part, a fourth-layer wiring (14) to a seventh-layer wiring (17) formed on a main surface of a glass substrate (30) different from the silicon substrate (1). The main surface of the silicon substrate (1) and the main surface of the glass substrate (30) are arranged in face-to-face relation with each other, and a plurality of microbumps (20A) formed at the uppermost portion of the silicon substrate (1) and a plurality of microbumps (20B) formed at the uppermost portion of the glass substrate (30) are electrically connected, thereby constituting the CMOS logic LSI as a whole.

Abstract: A method for fabricating a semiconductor device suitable for embodying an isotropic etching profile in etching a silicon substrate when a single drain cell is formed, including the steps of: a) forming a gate electrode on a silicon substrate; b) forming a spacer contacting both sides of the gate electrode; c) growing a silicon germanium layer on the silicon substrate exposed at the bottom of the spacer; d) exposing a source/drain formation region by selectively removing the silicon germanium layer; and e) growing an epitaxial silicon layer doped on the opened source/drain region.

Abstract: A semiconductor device with low contact resistance which can cope with the miniaturization of semiconductor devices as well as a manufacturing method thereof which is easy and inexpensive can be obtained. Impurity regions on an Si substrate, an interlayer insulation film, source and drain interconnections, a metal silicide layer larger in diameter than the lower edge of the contact holes around the impurity regions are provided and the metal silicide layer includes an interface making up a border between the upper metal silicide layer contacting with the bottom of the interlayer insulation film and the lower metal silicide layer contacting with the impurity region surface. Thus, the contact area between the source and drain lines and the impurity regions can be increased via the metal silicide layer so as to reduce the contact resistance.

Abstract: A process for formation of metal silicide on elements of an NMOS device and on elements of a PMOS device, wherein the metal silicide formed on elements of the PMOS device is thinner than the metal silicide simultaneously formed on elements of said NMOS device, has been developed. The process features the implantation of metal ions such as titanium, tantalum, vanadium, or rhenium, during the implantation procedure used for formation of the heavily doped P type source/drain region of the PMOS device. The presence of the implanted metal ions in PMOS regions retard the formation of metal silicide resulting in a thinner metal silicide layer on the heavily doped P type source/drain region, when compared to the thicker metal silicide counterparts simultaneously formed on elements of the NMOS device.

Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.

Abstract: Semiconductor devices with improved transistor performance are fabricated by ion-implanting a dopant into the oxide liner to prevent or substantially reduce dopant out-diffusion from the shallow source/drain extensions. Embodiments include ion implanting a P-type dopant, such as B or BF2, using the gate electrode as a mask, to form shallow source/drain extensions, depositing a conformal oxide liner, and ion implanting the P-type impurity into the oxide liner at substantially the same dopant concentration as in the shallow source/drain extensions. Subsequent processing includes depositing a spacer layer, etching to form sidewall spacers, ion implanting to form deep moderate or heavy source/drain implants and activation annealing.

Abstract: A sidewall spacer is formed in a CMOS device by depositing a layer of silicon nitride on a wafer and anisotropically etching away the silicon nitride layer with a chorine-based plasma etchant.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A method for reducing a gate length bias is disclosed. The method utilizes an additional blanket ion implantation process to adjust the etching property of the undoped conductive layer such as a polysilicon layer used to form NMOS and PMOS gate electrodes so that the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes can be effectively reduced.

Abstract: A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

Abstract: In a method of fabricating a metal oxide semiconductor (MOS) transistor with a lightly doped drain (LDD) structure without spacers, gate electrodes and spacers are formed on a semiconductor substrate. A high density source/drain region is formed using the gate electrodes and the spacers as masks. A low density source/drain region is formed after removing the spacers. It is possible to reduce the thermal stress of the low density source/drain region by forming the high density source/drain region before the low density source/drain region is formed and to increase an area, in which suicide is formed, by forming a structure without spacers. Also, it is possible to simplify processes of fabricating a complementary metal oxide semiconductor (CMOS) LDD transistor by reducing the number of photoresist pattern forming processes in the method.

Abstract: A method for fabricating an ultra-shallow semiconductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: A method of manufacturing a transistor by using two layers of a silicon epitaxial layer is disclosed. In the first step of the manufacturing process, a spacer is formed around gate structures. Then, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited and then etched, such that the second spacer remains around a gate structure. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer, and the second spacer is etched from around the gate structure. After etching the first oxide spacer, ions are implanted at a first energy level to form four junctions. Then a third spacer is deposited and etched, so that the third spacer remains around the gate structures. Then ions are implanted at a second energy level to form two more junctions, each of these two junctions being located between two of the earlier formed junctions. The junctions and the gate structures provide a transistor structure.

Abstract: A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract: A method of fabricating a semiconductor device (300) is disclosed. A low energy ion implantation (318) may form low voltage source and drain regions in a low voltage region (402-3) of a substrate. A low energy implant may also form a portion of source and drain regions in a high voltage region (402-2). A high energy ion implantation (322) may complete the formation of high voltage transistors in a high voltage region (402-2). A high voltage gate structure (418-2) may be exposed during a high energy ion implantation and mask a channel region.

Abstract: A semiconductor device and a method for fabricating the same which improve characteristic of stand-by current of an SRAM cell is disclosed in the present invention.

Abstract: A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack comprising one or more thin film layers covers the gate oxide layer. A gate electrode pattern is partially etched into the gate stack, the partial etching step being completed before any of the gate oxide layer is exposed. Sidewall spacers are formed on edge surfaces of the partially formed gate electrode. Source and drain regions are created by ion implantation using the partially etched gate electrode and the sidewall spacers as a mask. The sidewall spacers are removed and lightly doped drain regions are formed by ion implantation using the partially etched gate electrode as a mask.

Abstract: A CMOS image sensor containing a plurality of unit pixels, each unit pixel having a light sensing region and a peripheral circuit region, includes: a semiconductor substrate of a first conductive type; a transistor formed on the peripheral circuit region of the semiconductor substrate, wherein the transistor has a gate oxide layer and a gate electrode formed on the gate oxide layer; spacers formed on sidewalls of the gate oxide layer and the gate electrode, wherein one spacer are formed on the light sensing region; a first doping region of a second conductive type formed on the light sensing region, wherein the first doping region is extended to an edge of the gate electrode; and a second doping region of the first conductive type formed on the first doping region, wherein the second doping region is extended to an edge of a spacer formed on the light sensing region.

Abstract: A method of fabricating a DRAM semiconductor device including forming gate stacks in which a gate pattern and a gate sacrificial mask are sequentially deposited on a semiconductor substrate, forming an etch stopper on the semiconductor substrate, forming a lightly doped impurity region between the gate stacks, forming a gate spacer along sidewalls of the gate stacks, forming a heavily doped impurity region to contact the lightly doped impurity region and to be aligned with the gate spacer, removing the gate spacer, forming an interlevel dielectric layer to fill a gap between the gate stacks, forming a groove on a gate conductive layer by etching an exposed top surface of the etch stopper and the gate sacrificial mask, forming a contact mask pattern for filling the groove, forming a contact hole to be self-aligned with respect to the contact mask pattern, and forming a contact pad in the contact hole.