Abstract: A stressed MOS device and a method for its fabrication are provided. The MOS device comprises a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant. A channel region is formed of the monocrystalline silicon material adjacent the surface. A stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant is grown under the channel region to exert a horizontal tensile stress on the channel region.

Abstract: A method of manufacturing a semiconductor device including MOS transistors is disclosed. N-type and p-type semiconductor films are formed respectively above first and second surface regions of a semiconductor substrate. First and second protective films are laminated on the semiconductor films. The second protective film is selectively etched to form first and second patterned films. Impurities are introduced into one of the first and second patterned films. Then, surface portions of the first and second patterned films are oxidized, and the formed oxide films are etched. The first protective film is etched using the first and second patterned films as a mask. The n-type and p-type semiconductor films are etched using the remaining first protective film as a mask to form first and second gate electrodes.

Abstract: Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate.

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract: A MOS transistor including a gate insulation layer and a gate electrode layer on a channel region of a semiconductor substrate. A gate spacer layer is formed on a sidewall of the electrode layer and the insulation layer. The transistor includes a deep extended source/drain region, a first source/drain region that is deeper than the extended source/drain region, and a second source/drain region that is shallower than the extended source/drain region.

Abstract: A semiconductor device having a dual gate is formed on a substrate having a dielectric layer. A first metallic conductive layer is formed on the dielectric layer to a first thickness, and annealed to have a reduced etching rate. A second metallic conductive layer is formed on the first metallic conductive layer to a second thickness that is greater than the first thickness. A portion of the second metallic conductive layer formed in a second area of the substrate is removed using an etching selectivity. A first gate structure having a first metallic gate including the first and the second metallic conductive layers is formed in a first area of the substrate. A second gate structure having a second metallic gate is formed in the second area. A gate dielectric layer is not exposed to an etching chemical due to the first metallic conductive layer, so its dielectric characteristics are not degraded.

Abstract: A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract: A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current.

Abstract: Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming these structures. The embodiments suppress short channel effects by incorporating buried isolation regions into a transistor below source/drain extension regions and between deep source/drain regions and the channel region and, particularly, between deep source/drain regions and the halo regions. Buried isolation regions between the deep source/drain regions and the channel region minimize drain induced barrier lowering (DIBL) as well as punch through. Additionally, because the deep source/drain regions and halo regions are separated by the buried isolation regions, side-wall junction capacitance and junction leakage are also minimized.

Abstract: MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.

Abstract: A semiconductor integrated circuit device includes an n-channel MOS transistor formed on a first device region of a silicon substrate and a p-channel MOS transistor formed on a second device region of the silicon substrate, wherein the n-channel MOS transistor includes a first gate electrode carrying a pair of first sidewall insulation films formed on respective sidewall surfaces thereof, the p-channel MOS transistor includes a second gate electrode carrying a pair of second sidewall insulation films formed on respective sidewall surfaces thereof, first and second SiGe mixed crystal regions being formed in the second device region epitaxially so as to fill first and second trenches formed at respective, outer sides of the second sidewall insulation films so as to be included in source and drain diffusions of the p-channel MOS transistor, a distance between n-type source and drain diffusion region in the first device region being larger than a distance between the p-type source and drain diffusion regions in t

Abstract: A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.

Abstract: A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS, when activating a shallow source/drain extension region.

Abstract: A method of forming a semiconductor structure includes forming a PMOS device and an NMOS device. The step of forming the PMOS device includes forming a first gate stack on a semiconductor substrate; forming a first offset spacer on a sidewall of the first gate stack; forming a stressor in the semiconductor substrate using the first offset spacer as a mask; and epitaxially growing a first raised source/drain extension (LDD) region on the stressor. The step of forming the NMOS device includes forming a second gate stack on the semiconductor substrate; forming a second offset spacer on a sidewall of the second gate stack; epitaxially growing a second raised LDD region on the semiconductor substrate using the second offset spacer as a mask; and forming a deep source/drain region adjoining the second raised LDD region.

Abstract: Provided are semiconductor devices and methods of fabricating the same. A semiconductor device may include a semiconductor substrate with a device isolation layer defining HVE and HVD active regions. Gate insulation layer patterns may be disposed on the HVE and HVD active regions. Gate electrodes may be disposed on the gate insulation layer patterns to intersect the HVE and HVD active regions and the device isolation layer. An ion implantation layer may be disposed on the semiconductor substrate under the gate electrode of the HVD active region, spaced apart from the device isolation layer, and serves to adjust a threshold voltage.

Abstract: A semiconductor device having a simple structure with selectively formed full-silicide (FUSI) and partial silicide gate electrodes and a manufacturing method thereof are provided. According to one aspect, there is provided a semiconductor device includes a first field effect transistor (MOSFET), and a second MOSFET, the first MOSFET including a first gate electrode provided on a gate insulator on a semiconductor substrate and formed of a first metal silicide layer, a first insulator provided to be adjacent to the first gate electrode, and a first sidewall including the first insulator, the second MOSFET including a second gate electrode provided on a gate insulator on the semiconductor substrate and formed of a conductor film including a polysilicon layer and a second metal silicide layer, a second insulator provided to be adjacent to the second gate electrode, and a second sidewall including the second insulator.

Abstract: A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implantation method for forming a shallow junction comprises providing a semiconductor substrate including at least one transistor structure. During ion implantation to form a shallow junction, a buffer layer is formed on the implantation region. The buffer layer has a predetermined thickness. Charged ions are implanted into the implantation region through the buffer layer by an energy provided by a middle-energy ion implanter, and the buffer layer is removed. The buffer layer is used for blocking the amount of the charged ions that will be implanted into the implantation region so as to form a shallow junction that would require a low-energy ion implanter without the buffer layer.

Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.

Abstract: A method of manufacturing a CMOS is disclosed. A substrate has a first gate and a second gate. A dielectric layer and a patterned photo-resist layer are formed sequentially on the substrate. After an etching process, the dielectric layer without the photo-resist layer forms a spacer around the first gate, and the dielectric layer with the photo-resist layer forms a block layer on the second gate. The recesses are formed in the substrate of two lateral sides of the first gate. The epitaxial silicon layers are formed in the recesses.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation for formation of source/drain regions, on the entire surface of the semiconductor substrate having the gate stack formed thereon. In accordance with the present invention, since ion implantation is carried out after formation of the gate stack involving a thermal process, there are no changes in concentrations of implanted dopants due to heat treatment upon formation of the gate stack.

Abstract: By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

Abstract: Silicide is introduced into the gate region of a CMOS device through different process options for both conventional and replacement gate types processes. Placement of silicide in the gate itself, introduction of the silicide directly in contact with the gate dielectric, introduction of the silicide as a fill on top of a metal gate all ready in place, and introduction the silicide as a capping layer on polysilicon or on the existing metal gate, are presented. Silicide is used as an option to connect between PFET and NFET devices of a CMOS structure. The processes protect the metal gate while allowing for the source and drain silicide to be of a different silicide than the gate silicide. A semiconducting substrate is provided having a gate with a source and a drain region. A gate dielectric layer is deposited on the substrate, along with a metal gate layer. The metal gate layer is then capped with a silicide formed on top of the gate, and conventional formation of the device then proceeds.

Abstract: A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

Abstract: An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.

Abstract: A method of forming a source/drain region of a semiconductor device includes forming a photoresist pattern through which an NMOS region of a semiconductor substrate is exposed, and then performing an ion implant process to form NMOS LDD regions in the semiconductor substrate of the NMOS region. An ion implant process is performed to form PMOS pocket regions in a PMOS region of the semiconductor substrate. Spacers are formed on sidewalls of a PMOS gate electrode pattern and sidewalls of an NMOS gate electrode pattern, and an ion implant process is performed to form PMOS source/drain regions in the semiconductor substrate in which the PMOS pocket regions are formed. An ion implant process is performed to form NMOS source/drain regions in the semiconductor substrate in which the NMOS LDD regions are formed.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

Abstract: An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

Abstract: A method for fabricating a semiconductor device including on a single semiconductor substrate, a first MOS transistor having a first gate insulating film of a predetermined thickness, and second and third MOS transistors sharing a second gate insulating film smaller in thickness than the first gate insulating film, the third MOS transistor being lower in threshold voltage than the second MOS transistor, the method includes the steps of: adjusting the threshold voltages of the first and third MOS transistors by first ion-implantation; and adjusting the threshold voltage of the second MOS transistor by second ion-implantation, the second ion-implantation being performed under implantation conditions different from those of the first ion-implantation.

Abstract: A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

Abstract: In a method for manufacturing a semiconductor device, gate insulation films and gate electrodes are first formed on a substrate. An impurity is implanted into each gate electrode. Next, a first heat treatment is performed to the substrate for diffusing the impurity in the gate electrodes. After the heat treatment, a second heat treatment is performed for releasing stress generated in the substrate in the first heat-treatment. Thereafter, an impurity is implanted into an area to become an implanted region of the substrate, using the gate electrodes as masks, and a third heat treatment is performed for activating the impurity implanted.

Abstract: Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material layer; depositing a protective layer on the gate electrode material layer; removing a portion of the protective layer, a portion of the gate electrode material layer, and a portion of the gate insulating layer to expose a surface area of the semiconductor substrate; performing ion implantation and heat treatment processes to form a device isolation structure; forming a gate electrode by removing a portion of the gate electrode material layer; forming an LDD region by implanting low concentration impurity ions in the semiconductor substrate; forming a spacers on a sidewall of the gate electrode; and forming a source/drain region by implanting high concentration impurity ions.

Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.

Abstract: The present invention discloses a method for fabricating a semiconductor device. A substrate is provided. At least one first and second gate structure, having sidewalls, are included on a surface of the substrate. A first ion implantation process is performed to form a shallow-junction doping region of a first conductive type in the substrate next to each of the sidewalls of the first gate structure, followed by the formation of offset spacers on each of the sidewalls of the first and second gate structure. A second ion implantation process is performed to form a shallow-junction doping region of a second conductive type in the substrate next to the offset spacer on each of the sidewalls of the second gate structure.

Abstract: The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Abstract: Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may significantly be improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract: Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a sacrificial layer on the high-k gate dielectric layer. After etching the sacrificial layer, first and second spacers are formed on opposite sides of the sacrificial layer. After removing the sacrificial layer to generate a trench that is positioned between the first and second spacers, a metal layer is formed on the high-k gate dielectric layer.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

Abstract: Methods of forming a semiconductor device are provided by forming a gate pattern that includes a gate electrode on a substrate. Lightly doped impurity diffusion layers are formed in the substrate at both sides of the gate pattern. Spacers are formed on sidewalls of the gate pattern. The spacers having a bottom width. Impurity ions are implanted using the gate pattern and the spacer as a mask to form a heavily doped impurity diffusion layer in the substrate. The spacers are removed. A conformal etch stop layer is formed on the gate pattern and the substrate. The etch stop layer is formed to a thickness of at least the bottom width of the spacers.

Abstract: Several a transistor, which are inhibited short channel effect moderately according to each transistor's channel length, are formed on a same SOI substrate. In the present invention, forming a first transistor on SOI substrate, and forming a second transistor which has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction The impurities are doped from above a surface of the SOI substrate in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor. By this means, a pocket layer is formed under an insulator layer of a SOI substrate.

Abstract: Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes first providing and masking a surface on an in-process integrated circuit wafer on which the shallow junction is to be formed. Next, a low ion velocity and low energy ion bombardment plasma doping or PLAD operation is conducted to provide a highly doped inner portion of a shallow junction. In a further step, a higher ion velocity and energy conventional ion bombardment implantation doping operation is conducted using a medium power implanter to extend the shallow junction boundaries with a lightly doped outer portion. In various embodiments, the doping steps can be performed in reverse order. In addition, an anneal step can be performed after any doping operation.

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply tensile strain to channel regions of devices while mitigating masking operations employed. A cap poly layer is formed over NMOS and PMOS regions of a semiconductor device. Then, a resist mask is employed to remove a portion of the cap poly layer from the PMOS region. Subsequently, the same resist mask and/or remaining portion of the cap poly layer is employed to form source/drain regions within the PMOS region by implanting a p-type dopant. Afterward, a cap poly thermal process is performed that causes tensile strain to be induced only in channel regions of devices located within the NMOS region. As a result, channel mobility and/or performance of devices located in the PMOS region is not substantially degraded.

Abstract: A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

Abstract: A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.