Plural Doping Steps Patents (Class 438/231)
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Patent number: 7629212Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.Type: GrantFiled: March 19, 2007Date of Patent: December 8, 2009Assignee: Texas Instruments IncorporatedInventors: Manfred Ramin, Mark R. Visokay, Michael Francis Pas
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Patent number: 7629216Abstract: A method for fabricating a complementary metal-oxide semiconductor (CMOS) image sensor includes providing a semi-finished substrate, forming a patterned blocking layer over a photodiode region of the substrate, implanting impurities on regions other than the photodiode region using a mask while the patterned blocking layer remains, and removing the mask.Type: GrantFiled: March 28, 2007Date of Patent: December 8, 2009Inventor: Han-Seob Cha
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Publication number: 20090294866Abstract: Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Inventors: Manfred Eller, Jiang Yan, Jin-Ping Han, Alois Gutmann
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Publication number: 20090291539Abstract: A method of manufacturing an LCD driver chip includes forming a heavily doped P-type well and a heavily doped N-type well over a high voltage region of a substrate; and then forming an oxide layer over the heavily doped P-type well and the heavily doped N-type; and then simultaneously forming a first gate electrode over the heavily doped P-type well and a second gate electrode over the heavily doped N-type well including the oxide layer; and then patterning the oxide layer to form a gate insulating layer under the first and second gate electrodes and an oxide layer portion connected to lateral sides of the gate insulating layers; and then forming an insulating layer over the entire surface of the substrate including the first and second gate electrodes and the oxide layer portion; and then forming spacers on sidewalls of the first and second gate electrodes and then removing the oxide layer portion after forming the spacers; and then forming ion implantations regions over the heavily doped P-type well and theType: ApplicationFiled: November 6, 2008Publication date: November 26, 2009Inventor: Duck-Ki Jang
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Publication number: 20090275179Abstract: Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).Type: ApplicationFiled: January 3, 2008Publication date: November 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, John M. Cotte, Hariklia Deligianni, Toshiharu Furukawa, Vamsi K. Paruchuri, William R. Tonti
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Publication number: 20090263945Abstract: The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: Renesas Technology Corp.,Inventors: Shimpei Tsujikawa, Yasuhiko Akamatsu, Hiroshi Umeda, Jiro Yugami, Masaharu Mizutani, Masao Inoue, Junichi Tsuchimoto, Kouji Nomura
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Publication number: 20090263946Abstract: An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kamel Benaissa, Greg Baldwin, Shashank Ekbote
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Patent number: 7601583Abstract: A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.Type: GrantFiled: December 21, 2007Date of Patent: October 13, 2009Assignee: Hynix Semiconductor Inc.Inventors: Se Aug Jang, Yong Soo Kim, Jae Geun Oh, Jae Sung Rohh, Hyun Chul Sohn
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Publication number: 20090253235Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: June 15, 2009Publication date: October 8, 2009Applicant: Renesas Technology Corp.Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20090246922Abstract: A method of forming CMOS transistor is disclosed. A CMOS transistor having a first active area and a second active area is provided. In order to maintain the concentration of the dopants in the second active area, according to the method of the present invention an ion implantation process is performed to form a lightly doped drain (LDD) in the second active area after an epitaxial layer is formed in the first active area. On the other hand, the ion implantation process is performed to form the respective LDD of the first active area and the second active area. After the epitaxial layer in the first active area is formed, another ion implantation process is performed to implant dopants into the LDD of the second active area again.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Inventors: Meng-Yi Wu, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Kun-Hsien Lee, Li-Shian Jeng, Shih-Jung Tu, Yu-Ming Lin, Yao-Chin Cheng
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Patent number: 7595234Abstract: A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.Type: GrantFiled: September 15, 2006Date of Patent: September 29, 2009Assignee: United Microelectronics Corp.Inventors: Po-Chao Tsao, Chang-Chi Huang, Ming-Tsung Chen, Yi-Yiing Chiang, Yu-Lan Chang, Chung-Ju Lee, Chih-Ning Wu, Kuan-Yang Liao
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Patent number: 7591659Abstract: A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region.Type: GrantFiled: October 4, 2005Date of Patent: September 22, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: John Chen, Xian J. Ning, Hanming Wu
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Patent number: 7582523Abstract: A method of manufacturing a semiconductor device including MOS transistors is disclosed. N-type and p-type semiconductor films are formed respectively above first and second surface regions of a semiconductor substrate. First and second protective films are laminated on the semiconductor films. The second protective film is selectively etched to form first and second patterned films. Impurities are introduced into one of the first and second patterned films. Then, surface portions of the first and second patterned films are oxidized, and the formed oxide films are etched. The first protective film is etched using the first and second patterned films as a mask. The n-type and p-type semiconductor films are etched using the remaining first protective film as a mask to form first and second gate electrodes.Type: GrantFiled: January 23, 2008Date of Patent: September 1, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoya Satonaka, Hideki Oguma
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Publication number: 20090197377Abstract: A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.Type: ApplicationFiled: August 6, 2008Publication date: August 6, 2009Inventors: Sreenivasa Chalamala, Matthias Baer
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Publication number: 20090186457Abstract: The present invention relates to semiconductor devices, and more particularly to a method for forming a CMOS semiconductor device, the method including a first integration anneal sequence for each NFET and a second integration anneal sequence for each PFET of the semiconductor device. The method includes providing a structure having an nFET gate stack and a pFET gate stack patterned on a substrate. A first disposable spacer is formed adjacent the nFET gate stack and a second disposable spacer is formed adjacent the pFET gate stack. A first doped S/D region and a second doped S/D region are then formed in the substrate. The first and second disposable spacers are removed after the first and second doped S/D regions are formed. A first halo implant and a first S/D extension region are formed adjacent the nFET gate stack after the first and second disposable spacers are removed. The structure is annealed using a RTA process.Type: ApplicationFiled: January 23, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kam-Leung Lee, Paul M. Kozlowski
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Patent number: 7563665Abstract: To laminate field effect transistors having different conductivity types, while suppressing deterioration of the crystallinity of semiconductor layers where the field effect transistors are formed. A single crystal semiconductor layer, a dielectric layer and a single crystal semiconductor layer are successively laminated on a dielectric layer, a gate electrode is formed on side walls on both sides of the single crystal semiconductor layers through gate dielectric films and formed on side surfaces on both side of the single crystal semiconductor layers, source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer 13a, and source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer, whereby a P-channel field effect transistor MP1 and an N-channel field effect transistor MN1 are laminated.Type: GrantFiled: May 13, 2005Date of Patent: July 21, 2009Assignee: Seiko Epson CorporationInventor: Juri Kato
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Patent number: 7560319Abstract: A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.Type: GrantFiled: March 30, 2007Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Kwan Kang, Yu-Gyun Shin, Jong-Wook Lee, Yong-Hoon Son
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Publication number: 20090174002Abstract: Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material may be grown only in the source and drain extension regions, or in the source and drain extension regions and in deep source and drain regions. In one embodiment, an etch process that removes doped semiconductor regions of one conductivity type selective to doped semiconductor regions of another conductivity type may be employed. In another embodiment, a dopant concentration dependent etch process that removes doped semiconductor regions irrespective of the conductivity type selective to undoped semiconductor regions may be employed.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qiqing Ouyang, Kathryn T. Schonenberg, John Yates, III
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Publication number: 20090170259Abstract: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Applicant: Texas Instruments IncorporatedInventors: Brian Edward Hornung, Rajesh Gupta, Mike Voisard
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Patent number: 7550396Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.Type: GrantFiled: May 1, 2007Date of Patent: June 23, 2009Assignee: Advanced Micro Devices, Inc.Inventors: Kai Frohberg, Volker Grimm, Sven Mueller, Matthias Lehr, Ralf Richter, Jochen Klais, Martin Mazur, Heike Salz, Joerg Hohage, Matthias Schaller
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Patent number: 7528030Abstract: A semiconductor device includes at least one MOS transistor, each transistor being provided with a source region and a drain region formed in a semiconductor substrate, along with a gate region and spacers. The transistor is covered with a unitary etch stop layer that includes at least a first zone having a first residual stress level (in tension) covering at least one part of the transistor and at least a second zone having a second residual stress level (in compression) covering at least another part of the device. With this configuration, the first residual stress level is higher than the second residual stress level.Type: GrantFiled: September 8, 2006Date of Patent: May 5, 2009Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat a l'Energie AtomiqueInventors: Pierre Morin, Catherine Chaton
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Patent number: 7524716Abstract: A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.Type: GrantFiled: May 30, 2007Date of Patent: April 28, 2009Assignee: United Microelectronics Corp.Inventors: Shyh-Fann Ting, Cheng-Tung Huang, Wen-Han Hung, Li-Shian Jeng, Kun-Hsien Lee, Tzyy-Ming Cheng, Jing-Chang Wu, Tzermin Shen
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Publication number: 20090104743Abstract: Metal Oxide Semiconductor (MOS) transistors fabricated using current art may utilize a nitridation process on the gate dielectric to improve transistor reliability. Nitridation by the current art, which involves exposing the gate dielectric to a nitridation source, produces a significant concentration of nitrogen at the interface of the gate dielectric and the transistor substrate, which adversely affects transistor performance. This invention comprises the process of depositing a sacrificial layer on the gate dielectric prior to nitridation, exposing the sacrificial layer to a nitridation source, during which time nitrogen atoms diffuse through the sacrificial layer into the gate dielectric, then removing the sacrificial layer without degrading the gate dielectric. Work associated with this invention on high-k gate dielectrics has demonstrated a 20 percent reduction in nitrogen concentration at the gate dielectric-transistor substrate interface.Type: ApplicationFiled: September 24, 2007Publication date: April 23, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Husam Alshareef, Manuel Quevedo Lopez
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Publication number: 20090098695Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted.Type: ApplicationFiled: October 10, 2007Publication date: April 16, 2009Applicant: Texas Instruments IncorporatedInventors: Shashank Ekbote, Deborah J. Riley, Borna Obradovic
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Publication number: 20090093095Abstract: A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.Type: ApplicationFiled: October 8, 2007Publication date: April 9, 2009Inventors: Borna Obradovic, Shashank S. Ekbote
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Patent number: 7514309Abstract: A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.Type: GrantFiled: July 19, 2005Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: Seetharaman Sridhar, Craig Hall, Che-Jen Hu, Antonio Luis Pacheco Rotondaro
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Patent number: 7510925Abstract: A method of manufacturing a semiconductor device includes: the first step of forming a gate electrode over a silicon substrate, with a gate insulating film; and the second step of digging down a surface layer of the silicon substrate by etching conducted with the gate electrode as a mask. The method of manufacturing the semiconductor device further includes the third step of epitaxially growing, on the surface of the dug-down portion of the silicon substrate, a mixed crystal layer including silicon and atoms different in lattice constant from silicon so that the mixed crystal layer contains an impurity with such a concentration gradient that the impurity concentration increases along the direction from the silicon substrate side toward the surface of the mixed crystal layer.Type: GrantFiled: April 25, 2007Date of Patent: March 31, 2009Assignee: Sony CorporationInventor: Yuki Miyanami
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Publication number: 20090079008Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm?2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.Type: ApplicationFiled: September 12, 2008Publication date: March 26, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mahalingam Nandakumar, Song Zhao, Amitabh Jain
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Publication number: 20090081837Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Zhonghai SHI, Mark MICHAEL, David WU, James F. BULLER, Jingrong ZHOU, Akif SULTAN, Donna Michael
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Patent number: 7507618Abstract: A method of making a thin film transistor comprises (a) solution depositing a dispersion comprising semiconducting metal oxide nanoparticles onto a substrate, (b) sintering the nanoparticles to form a semiconductor layer, and (c) optionally subjecting the resulting semiconductor layer to post-deposition processing.Type: GrantFiled: June 27, 2005Date of Patent: March 24, 2009Assignee: 3M Innovative Properties CompanyInventor: Timothy D. Dunbar
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Patent number: 7504289Abstract: An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.Type: GrantFiled: October 26, 2005Date of Patent: March 17, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Sangwoo Lim, Stanley L. Filipiak, Paul A. Grudowski, Venkat R. Kolagunta
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Publication number: 20090065807Abstract: The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating film and a first gate electrode formed on the first region, first sidewalls formed on the side faces of the first gate electrode, and first source/drain regions made of silicon formed in portions of the first region. The second MIS transistor has a second gate insulating film and a second gate electrode formed on the second region, second sidewalls formed on the side faces of the second gate electrode, and second source/drain regions including silicon germanium formed in portions of the second region. The second sidewalls are smaller in height than the first sidewalls.Type: ApplicationFiled: August 29, 2008Publication date: March 12, 2009Inventor: Hiromasa FUJIMOTO
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Patent number: 7494862Abstract: Methods for uniformly tip doping a silicon body of a non-planar transistor and devices and systems formed by such methods. In one embodiment, a method can include vertical tip ion implantation of a silicon body with at least three surfaces on a substrate followed by conformal deposition of a dielectric material. The dielectric material can be selectively etched to expose a top surface of the silicon body followed by selective re-oxidation of the top surface for form a mask. The remaining dielectric material can be removed followed by angled ion implantation of at least two sidewalls of the silicon body. The mask can be removed resulting in a silicon body with uniform doping.Type: GrantFiled: September 29, 2006Date of Patent: February 24, 2009Assignee: Intel CorporationInventors: Brian Doyle, Robert Chau, Suman Datta, Jack Kavalieros
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Patent number: 7473595Abstract: A method for decreasing a PN junction leakage current of a dynamic random access memory (DRAM), including the steps of: preparing an NMOS transistor formed on a P-type silicon substrate and comprising a drain; forming an insulation oxide layer on the P-type silicon substrate; etching the insulation oxide layer until the P-type silicon substrate is exposed so as to form a bit line contact hole on the drain; implanting arsenic ions into the P-type silicon substrate via the bit line contact hole to form an arsenic bit line contact window; and implanting phosphorus ions into the P-type silicon substrate via the bit line contact hole to form a phosphorus bit line contact window below the arsenic bit line contact window. In this way, a concentration gradient of N-type ions can be reduced at the bit line contact window, and further a PN junction leakage current can be reduced, thus lowing the power consumption of the DRAM when the DRAM is used for a low power consumption product.Type: GrantFiled: December 29, 2006Date of Patent: January 6, 2009Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Yonggang Wang, Jianguang Chang
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Publication number: 20090001371Abstract: A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.Type: ApplicationFiled: February 5, 2008Publication date: January 1, 2009Inventors: Anthony Mowry, Markus Lenski, Andy Wei, Roman Boschke
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Patent number: 7470562Abstract: Methods of forming a field effect transistor by forming a gate electrode on a semiconductor substrate and forming aluminum oxide spacers on sidewalls of the gate electrode. Source and drain region dopants of first conductivity type are implanted into the semiconductor substrate using the aluminum oxide spacers as an implant mask. Thereafter, the aluminum oxide spacers are selectively removed by exposing them to tetramethyl ammonium hydroxide (TMAH). The step of selectively removing the aluminum oxide spacers may include exposing the aluminum oxide spacers to tetramethyl ammonium hydroxide having a temperature of about 80° C.Type: GrantFiled: November 7, 2005Date of Patent: December 30, 2008Assignees: Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: Jong Pyo Kim, Andre I. Nasr
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Patent number: 7456062Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.Type: GrantFiled: August 23, 2005Date of Patent: November 25, 2008Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Thorsten Kammler, Eric N. Paton, Paul R. Besser, Simon Siu-Sing Chan
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Publication number: 20080283926Abstract: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate having a PMOS device region and NMOS device region. Thereafter, a first gate structure and a second gate structure are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions and activated second source/drain regions, respectively.Type: ApplicationFiled: May 18, 2007Publication date: November 20, 2008Applicant: Texas Instruments IncorporatedInventor: Seetharaman Sridhar
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Publication number: 20080274598Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.Type: ApplicationFiled: March 19, 2007Publication date: November 6, 2008Inventors: Manfred Ramin, Mark R. Visokay, Michael Francis Pas
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Publication number: 20080265332Abstract: A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Yoshikazu Moriwaki
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Patent number: 7439124Abstract: Method of manufacturing a semiconductor device includes: forming a substrate protection film to cover an n-type FET forming region having a first gate electrode and a p-type FET forming region having a second gate electrode; opening the p-type FET forming region by patterning a resist film after the resist film is formed to cover the n-type FET and p-type FET forming regions; exposing the surface of the semiconductor substrate by selectively removing the substrate protection film in the p-type FET forming region, leaving the film only on side walls of the second gate electrode; forming a pair of p-type extension regions at both sides of the second gate electrode, by doping impurities to the semiconductor substrate, with the resist film, the second gate electrode, and the substrate protection film formed on side walls of the second electrode; and removing the resist film formed on the n-type FET forming region.Type: GrantFiled: April 11, 2006Date of Patent: October 21, 2008Assignee: NEC Electronics CorporationInventors: Toshinori Fukai, Akihito Sakakidani
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Patent number: 7439123Abstract: A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic layer on the first metallic layer; doping the first metallic layer with a first dopant through a portion of the second metal layer disposed over the second gate with spacers; and then heating the intermediate structure to a temperature and for a time sufficient to form a silicide of the first metallic layer. This first layer is, for example, Ni while the second layer is, for example, TiN.Type: GrantFiled: October 31, 2005Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventors: Dureseti Chidambarrao, William K. Henson
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Patent number: 7432144Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.Type: GrantFiled: December 30, 2005Date of Patent: October 7, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Kye-Nam Lee
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Patent number: 7432570Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.Type: GrantFiled: December 7, 2006Date of Patent: October 7, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
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Publication number: 20080242017Abstract: A method of fabricating metal-oxide-semiconductor (MOS) transistor devices is disclosed. A semiconductor substrate is provided. A gate dielectric layer is formed. A gate electrode is stacked on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. Using the gate electrode and the silicon nitride spacer as an implantation mask, a source/drain is implanted into the substrate. After the source/drain implant, the silicon nitride spacer is then stripped. A silicide layer is formed on the source/drain region. Subsequently, a silicon nitride cap layer is deposited. The silicon nitride cap layer has a specific stress status.Type: ApplicationFiled: March 26, 2007Publication date: October 2, 2008Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Shyh-Fann Ting, Li-Shian Jeng, Wen-Han Hung, Tzyy-Ming Cheng, Chia-Wen Liang
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Publication number: 20080237727Abstract: The present invention provides a CMIS device that achieves a low threshold voltage by use of a metal gate superior in the resistance to annealing in a reducing atmosphere. The CMIS device includes a substrate, PMISFET and NMISFET. THE PMISFET includes: an N-type semiconductor layer formed on the substrate; first source/drain regions formed in the N-type semiconductor layer; a first gate insulating film formed on the N-type semiconductor layer between the first source/drain regions; a carbon layer formed on the first gate insulating film and having a thickness of 5 nanometers or smaller; a first gate electrode formed on the carbon layer and including a metal.Type: ApplicationFiled: December 27, 2007Publication date: October 2, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Reika ICHIHARA, Yoshinori Tsuchiya, Masato Koyama
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Publication number: 20080237743Abstract: A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. The method includes an independent work function adjustment process that implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants Lanthanide series dopants into a gate polysilicon layer of NMOS.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Manfred Ramin, Michael Pas
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Publication number: 20080220574Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.Type: ApplicationFiled: March 5, 2007Publication date: September 11, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Li-Shian Jeng, Cheng-Tung Huang, Shyh-Fann Ting, Wen-Han Hung, Kun-Hsien Lee, Meng-Yi Wu, Tzyy-Ming Cheng
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Patent number: 7413946Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.Type: GrantFiled: December 4, 2006Date of Patent: August 19, 2008Assignee: Micron Technology, Inc.Inventors: Mark Helm, Xianfeng Zhou
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Publication number: 20080191243Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.Type: ApplicationFiled: February 8, 2007Publication date: August 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yaocheng Liu, Shreesh Narasimha, Katsunori Onishi, Kern Rim