Stacked Capacitor Patents (Class 438/253)
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Patent number: 7968403Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.Type: GrantFiled: September 1, 2006Date of Patent: June 28, 2011Assignee: Micron Technology, Inc.Inventors: Philip J. Ireland, Howard E. Rhodes
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Patent number: 7964471Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.Type: GrantFiled: March 3, 2010Date of Patent: June 21, 2011Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Kevin R. Shea
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Publication number: 20110140187Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.Type: ApplicationFiled: February 28, 2011Publication date: June 16, 2011Applicant: Micron Technology, Inc.Inventors: Larson Lindholm, David Hwang
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Patent number: 7960227Abstract: After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.Type: GrantFiled: August 18, 2009Date of Patent: June 14, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Yasuhiro Hayashi, Kazutoshi Izumi
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Patent number: 7955945Abstract: A process for making a dielectric material where a precursor polymer selected from poly(phenylene vinylene) polyacetylene, poly(p-phenylene), poly(thienylene vinylene), poly(1,4-naphthylene vinylene), and poly(p-pyridine vinylene) is energized said by exposure by radiation or increase in temperature to a level sufficient to eliminate said leaving groups contained within the precursor polymer, thereby transforming the dielectric material into a conductive polymer. The leaving group in the precursor polymer can be a chloride, a bromide, an iodide, a fluoride, an ester, an xanthate, a nitrile, an amine, a nitro group, a carbonate, a dithiocarbamate, a sulfonium group, an oxonium group, an iodonium group, a pyridinium group, an ammonium group, a borate group, a borane group, a sulphinyl group, or a sulfonyl group.Type: GrantFiled: September 28, 2010Date of Patent: June 7, 2011Assignee: Sandia CorporationInventors: Shawn M. Dirk, Ross S. Johnson, David R. Wheeler, Gregory R. Bogart
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Patent number: 7951667Abstract: A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions.Type: GrantFiled: December 5, 2008Date of Patent: May 31, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin Soo Kim
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Patent number: 7951668Abstract: A process for fabricating crown capacitors is described. A substrate having a template layer thereon is provided. A patterned support layer is formed over the template layer. A sacrifice layer is formed over the substrate covering the patterned support layer. Holes are formed through the sacrifice layer, the patterned support layer and the template layer, wherein the patterned support layer is located at a depth at which bowing of the sidewalls of the holes occurs and is bowed less than the sacrifice layer at the sidewalls. A substantially conformal conductive layer is formed over the substrate. The conductive layer is then divided into lower electrodes of the crown capacitors.Type: GrantFiled: January 14, 2009Date of Patent: May 31, 2011Assignee: Powerchip Semiconductor Corp.Inventors: Kun-Jung Wu, Nagai Yukihiro
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Patent number: 7947554Abstract: According to an aspect of the invention, there is provided a semiconductor device including a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers, a first insulating film and a second insulating film formed on source/drain regions and gate electrodes of the first element and the second element, the first insulating film having tensile stress with respect to the first element, and the second insulating film having compression stress with respect to the second element, and sidewall spacers of the gate electrodes of the first element and the second element, at least portions of the sidewall spacers being removed, wherein at least one of the first insulating film and the second insulating film does not close a spacing between the gate electrodes of the first element and the second element.Type: GrantFiled: September 28, 2007Date of Patent: May 24, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hideki Inokuma
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Publication number: 20110110156Abstract: There is provided a technology which can allow a semiconductor chip formed with a nonvolatile memory to be sufficiently reduced in size. There is also provided a technology which can ensure the reliability of the nonvolatile memory. In a memory cell of the present invention, a boost gate electrode is formed over a control gate electrode via an insulating film. The boost gate electrode has the function of boosting a voltage applied to a memory gate electrode through capacitive coupling between the boost gate electrode and the memory gate electrode. That is, during a write operation or an erase operation to the memory cell, a high voltage is applied to the memory gate electrode and, to apply the high voltage to the memory gate electrode, the capacitive coupling using the boost gate electrode is subsidiarily used in the present invention.Type: ApplicationFiled: October 23, 2010Publication date: May 12, 2011Inventors: Yoshiyuki KAWASHIMA, Takashi Hashimoto
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Patent number: 7939404Abstract: A manufacturing method of a capacitor of a semiconductor device includes a first step of forming a graphene seed film over a substrate; a second step of increasing surface energy of the graphene seed film and performing a first plasma process to the graphene seed film; a third step of growing a graphene on the graphene seed film; a fourth step of growing a nano tube or a nano wire using the graphene as a mask; and a fifth step of sequentially forming a dielectric film and a conductive layer over the nano tube or the nano wire.Type: GrantFiled: December 28, 2009Date of Patent: May 10, 2011Assignee: Hynix Semiconductor IncInventor: Chi Hwan Jang
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Patent number: 7939877Abstract: Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions.Type: GrantFiled: March 23, 2009Date of Patent: May 10, 2011Assignee: Micron Technology, Inc.Inventor: John Kennedy
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Patent number: 7939872Abstract: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.Type: GrantFiled: March 28, 2008Date of Patent: May 10, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Sang-Yeol Kang, Ki-Vin Lim, Hoon-Sang Choi, Eun-Ae Chung
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Publication number: 20110092036Abstract: After forming a first capacitor hole, first mask material is filled in an upper portion of the first capacitor hole. A second capacitor hole is formed so that it is aligned with the first capacitor hole. After removing the first mask material, a lower electrode is formed in the first and second capacitor holes by one film formation step. After that, a capacitor dielectric film and an upper electrode are sequentially formed on the lower electrode.Type: ApplicationFiled: August 17, 2010Publication date: April 21, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Yoshitaka NAKAMURA
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Patent number: 7927945Abstract: Provided is a method for manufacturing a semiconductor device having a 4F2 transistor. In the method, a gate stack is formed on a semiconductor substrate. A first interlayer dielectric including a contact hole which includes a first region and second regions Spacer layers are formed on both sides of the gate stack and a portion of the second region. Landing plugs are formed on the contact hole, a portion of the semiconductor substrate exposed by a thickness of the spacer layer, and a lateral side of the trench. A second interlayer dielectric is formed to separate the landing plug. The bit line contact plug is connected to a first portion of the landing plug that extends to the lateral side of the trench. The bit line stack is connected to the bit line contact plug. The storage node contact plug is connected to the first portion and a second portion of the landing plug located at a corresponding position in a diagonal direction.Type: GrantFiled: May 8, 2008Date of Patent: April 19, 2011Assignee: Hynix Semiconductor Inc.Inventor: Jin Yul Lee
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Patent number: 7927928Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.Type: GrantFiled: January 16, 2008Date of Patent: April 19, 2011Assignee: Cadence Design Systems, Inc.Inventor: Christophe Pierrat
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Patent number: 7928420Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.Type: GrantFiled: December 10, 2003Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: David V. Horak, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 7927990Abstract: A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.Type: GrantFiled: June 29, 2007Date of Patent: April 19, 2011Assignee: SanDisk CorporationInventors: Kang-Jay Hsia, Calvin K Li, Christopher J Petti
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Patent number: 7927947Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.Type: GrantFiled: June 30, 2009Date of Patent: April 19, 2011Assignee: Intermolecular, Inc.Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
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Publication number: 20110086490Abstract: A single-side implanting process for capacitors of stack DRAM is disclosed. Firstly, form a stacked structure with a dielectric layer and an insulating nitride layer on a semi-conductor substrate and etch the stacked structure to form a plurality of trenches. Then, form conductive metal plates respectively on an upper surface of the stacked structure and bottoms of the trenches, form a continuous conductive nitride film, form a continuous oxide film, and form a photo resist layer for covering the trenches which are provided for isolation. Then, form a plurality of implanted oxide areas on a single-side surface, remove the photo resist layer, remove the plurality of implanted oxide areas, remove the conductive metal plates and the conductive nitride film uncovered by the oxide film, and remove the oxide film and the dielectric film.Type: ApplicationFiled: March 10, 2010Publication date: April 14, 2011Applicant: INOTERA MEMORIES, INC.Inventors: HSIAO-LEI WANG, SHIN BIN HUANG, CHING-NAN HSIAO, CHUNG-LIN HUANG
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Patent number: 7923719Abstract: In the present invention, a semiconductor device that has a nonvolatile memory element to which data can be written at times other than during manufacture and in which forgery and the like performed by rewriting of data can be prevented is provided. In addition, a semiconductor device in which a high level of integration is possible is provided. Furthermore, a semiconductor device in which miniaturization is possible is provided. In a semiconductor device having a memory element that includes a first conductive layer, a second conductive layer, and an organic compound layer interposed between the first conductive layer and the second conductive layer; the second conductive layer is connected to a wiring, formed in the same way as the first conductive layer is formed, through an opening formed in the organic compound layer.Type: GrantFiled: April 25, 2007Date of Patent: April 12, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kiyoshi Kato, Ryoji Nomura
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Patent number: 7923645Abstract: A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.Type: GrantFiled: June 20, 2007Date of Patent: April 12, 2011Assignee: Amkor Technology, Inc.Inventors: Ronald Patrick Huemoeller, Sukianto Rusli, Robert F. Darveaux
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Publication number: 20110079836Abstract: A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Inventor: Shian-Jyh Lin
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Publication number: 20110073925Abstract: A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.Type: ApplicationFiled: December 30, 2009Publication date: March 31, 2011Inventors: Eun-Shil PARK, Young-Seok Eun, Kee-Jeung Lee, Min-Soo Kim
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Patent number: 7915656Abstract: A nonvolatile semiconductor memory apparatus (10) of the present invention comprises a semiconductor substrate (11), an active element forming region provided on the semiconductor substrate (11) and including a plurality of active elements (12), a wire forming region which is provided on the active element forming region to electrically connect the active elements (12) and includes plural layers of semiconductor electrode wires (15, 16), a memory portion forming region (100) which is provided above the wire forming region and provided with memory portions (26) arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, and an oxygen barrier layer (17) which is provided between the memory portion forming region (100) and the wire forming region so as to extend continuously over at least an entire of the memory portion forming region (100).Type: GrantFiled: October 22, 2007Date of Patent: March 29, 2011Assignee: Panasonic CorporationInventors: Takumi Mikawa, Takeshi Takagi
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Patent number: 7915117Abstract: An electroluminescence (EL) device includes a substrate and a plurality of pixels formed on the substrate. Each pixel includes a first area including at least a first capacitor and a second capacitor, the first capacitor including a first conductive layer, a first dielectric layer over the first conductive layer, and a second conductive layer over the first dielectric layer, and the second capacitor including the second conductive layer, a second dielectric layer over the second conductive layer, and a third conductive layer over the second dielectric layer, and a second area including a first semiconductor layer formed on the substrate, a first gate oxide layer over the first semiconductor layer, and a fourth conductive layer over the first gate oxide layer.Type: GrantFiled: December 28, 2006Date of Patent: March 29, 2011Assignee: Au Optronics CorporationInventor: Wein-Town Sun
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Patent number: 7915135Abstract: The present invention discloses a method of making a multi-layer structure for metal-insulator-metal capacitors, in which, a bottom electrode plate layer is formed on a substrate, wherein a Ti/TiN layer serving as a top anti-reflection coating (top ARC) of the bottom electrode plate layer including a titanium layer and a titanium nitride layer formed on the titanium layer is formed using a first and a second physical vapor deposition (PVD) processes at a temperature ranging from 25 to 400° C., and then a first capacitor dielectric layer, a middle electrode plate layer, a second capacitor dielectric layer, and a top electrode plate layer are formed on the bottom electrode plate layer in an order from bottom to top.Type: GrantFiled: April 30, 2009Date of Patent: March 29, 2011Assignee: United Microelectronics Corp.Inventors: Chun-Kai Wang, Chun-Chih Huang, Chun-Ming Wu
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Patent number: 7910428Abstract: A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.Type: GrantFiled: June 29, 2008Date of Patent: March 22, 2011Assignee: Hynix Semiconductor Inc.Inventors: Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
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Patent number: 7908744Abstract: A method of fabricating a printed circuit board having capacitance components, including: providing a core board having first and second surfaces with first and second wiring layers provided thereon, respectively, and electrically connected, a second dielectric layer, and a carrier board sequentially provided thereon with a second metal layer, a high dielectric material layer, and a third wiring layer with a plurality of first electrode plates thereon; laminating the core board, second dielectric layer, and carrier board to one another; removing the carrier board so as to expose the second metal layer; and patterning the second metal layer so as to form a fifth wiring layer having a plurality of second electrode plates and a plurality of second conductive vias electrically connected to the third wiring layer, thereby allowing the first electrode plates, high dielectric material layer, and second electrode plates together to form a plurality of capacitance components.Type: GrantFiled: August 14, 2009Date of Patent: March 22, 2011Assignee: Unimicron Technology Corp.Inventors: Shin-Ping Hsu, Chih-Kui Yang
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Patent number: 7906392Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.Type: GrantFiled: January 15, 2008Date of Patent: March 15, 2011Assignee: SanDisk 3D LLCInventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
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Patent number: 7902059Abstract: In a method of manufacturing a floating gate of a non-volatile semiconductor memory, a pattern is formed on a substrate to have an opening that exposes a portion of the substrate. A first preliminary polysilicon layer is formed on the pattern and the exposed portion of the substrate to substantially fill the opening. A first polysilicon layer is formed by partially etching the first preliminary polysilicon layer until a first void formed in the first preliminary polysilicon layer is exposed. A second polysilicon layer is formed on the first polysilicon layer.Type: GrantFiled: October 29, 2009Date of Patent: March 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Jai-Dong Lee, Young-Seok Kim, Young-Sub You, Ki-Su Na, Woong Lee
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Patent number: 7897454Abstract: The present invention provides a metal-insulator-metal capacitor, which comprises a semiconductor substrate; an interlayer dielectric layer disposed on the semiconductor substrate; and an insulation trench and two metal trenches all running through the interlayer dielectric layer and allowing the semiconductor substrate to be exposed; wherein the metal trenches being located on each side of the insulation trench and sharing a trench wall with the insulation trench respectively, the insulation trench being filled with insulation material as an insulation structure, the metal trenches being filled with metal material as electrodes of the capacitor.Type: GrantFiled: August 3, 2007Date of Patent: March 1, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Yuan Wang, Buxin Zhang
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Patent number: 7897413Abstract: The present invention provides a method for manufacturing a semiconductor device, including the steps of: forming a ferroelectric film on a first conductive film by a sol-gel method; forming a first conductive metal oxide film on the ferroelectric film; carrying out a first annealing on the first conductive metal oxide film; forming a second conductive metal oxide film on the first conductive metal oxide film, so that the first and second conductive films serve as a second conductive film; and forming a capacitor by patterning the first conductive film, the ferroelectric film and the second conductive film. In the step of forming the first conductive metal oxide film, ferroelectric characteristics are adjusted with a flow rate ratio of oxygen by utilizing the fact that the ferroelectric characteristics of the ferroelectric film improve as the flow rate ratio of oxygen in a sputtering gas increases.Type: GrantFiled: November 13, 2007Date of Patent: March 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Wensheng Wang, Yoshimasa Horii
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Patent number: 7897474Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A second insulating film may be formed over a first insulating film. At least one through-hole may be formed, which penetrates the first and second insulating films. At least one first electrode may be formed, which extends at least along the side wall of the at least one through-hole. The first inter-layer insulator may be removed, while using the second insulating film as a temporary supporter that supports the at least one first electrode. At least one permanent supporter may be formed, which supports the at least one first electrode. The second insulating film as the temporary supporter may be removed, while leaving the at least one permanent supporter to support the at least one first electrode.Type: GrantFiled: December 3, 2008Date of Patent: March 1, 2011Assignee: Elpida Memory, Inc.Inventor: Toyonori Eto
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Patent number: 7892918Abstract: A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.Type: GrantFiled: July 9, 2008Date of Patent: February 22, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Yoon Lee, Hyuck-Chai Jung
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Publication number: 20110037111Abstract: The invention relates to a semiconductor device and a method of fabricating the same, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance, and the SAC process is eliminated at the time of the bit line formation. A method of fabricating a semiconductor device according to the invention comprises: forming a device isolation film for defining a multiplicity of active regions in a semiconductor substrate; forming a multiplicity of buried word lines in the semiconductor substrate; forming a storage node contact hole for exposing a storage node contact region of two adjoining active regions; filling the storage node contact hole with a storage node contact plug material; forming a bit-line groove for exposing a bit-line contact region of the active region and splitting the storage node contact plug material into two; and burying the bit line into the bit-line groove.Type: ApplicationFiled: December 29, 2009Publication date: February 17, 2011Applicant: Hynix Semiconductor Inc.Inventors: Do Hyung KIM, Young Man Cho
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Patent number: 7888202Abstract: A method and apparatus for reducing parasitic capacitance. A P-well blocked layer is formed directly beneath a parasitic device. The P-well blocked layer significantly increases the resistance underneath the parasitic device. The resistance of the P-well blocked layer, in effect, partially disconnects the parasitic device from the ground terminal to minimize the effective capacitive impedance that is added to the total termination impedance.Type: GrantFiled: September 14, 2009Date of Patent: February 15, 2011Assignee: Xilinx, Inc.Inventors: Firas N. Abughazaleh, Brian T. Brunn
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Patent number: 7880213Abstract: A structure and a method of fabricating a bottom electrode of a metal-insulator-metal (MIM) capacitor are provided. First, a transition metal layer is formed on a substrate. Thereafter, a self-assembling polymer film having a nano-pattern is formed on the transition metal layer to expose a portion of the transition metal layer. Using the self-assembling polymer film as a mask, the exposed portion of the transition metal layer is treated to undergo a phase change so that the bottom electrode can achieve a nano-level of phase separation. Thereafter, the self-assembling polymer film is removed.Type: GrantFiled: May 15, 2006Date of Patent: February 1, 2011Assignee: Industrial Technology Research InstituteInventors: Wen-Miao Lo, Lurng-Sheng Lee, Pei-Ren Jeng, Cha-Hsin Lin, Ching-Chiun Wang
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Patent number: 7879671Abstract: A method for manufacturing a semiconductor device that is less prone to DC failures brought about by unwanted defects on capacitors in the device is presented. Manufacturing defects such as scratches are known to occur when making capacitors and that these defects are thought to be a primary cause of subsequent performance DC failures in the completed semiconductor devices. The method includes the steps of depositing, removing, forming, polishing, etching and forming. A sacrificial layer is exploited to allow a subsequent polishing down step to mechanically remove defects from the capacitors.Type: GrantFiled: June 26, 2009Date of Patent: February 1, 2011Assignee: Hynix Semiconductor Inc.Inventor: Hyuk Kwon
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Patent number: 7871892Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.Type: GrantFiled: June 7, 2009Date of Patent: January 18, 2011Assignee: Kinsus Interconnect Technology Corp.Inventors: Chien-Wei Chang, Ting-Hao Lin, Ya-Hsiang Chen, Yu-Te Lu
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Patent number: 7867842Abstract: A method for forming alloy deposits at selected areas on a receiving substrate includes the steps of: providing an alloy carrier including at least a first decal including a first plurality of openings and a second decal including a second plurality of openings, the first and second decals being arranged such that each of the first plurality of openings is in alignment with a corresponding one of the second plurality of openings; filling the first and second plurality of openings with molten alloy; cooling the molten alloy to thereby form at least first and second plugs, the first plug having a first surface and a second surface substantially parallel to one another, the second plug having a third surface and a fourth surface substantially parallel to one another; removing at least one of the first and second decals to at least partially expose the first and second plugs; aligning the alloy carrier with the receiving substrate so that the first and second plugs correspond to the selected areas on the receivinType: GrantFiled: July 29, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Peter Alfred Gruber, Paul Alfred Lauro, Jae-Woong Nah
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Publication number: 20100330813Abstract: The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.Type: ApplicationFiled: September 10, 2010Publication date: December 30, 2010Applicant: CANON ANELVA CORPORATIONInventors: Takashi Nakagawa, Naomu Kitano, Toru Tatsumi
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Publication number: 20100327407Abstract: A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches.Type: ApplicationFiled: November 9, 2009Publication date: December 30, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Chun Soo Kang
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Patent number: 7858472Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.Type: GrantFiled: March 22, 2007Date of Patent: December 28, 2010Assignee: SanDisk CorporationInventors: Jack H. Yuan, Eliyahou Harari, Yupin K. Fong, George Samachisa
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Patent number: 7851302Abstract: Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increased capacitance, or arranged in arrays. The plates of the capacitors are substantially the same dimensions as conductive features, such as conductive lines or vias, or are substantially the same dimensions as fill structures of the semiconductor device.Type: GrantFiled: February 4, 2005Date of Patent: December 14, 2010Assignee: Infineon Technologies AGInventor: Matthias Hierlemann
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Patent number: 7851303Abstract: A semiconductor device includes: a transistor having source and drain regions; first and second contact electrodes embedded in a first interlayer insulating film, and electrically connected to the source region and the drain region, respectively; a third electrode embedded in a second interlayer insulating film positioned in an upper layer of the first interlayer insulating film, and electrically connected to the first contact electrode; a wiring pattern embedded in a third interlayer insulating film positioned in an upper layer of the second interlayer insulating film, and electrically connected to the third contact electrode; and a fourth contact electrode embedded in at least the second and third interlayer insulating films, and electrically connected to the second contact electrode, wherein side surfaces of the wiring pattern along an extending direction of the wiring pattern coincide with side surfaces of the third contact electrode along an extending direction of the wiring pattern.Type: GrantFiled: July 6, 2009Date of Patent: December 14, 2010Assignee: Elpida Memory, Inc.Inventor: Noriaki Mikasa
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Publication number: 20100297820Abstract: An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed.Type: ApplicationFiled: August 4, 2010Publication date: November 25, 2010Inventors: Se-young LEE, IL-young YOON, Boung-ju LEE
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Publication number: 20100295110Abstract: A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body.Type: ApplicationFiled: May 17, 2010Publication date: November 25, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Yoshihiro TAKAISHI
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Patent number: 7838385Abstract: A method for manufacturing a reservoir capacitor of a semiconductor device reduces the resistance of the reservoir capacitor to secure reliability of the semiconductor device. The method comprises: forming a dummy pattern having a lattice structure over a transistor; forming a first interlayer insulating film over the resulting structure including the dummy pattern; etching the first interlayer insulating film to form a line-structured storage node contact region between the lattice structures; and filling a conductive layer in the line-structured storage node contact region to form a line-structured storage node contact.Type: GrantFiled: June 21, 2009Date of Patent: November 23, 2010Assignee: Hynix Semiconductor IncInventor: Won Ho Shin
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Publication number: 20100273303Abstract: A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays.Type: ApplicationFiled: July 1, 2010Publication date: October 28, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Gordon A. Haller, Sanh D. Tang
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Patent number: 7821052Abstract: A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.Type: GrantFiled: March 20, 2008Date of Patent: October 26, 2010Assignee: Micron Technology, Inc.Inventors: James E. Green, Terrence B. McDaniel