Abstract: A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

Abstract: Memory devices are provided. A memory device includes one or more adjacent memory cells on a substrate. A memory cell includes first dielectric layer on the substrate, floating gate, second dielectric layer, control gate layer, and first mask layer. The control gate layer has a first portion and a second portion thereon. A silicide layer is in the control gate layer and covers at least a sidewall of the second portion of the control gate layer. In a direction parallel to a surface of the substrate, the silicide layer has a size smaller than the first portion of the control gate layer or a size of the floating gate layer. A fourth dielectric layer is on the substrate and on the memory cell. The fourth dielectric layer contains an opening exposing a portion of the substrate between adjacent memory cells. A conductive structure is in the opening.

Abstract: The present invention relates to a substrate comprising an ion-implanted layer, for example a cation, wherein the ion implanted layer has a substantially uniform distribution of the implanted ions at a significantly greater depth than previously possible, to a well-defined and sharp boundary within the substrate. The invention further comprises said substrate wherein the substrate is a silicon based substrate, such as glass. The invention also comprises the use of said material as a waveguide and the use of said material in measurement devices.

Abstract: An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.

Abstract: The present disclosure provides a method for producing a semiconductor element that can lower the potential risk of malfunction. The production method of the disclosure is a method for producing a semiconductor element which includes providing a semiconductor element precursor, the precursor having a metal electrode layer formed on the surface of a gallium oxide-based single crystal semiconductor layer and a dopant doped in at least part of an exposed portion on the surface of the gallium oxide-based single crystal semiconductor layer where the metal electrode layer is not layered, and annealing treatment of the semiconductor element precursor whereby the dopant is diffused to a portion of the gallium oxide-based single crystal semiconductor layer that are overlapping with the metal electrode layer in the layering direction, to form a Schottky junction between the gallium oxide-based single crystal semiconductor layer and the metal electrode layer.

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

Abstract: A method can be used for fabricating first and second semiconductor regions separated by isolating trenches. A semiconductor substrate is covered with silicon nitride. The silicon nitride situated above the first region is doped by ion implantation. Trenches are etched through the silicon nitride and the doped silicon nitride is partially etching in an isotropic manner. The trenches are filled with an insulator to a level situated above that of the first region. The silicon nitride is removed resulting in the edges of the first region only being covered with an insulator annulus.

Abstract: There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material.

Abstract: The present disclosure provides an organic light-emitting display device that includes a substrate. A plurality of sub-pixels are arranged on the substrate, and each of the sub-pixels includes an organic light-emitting diode having a first electrode. A first bank has a plurality of first openings, and each of the first openings at least partially exposes a respective first electrode. A second bank has a plurality of second openings, and each of the second openings at least partially exposes one or more of the first electrodes. Each of a first set of the second openings exposes n first electrodes (n is a natural number equal to or greater than 1), and each of a second set of the second openings exposes m first electrodes (m is a natural number equal to or greater than 1), wherein n and m are different values.

Abstract: A semiconductor device includes a source region, a drain region, a SiGe channel region, an interfacial layer, a high-k dielectric layer and a gate electrode. The source region and the drain region are over a substrate. The SiGe channel region is laterally between the source region and the drain region. The interfacial layer forms a nitrogen-containing interface with the SiGe channel region. The high-k dielectric layer is over the interfacial layer. The gate electrode is over the high-k dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate and a pair of memory device structures. The semiconductor substrate includes a common source/drain region and a pair of individual source/drain regions, in which the common source/drain region is between the individual source/drain regions. The memory device structures each corresponds to one of the individual source/drain regions. Each memory device structure includes a trap storage structure, a control gate, a cap structure, and a word line. The trap storage structure is between the common source/drain region and the corresponding individual source/drain region. The control gate is over the trap storage structure. The cap structure is over the control gate, in which the cap structure comprises a nitride layer over the control gate and an oxide layer over the nitride layer. The word line is over the semiconductor substrate and laterally spaced from the control gate.

Abstract: A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

Abstract: A PNA temperature monitoring method comprises: Step 1, forming zero mark layer patterns on a tested silicon substrate; Step 2, forming a nitrogen-doped gate oxide by the following process: growing an oxide layer, doping the oxide layer with nitrogen, and carrying out PNA; Step 3, forming overlay layer patterns, and overlaying the overlay layer patterns and the corresponding zero mark layer patterns to form monitoring structures; and Step 4, measuring overlay values of the overlay layer patterns and the corresponding zero mark layer patterns of the monitoring structures, and regulating a PNA temperature according to the measured overlay values. By adoption of the method, the influence of the PNA temperature on a gate oxide in a two-dimensional plane can be monitored, and then the PNA temperature can be regulated to increase product yield.

Abstract: A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer. The implanted region remains after the un-implanted portions of the first layer are removed. An etching is then performed on a second layer underlying the first layer, wherein the implanted region is used as a portion of a first etching mask in the etching. The implanted region is removed. A metal mask is etched using the second layer to form a patterned mask. An inter-layer dielectric is then etched to form a contact opening, wherein the patterned mask is used as a second etching mask.

Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.

Abstract: According to one embodiment, a semiconductor storage device includes: a first stair portion which descends in a second direction that is a direction away from a pillar, and has a plurality of steps; and a third stair portion which is provided to face the first stair portion, and ascends in the second direction, and has a plurality of steps. A distance from an upper end of an uppermost step surface of the first stair portion to an upper end of a lowermost step surface of the first stair portion at a position identical to the upper end in the third direction is longer than a distance from an upper end of an uppermost step surface of the third stair portion to an upper end of a lowermost step surface of the third stair portion at a position identical to the upper end in the third direction.

Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.

Abstract: Provided is a complex biometric sensor. The complex biometric sensor includes a substrate including a light emitting region, a first light receiving region, and a second light receiving region, a light emitting part disposed adjacent to the substrate in the light emitting region, a color conversion layer disposed on the substrate in the light emitting region and vertically overlapping the light emitting part; a first light receiving layer disposed on the substrate in the first light receiving region, and a second light receiving layer disposed on the substrate in the second light receiving region. The light emitting part generates light of a first wavelength. The color conversion layer receives light of the first wavelength and emits the light of the first wavelength and light of the second wavelength. The first light receiving layer detects the light of the first wavelength. The second light receiving layer detects the light of the second wavelength.

Abstract: A radiation detection system may include a mobile device having a flash memory. The device may monitor various characteristics of the flash memory to determine when damage to the flash memory has occurred from radiation exposure. The device may associate damage to the flash memory with a radiation dose, and determine a level of radiation to which the memory, and thus the device, has been exposed. The device also may determine a length of time and locations where the radiation exposure has occurred. If the device determines that the level of radiation exposure exceeds a threshold associated with a safe level of radiation exposure for a human user, the device may generate an alert to the user.

Abstract: A contact structure and semiconductor device and method of forming the same are disclosed. The contact structure includes a first metal layer and a second metal layer. The first metal layer is disposed in a first dielectric layer. The second metal layer is disposed in a second dielectric layer and extended into the first dielectric layer to electrically connect the first metal layer, wherein the first metal layer and the second metal layer include different metals.

Abstract: In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.

Abstract: A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, a stack body including metal films and first insulating films alternately stacked on the semiconductor substrate and including a stepped end portion, conducting films respectively protruding from the metal films on all steps of the end portion, contact portions respectively provided above the conducting films, a second insulating film surrounding side surfaces of the contact portions, and a barrier metal film provided between the second insulating film and the contact portions and between the conducting films and the contact portions. The entire top surfaces of the conducting films are covered by the barrier metal film and the second insulating film.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First conductive layers are stacked in first direction and extends in second and third directions. The first conductive layers each includes a pair of first portions, and second and third portions. The first portions extend in second direction, is provided separately from each other in third direction and includes a metal. The second portion is provided between the first portions and includes silicon. The third portion is provided on at least one side of the second portion in second direction, extends in third direction, electrically connects the first portions and includes a metal. Memory pillars extend through the second portions in first direction. Contact plugs are respectively provided on the third portion of one of the first conductive layers.

Abstract: A vertical memory device includes a substrate including a first region including a cell array formed thereon and a second region surrounding the first region, the second region including a stair structure formed thereon, gate electrodes stacked on the substrate to be spaced apart from each other in a first direction vertical to an upper surface of the substrate, each of the gate electrodes extending in a second direction parallel to the upper surface of the substrate and including a pad at an end portion thereof in the second direction, a channel extending through the gate electrodes in the first direction on the first region of the substrate, and contact plugs formed on the second region, the contact plugs extending in the first direction to contact the pads of the gate electrodes respectively.

Abstract: In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.

Abstract: A semiconductor memory device includes a substrate; a stacked body on the substrate and including a first stacked body formed of stacked first electrode layers and a second stacked body on the first stacked body and including a second electrode layer; a hole passing through the stacked bodies in a first direction and having a first insulator, and a channel film between the first insulator and first electrode layers and between the first insulator and second electrode layer and having first and second portions facing each other, with the first insulator placed therebetween. A first memory between the first electrode layers and the first portion and a second memory between the first electrode layers and the second portion are insulated. A third memory between the second electrode layer and the first portion and a fourth memory between the second electrode layer and the second portion are connected.

Abstract: Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

Abstract: A reduced parasitic capacitance radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM. A PCM contact connects a PCM routing interconnect with a passive segment of the PCM, wherein the passive segment extends outward and is transverse to the heating element. A heating element contact connects a heating element routing interconnect with a terminal segment of the heating element. The heating element contact is situated cross-wise to the PCM contact. The heating element routing interconnect is situated at a different interlayer metal level relative to the PCM routing interconnect so as to achieve the reduced parasitic capacitance. The heating element routing interconnect can be situated above the heating element. Alternatively, the heating element routing interconnect can be situated below the heating element.

Abstract: A method for forming a silicon oxide film on a tungsten film includes performing a first process of arranging an object to be processed in a processing container kept under a reduced pressure, the object including a tungsten film and a natural oxide film being formed on a surface of the tungsten film, performing a second process of forming a silicon seed layer by adsorbing a silicon-containing gas to the tungsten film, subsequently performing a third process of annealing the object and forming the silicon oxide film by a reaction of the natural oxide film and the silicon seed layer and subsequently performing a fourth process of forming an ALD silicon oxide film by ALD using a silicon-containing gas and an oxygen active species.

Abstract: A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.

Abstract: A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.

Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

Abstract: Provided is a method of manufacturing a memory device including following steps. A substrate including an active region and a periphery region. A stack layer is formed on the substrate. A first trench is formed in the substrate and the stack layer in the active region. A first isolation structure is formed in the first trench. An ion implantation process is performed to form a doped first isolation structure. A first wet etching process is performed to remove a portion of the doped first isolation structure, so that a first recess is formed on the doped first isolation structure. A protection layer is formed on the substrate to at least cover sidewalls of the first recess. A second wet etching process is performed to remove the protection layer and another portion of the doped first isolation structure and deepen the first recess. A SICONI etching process is performed.

Abstract: Methods of forming the MRAM generally include forming an array of MTJ having sub-lithographic dimensions. The array can be formed by providing a substrate including a MTJ material stack including a reference ferromagnetic layer, a tunnel barrier layer, and a free ferromagnetic layer on an opposite side of the tunnel barrier layer. A hardmask layer is deposited onto the MTJ material stack. A first sidewall spacer is formed on the hardmask layer in a first direction. A second sidewall spacer is formed over the first sidewall in a second direction, wherein the first direction is orthogonal to the second direction. The second sidewall spacer intersects the first sidewall spacer. The first sidewall spacer is processed using the second sidewall spacer as mask to form a pattern of oxide pillars having sub-lithographic dimensions. The pattern of oxide pillars are transferred into the MTJ stack to form the array.

Abstract: A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.

Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.

Abstract: A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.