Abstract: A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.

Abstract: A method for fabricating a non-volatile memory device includes: providing a substrate which includes a cell region where a plurality of memory cells are to be formed and a peripheral circuit region where a plurality of peripheral circuit devices are to be formed; forming the memory cells that are stacked perpendicularly to the substrate of the cell region; and forming a first conductive layer for forming a gate electrode of a selection transistor over the memory cells while forming the first conductive layer in the peripheral circuit region simultaneously, wherein the first conductive layer of the peripheral circuit region functions as a resistor body of at least one peripheral circuit device of the peripheral circuit devices.

Abstract: A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns.

Abstract: A semiconductor device includes a semiconductor material and trenches extending into the semiconductor material from a first main surface of the semiconductor material to form mesas of semiconductor material between the trenches. The device also includes a field plate in the trenches, a body region in the mesas, a source region in contact with the body region in the mesas, and a gate electrode on the first main surface of the semiconductor material and defining a lateral channel region in each of the body regions under the gate electrodes. A drain region is at the opposing main surface of the semiconductor material. The gate electrodes adjacent opposing sides of the same field plate have the same alignment with respect to that field plate. The device can be a MOSFET or HEMT. Corresponding methods of manufacture are also provided.

Abstract: A vertical-type nonvolatile memory device includes a first vertical channel structure, and first and second stacked structure. The first vertical channel structure extends vertically on a substrate. The first stacked structure includes gate electrodes and first interlayer insulating layers. The gate layers and the first interlayer insulating layers are alternately and vertically stacked on each other. The first stacked structure is disposed on a first sidewall of the first vertical channel structure. The second stacked structure includes first sacrificial layers and second interlayer insulating layers. The first sacrificial layers and the second interlayer insulating layers are alternately and vertically stacked on each other. The second stacked structure is disposed on a second sidewall of the first vertical channel structure. The first sacrificial layers is formed of a polysilicon layer.

Abstract: What is provided is a field effect component including a semiconductor body, which extends in an edge zone from a rear side as far as a top side and which includes a semiconductor mesa, which extends in a vertical direction, which is perpendicular to the rear side and/or the top side. The semiconductor body in a vertical cross section further includes a drift region, which extends at least in the edge region as far as the top side and which is arranged partly in the semiconductor mesa, and a body region, which is arranged at least partly in the semiconductor mesa and which forms a pn junction with the drift region. The pn junction extends between two sidewalls of the semiconductor mesa.

Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.

Abstract: A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.

Abstract: In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.

Abstract: An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.

Abstract: A SiC semiconductor element includes: a SiC substrate which has a principal surface tilted with respect to a (0001) Si plane; a SiC layer arranged on the principal surface of the substrate; a trench arranged in the SiC layer and having a bottom, a sidewall, and an upper corner region located between the sidewall and the upper surface of the SiC layer; a gate insulating film arranged on at least a part of the sidewall and on at least a part of the upper corner region of the trench and on at least a part of the upper surface of the SiC layer; and a gate electrode arranged on the gate insulating film. The upper corner region has a different surface from the upper surface of the SiC layer and from a surface that defines the sidewall. The gate electrode contacts with both of a first portion of the gate insulating film located on the upper corner region and a second portion of the gate insulating film located on the sidewall.

Abstract: A three-dimensional charge trap semiconductor device is constructed with alternating insulating and gate layers stacked over a substrate. During the manufacturing process, a channel hole is formed in the stack and the gate layers are recessed from the channel hole. Using the recessed topography of the gate layers, a charge trap layer can be deposited on the sidewalls of the channel hole and etched, leaving individual discrete charge trap layer sections in each recess. Filling the channel hole with channel material effectively provides a three-dimensional semiconductor device having individual charge trap layer sections for each memory cell.

Abstract: A semiconductor device includes word lines and interlayer insulating layers alternately stacked over a substrate, vertical channel layers protruding from the substrate and passing through the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding each of the vertical channel layers, a charge trap layer surrounding the tunnel insulating layer, wherein first regions of the charge trap layer between the tunnel insulating layer and the word lines have a thickness smaller than a thickness of second regions thereof between the tunnel insulating layer and the interlayer insulating layers, and first charge blocking layer patterns surrounding the first regions of the charge trap layer.

Abstract: A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

Abstract: Collections of laterally crystallized semiconductor islands for use in thin film transistors and systems and methods for making same are described. A display device includes a plurality of thin film transistors (TFTs) on a substrate, such that the TFTs are spaced apart from each other and each include a channel region that has a crystalline microstructure and a direction along which a channel current flows. The channel region of each of the TFTs contains a crystallographic grain that spans the length of that channel region along its channel direction. Each crystallographic grain in the channel region of each of the TFTs is physically disconnected from and crystallographically uncorrelated with each crystallographic grain in the channel region of each adjacent TFT.

Abstract: A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film.

Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

Abstract: A silicon carbide semiconductor device has a first-conductivity-type semiconductor layer having a lower impurity concentration and formed on a first-conductivity-type semiconductor substrate, a second-conductivity-type semiconductor layer having a higher impurity concentration and selectively formed in the first-conductivity-type semiconductor layer, a second-conductivity-type base layer having a lower impurity concentration formed on a surface of the second-conductivity-type semiconductor layer, a first-conductivity-type source region selectively formed in a surface layer of the base layer, a first-conductivity-type well region formed to penetrate the base layer from a surface to the first-conductivity-type semiconductor layer, and a gate electrode formed via a gate insulation film on a surface of the base layer interposed between the source region and the well region.

Abstract: A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 ?m.

Abstract: A method of manufacturing a semiconductor device includes providing a doped layer containing a first dopant of a first conductivity type and forming a counter-doped zone in the doped layer in an edge area surrounding an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of the concentration of the first dopant.

Abstract: An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Abstract: A semiconductor device includes a vertical IGFET in a first area of a semiconductor body, the vertical IGFET having a drift zone between a body zone and a drain electrode, the drift zone having a vertical dopant profile of a first conductivity type being a superposition of a first dopant profile declining with increasing distance from the drain electrode and dominating the vertical dopant profile in a first zone next to the drain electrode and a second dopant profile being a broadened peak dopant profile and dominating the vertical dopant profile in a second zone next to the body zone.

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract: A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

Abstract: Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure.

Abstract: A super-junction trench MOSFET with a short termination area is disclosed, wherein the short termination area comprising a charge balance region and a channel stop region formed near a top surface of an epitaxial layer with a trenched termination contact penetrating therethrough.

Abstract: A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.

Abstract: A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

Abstract: A nonvolatile memory device includes a pipe insulation layer having a pipe channel hole, a pipe gate disposed over the pipe insulation layer, a pair of cell strings each having a columnar cell channel, and a pipe channel coupling the columnar cell channels and surrounding inner sidewalls and a bottom of the pipe channel hole.

Abstract: A semiconductor device includes a semiconductor substrate including a plurality of pillars, a gate electrode formed to surround a lower portion of the pillar and having a top surface lower than a top surface of the pillar, a salicide layer formed to cover the top surface of the pillar and surround an upper portion of the pillar, and an electrode formed to cover a top surface and a lateral surface of the salicide layer.

Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.

Abstract: A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

Abstract: A finned structure is fabricated using a bulk silicon substrate having a carbon doped epitaxial silicon layer. A pFET region of the structure includes silicon germanium fins. Such fins are formed by annealing the structure to mix a germanium containing layer with an adjoining crystalline silicon layer. The structure further includes an nFET region including silicon fins formed from the crystalline silicon layer. The germanium containing layer in the nFET region is removed to create a space beneath the crystalline silicon layer in the nFET region. An insulating material is provided within the space. The pFET and nFET regions are electrically isolated by a shallow trench isolation region.

Abstract: A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source region of a semiconductor channel, partially filling the trench with a protective material, removing at least a portion of the alternating second material layers to form recesses between the first material layers, forming a conductive material in the recesses to form control gate electrodes for a memory device, depositing an insulating material over the sidewalls and bottom of the trench, etching through the insulating material and the protective material to expose the semiconductor channel at the trench bottom while leaving the insulating material on the trench sidewalls, and filling the trench with a source line that electrically contacts the source region while the insulating material is between the source line and the control gate electrodes along the trench sidewalls.

Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

Abstract: According to one embodiment, a method includes forming a gate insulating layer structure covering first and second stacked layer structures, forming a first conductive layer on the gate insulating layer structure, forming a sacrifice layer on the first conductive layer, patterning the first conductive layer and the sacrifice layer with a line & space pattern, filling an insulating layer in spaces of the line & space pattern, the insulating layer having an etching characteristic different from the sacrifice layer, forming trenches in lines of the line & space pattern by removing the sacrifice layer selectively, the trenches exposing the first conductive layer between the first and second stacked layer structures, and forming a second conductive layer on the first conductive layer in the trenches.

Abstract: A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

Abstract: There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.

Abstract: A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.

Abstract: To provide a vertical SIC-MOSFET and IGBT capable of having low ON-resistance without destruction of gate oxide films or degradation of reliability even when a high voltage is applied, and a fabrication method thereof, a vertical mosfet has a semiconductor layer and a base layer joined instead of a well region 6 so as to include, as a joining portion, a point that is farthest and equidistant from centers of all the source regions facing each other and that is closest and equidistant from end portions farthest from the centers of the source regions in a planar view.

Abstract: A method of fabricating a memory device, such as a three-dimensional NAND string, includes forming a trench through a stack of alternating first and second material layers to expose a source region of a semiconductor channel, partially filling the trench with a protective material, removing at least a portion of the alternating second material layers to form recesses between the first material layers, forming a conductive material in the recesses to form control gate electrodes for a memory device, depositing an insulating material over the sidewalls and bottom of the trench, etching through the insulating material and the protective material to expose the semiconductor channel at the trench bottom while leaving the insulating material on the trench sidewalls, and filling the trench with a source line that electrically contacts the source region while the insulating material is between the source line and the control gate electrodes along the trench sidewalls.

Abstract: A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

Abstract: A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.