Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: A semiconductor device includes a silicon substrate having a protrusion, a gate insulating film formed over an upper surface of the protrusion of the silicon substrate, a gate electrode formed over the gate insulating film, a source/drain region formed in the silicon substrate on the side of the gate electrode, a first side wall formed over the side surface of the protrusion of the silicon substrate, the first side wall containing an insulating material, a second side wall formed over the first side wall, the second side wall having a bottom portion formed below the upper surface of the protrusion of the silicon substrate, the second side wall containing a material having a Young's modulus greater than that of the silicon substrate, and a stress film formed over the gate electrode and the second side wall.

Abstract: A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%.

Abstract: An LDMOS device may include at least one of a second conduction type buried layer and a first conduction type drain extension region. An LDMOS device may include a second conduction type drain extension region configured to be formed in a portion of the first conduction type drain extension region. The second conduction type drain extension region may include a gate pattern and a drain region. An LDMOS device may include a first conduction type body having surface contact with the second conduction type drain extension region and may include a source region. An LDMOS device may include a first guard ring formed around the second conduction type drain extension region. An LDMOS device may include a second guard ring configured to be formed around the first guard ring and configured to be connected to a different region of the second conduction type buried layer.

Abstract: A method of forming a field effect transistor (FET) device includes forming a gate structure over a substrate, the gate structure including a wide bottom portion and a narrow portion formed on top of the bottom portion; the wide bottom portion comprising a metal material and having a first width that corresponds substantially to a transistor channel length, and the narrow portion also including a metal material having a second width smaller than the first width.

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device which includes a MISFET, includes: forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting nitrogen equal to or more than 5.0e14 atoms/cm2 and equal to or less than 1.5e15 atoms/cm2 in the semiconductor substrate by tilted ion implantation in a direction from an outside to an inside with respect to side surfaces of the gate electrode; depositing a metal film including nickel on areas in which nitrogen atoms are implanted, the areas are in a semiconductor substrate on both sides of the gate electrode; and performing first heat processing of reacting the metal film and the semiconductor substrate and forming metal semiconductor compound layers, the shapes of the layers are controlled by the nitrogen profiles of the areas.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.

Abstract: An insulated-gate field-effect transistor (110, 114, or 122) is fabricated so that its gate dielectric layer (500, 566, or 700) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (502, 568, or 702) from significantly penetrating through the gate dielectric layer into the underlying channel zone (484, 554, or 684) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

Abstract: One method includes forming first trenches in a semiconducting substrate to define at least one fin for a FinFET device, forming a second trench in the substrate that is wider than the first trenches, forming a flowable oxide material in the first and second trenches, removing substantially all the flowable oxide material from the second trench and a portion of the flowable oxide material from the first trenches, forming a thermal oxide material in the first trenches above the flowable oxide material and in the second trench, removing substantially all of the thermal oxide material from the second trench and a portion of the thermal oxide material from the first trenches, depositing a silicon dioxide material in the first trenches above the thermal oxide material and in the second trench, removing the silicon dioxide material from the first trenches, and forming a gate structure around the fin of the device.

Abstract: A field effect nano-pillar transistor has a pillar shaped gate element incorporating a biomimitec portion that provides various advantages over prior art devices. The small size of the nano-pillar transistor allows for advantageous insertion into cellular membranes, and the biomimitec character of the gate element operates as an advantageous interface for sensing small amplitude voltages such as transmembrane cell potentials. The nano-pillar transistor can be used in various embodiments to stimulate cells, to measure cell response, or to perform a combination of both actions.

Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Abstract: A method for fabricating an integrated circuit device is disclosed. An exemplary method comprises performing a gate replacement process to form a gate structure, wherein the gate replacement process includes an annealing process; after the annealing process, removing portions of a dielectric material layer to form a contact opening, wherein a portion of the substrate is exposed; forming a silicide feature on the exposed portion of the substrate through the contact opening; and filling the contact opening to form a contact to the exposed portion of the substrate.

Abstract: A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions.

Abstract: A semiconductor structure includes a gate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided.

Abstract: A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided.

Abstract: A semiconductor device cell is disclosed. The semiconductor device cell includes a transistor gate having a gating surface and a contacting surface and a source region contacted by a source contact. The semiconductor device cell further includes a drain region contacted by a drain contact, wherein the drain contact is not situated opposite the source contact with respect to the gating surface of the transistor gate. Additional semiconductor device cells in which the gate contact is closer to the source contact than to the drain contact are disclosed.

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract: Methods and apparatus for selectively improving integrated circuit performance are provided. In an example, a method is provided that includes defining a critical portion of an integrated circuit layout that determines the speed of an integrated circuit, identifying at least a part of the critical portion that includes at least one of a halo, lightly doped drain (LDD), and source drain extension (SDE) implant region, and performing a speed push flow process to increase performance of the part of the critical portion that includes the at least one of the halo, the LDD, and the SDE implant region. The resultant integrated circuit can be integrated with a mobile device.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a gate electrode on a channel region in a silicon substrate via a gate insulation film; forming a source region and a drain region in the silicon substrate so as to sandwich the channel region along a channel direction by injecting desired impurities to the silicon substrate; forming amorphous regions containing the impurities on surfaces of the source region and the drain region by amorphousizing the surfaces of the source region and the drain region; forming nickel films on the amorphous regions; and forming crystal layers containing the activated impurities and forming nickel silicide films on the crystal layers at low temperature by radiating microwaves to the amorphous regions and the nickel films.

Abstract: A method of forming a semiconductor structure, including forming a gate structure on a substrate; performing a first angled implantation on a first side of the gate structure to form a first doped region in the substrate, the first doped region partially extends within a channel of the gate structure and the gate structure blocks the first angled implantation from affecting the substrate on a second side of the gate structure; forming sidewall spacers on sidewalls of the gate; and forming a second doped region in the substrate on the second side of the gate, spaced apart from the channel.

Abstract: A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor.

Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Abstract: A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

Abstract: Provided is a semiconductor device that includes a vertical MOS transistor having a trench structure capable of enhancing a driving performance of the vertical MOS transistor. A thick oxide film is formed next to a gate electrode led out of a trench of the vertical MOS transistor having the trench structure, and is removed to form a stepped portion which has a face lower than a surrounding plane and has slopes as well. This makes it possible to form a heavily doped diffusion layer right under the gate electrode through ion implantation for forming a heavily doped source diffusion layer, thereby solving a problem of no current flow in a part of a driver element and enhancing the driving performance of the vertical MOS transistor.

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract: A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions.

Abstract: A structure includes a tensilely strained nFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed nFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained pFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed pFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer.

Abstract: A method of producing a transistor includes providing a substrate including a first electrically conductive material layer. A resist material layer is deposited over the first electrically conductive material layer. The resist material layer is patterned to expose a portion of the first electrically conductive material layer. Some of the first electrically conductive material layer is removed to create a reentrant profile in the first electrically conductive material layer and expose a portion of the substrate. The first electrically conductive material layer and at least a portion of the substrate are conformally coated with an electrically insulating material layer.

Abstract: In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.

Abstract: One illustrative method disclosed herein includes forming a plurality of layers of material above a semiconducting substrate, wherein the plurality of layers of material will comprise a gate structure for a transistor, performing a fluorine ion implantation process to implant fluorine ions into at least one of the plurality of layers of material, performing at least one ion implantation process to implant one of a P-type dopant material or an N-type dopant material into the substrate to form source/drain regions for the transistor, and performing an anneal process after the fluorine ion implantation process and the at least one ion implantation process have been performed.

Abstract: The field effect device comprises a sacrificial gate electrode having side walls covered by lateral spacers formed on a semiconductor material film. The source/drain electrodes are formed in the semiconductor material film and are arranged on each side of the gate electrode. A diffusion barrier element is implanted through the void left by the sacrificial gate so as to form a modified diffusion area underneath the lateral spacers. The modified diffusion area is an area where the mobility of the doping impurities is reduced compared with the source/drain electrodes.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.

Abstract: A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

Abstract: A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.

Abstract: A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon.

Abstract: An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench.

Abstract: Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm?2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Abstract: Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.

Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.

Abstract: A method for fabricating a field effect transistor device includes forming a gate stack on a substrate, forming a spacer on the substrate, adjacent to the gate stack, forming a first portion of an active region on the substrate, the first portion of the active region having a first facet surface adjacent to the gate stack, forming a second portion of the active region on a portion of the first portion of the active region, the second portion of the active region having a second facet surface adjacent to the gate stack, the first facet surface and the second facet surface partially defining a cavity adjacent to the gate stack.

Abstract: A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.

Abstract: A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate.

Abstract: A manufacturing method for semiconductor structures includes providing a substrate having a first region and a second region defined thereon, forming a plurality of first patterns in the first region and at least a second pattern in the second region, forming a plurality of first spacers respectively on sidewalls of the first patterns and at least a second spacer on a sidewall of the second pattern, forming a patterned protecting layer in the second region, removing the first patterns from the first region to form a plurality of first masking patterns in the first region and at least a second masking pattern in the second region, and transferring the first masking patterns and the second masking pattern to the substrate.

Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity is formed. Thereafter an ion implant step through the cavity results in a localized increase in well-doping directly beneath the cavity. The implant is activated by a microsecond annealing which causes minimum dopant diffusion. Within the cavity a recess into the well area is formed in which an active region is formed using an un-doped or lightly doped epitaxial layer. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries. In one embodiment of the invention a cap of poly-silicon or amorphous silicon is added on top of the metal gate.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.