Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.

Abstract: A new method for forming ultra-shallow junctions for PMOSFET while reducing short channel effects is described. A semiconductor substrate wafer is provided wherein there is at least one NMOS active area and at least one PMOS active area. Gate electrodes are formed in both the NMOS and PMOS areas. N-type source/drain extensions are implanted into the NMOS area. The wafer is annealed whereby the n-type source/drain extensions are driven in. Thereafter, p-type source/drain extensions are implanted in the PMOS area wherein the p-type source/drain extensions are not subjected to an annealing step. Spacers are formed on sidewalls of the NMOS and PMOS gate electrodes. Source/drain regions are implanted into the NMOS and PMOS areas wherein the source/drain regions are self-aligned to the spacers to complete formation of an integrated circuit device.

Abstract: For fabricating a PMOS (P-channel Metal Oxide Semiconductor) field effect transistor on a semiconductor substrate, a layer of gate dielectric material containing nitrogen is deposited on the semiconductor substrate, and a layer of gate electrode material is deposited on the layer of gate dielectric material. A first P-type dopant, such as boron for example, is implanted into a first region of the layer of gate electrode material disposed over a first active device area of the semiconductor substrate. The first region of the layer of gate electrode material is patterned to form a PMOS gate electrode. The layer of gate dielectric material is patterned to form a PMOS gate dielectric disposed under the PMOS gate electrode.

Abstract: A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Abstract: The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, forming a recess in said substrate proximate said gate stack, and performing an implantation process to implant dopant atoms into the bottom surface of the recess. The method further comprises forming a layer of epitaxial silicon in the recess, performing a second ion implantation process to form a doped region in at least the epitaxial silicon in the recess, and performing an anneal process to activate the implanted dopant atoms.

Abstract: A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.

Abstract: A simplified and cost reduced process for fabricating a field-effect transistor semiconductor device (104) using laser radiation is disclosed. The process includes the step of forming removable first dielectric spacers (116R) on the sides (120a, 120b) of the gate (120). Dopants are implanted into the substrate (100) and the substrate is annealed to form an active deep source (108) and an active deep drain (110). The sidewall spacers are removed, and then a blanket pre-amorphization implant is performed to form source and drain amorphized regions (200a, 200b) that include respective extension regions (118a, 118b) that extend up to the gate. A layer of material (210 is deposited over the source and drain extensions, the layer being opaque to a select wavelength of laser radiation (220). The layer is then irradiated with laser radiation of the select wavelength so as to selectively melt the amorphized source and drain extensions, but not the underlying substrate.

Abstract: A method for producing MOS type transistors with deep source/drain junctions and thin, silicided contacts with desireable interfacial and electrical properties. The devices are produced by a method that involves pre-amorphization of the gate, source and drain regions by ion-implantation, the formation of a metal layer, ion implantation through the metal layer, the formation of a capping layer and a subsequent laser anneal.

Abstract: The present invention provides a method of forming a Metal Oxide Semiconductor (MOS) transistor on a substrate of a semiconductor wafer. A gate of the MOS transistor is formed on the substrate. A source and a drain of the MOS transistor are then formed in the substrate. An ion implantation process is performed to form a first doped region, a second doped region and a third doped region. The first doped region is positioned under the gate and overlaps with the channel of the MOS transistor. The second doped region is positioned in a predetermined portion of the substrate under the source. The third doped region is positioned in a predetermined portion of the substrate under the drain. The first doped region, the second doped region, the third doped region, the source, and the drain are all of the same type of semiconductor.

Abstract: There is disclosed a method of manufacturing a transistor in a semiconductor device by which, when forming an elevated channel using an epitaxy technology for further expanding the applied region of a buried channel PMOS transistor, indium ions having the high amount of atoms and a low diffusion speed after growth of an epitaxial layer are implanted to distribute them into a boron epitaxial layer and a lower portion. Thus, it can obtain a desired threshold voltage Vt in a device and can improve degradation in a short channel.

Abstract: A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, a 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, a 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, a 4th step of forming a P-well region inside the 1st gate insulation film partially removed region before forming a 2nd N-channel region containing indium on this P-well region, and a 5th step of removing the 2nd resist mask before forming a 2nd gat

Abstract: A method of fabricating an integrated circuit (10, 51, 61, 71, 81, 91) includes forming on the upper surface (13) of a substrate (12) a part (18) which has thereon a side surface (19). A plurality of sidewalls (22, 27 and 83-84) are then formed in succession, outwardly from the side surface. A plurality of successive implants (21, 26, 31, 73-74, 87-88, 93-94) are introduced into the substrate, where a respective different subset of the sidewalls is present when each implant is created. The formation of sidewalls and implants may be carried out in an alternating manner, followed by removal of the sidewalls. Alternatively, removal of the sidewalls and formation of the implants may be carried out in an alternating manner. The width of each sidewall may be sublithographic, and the cumulative width of all sidewalls may be sublithographic.

Abstract: An integrated circuit (10, 60, 110, 210) is fabricated according to a method which includes the steps of providing a structure (12, 112, 212) having a top surface (13, 113, 213), and forming spaced first and second sections (16-18, 67-69, 72-73, 126-127, 231-232) on the top surface. The first and second sections have side surfaces (21-26, 81-88, 131-134, 241-244) thereon. A respective sidewall (31-36, 91-98, 141-144, 251-254) with a sublithographic thickness is formed on each side surface. Then, a further section (42A-42D, 101A-101D, 152, 268) is formed in the region between the sidewalls on the first and second sections, for example by introducing a selected material between those sidewalls, and by then removing any portion of the selected material which is higher than the upper ends of the sidewalls.

Abstract: A method for forming a gate electrode for a MOS type transistor including formation of an insulating layer on a portion of a semiconductor substrate is not used for the gate electrode. A spacer is formed on the sides of the insulating layer and a gate oxide and gate electrode layers are stacked on the portion of the semiconductor substrate that is used for forming the gate. Source/drain regions are formed by implanting ions after removing the insulating layer. A plug poly is formed in the opening portion left by the removal of the insulating layer. The spacer is then removed to allow LDD ion implantation true openings left by removal of the spacer. Prior to the LDD ion implantation, however, rapid thermal annealing is performed to activate the source/drain regions and the gate electrode, thereby effecting formation of a short effective channel of the gate, which is advantageous in high density integrated circuits.

Abstract: A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

Abstract: A FET with reduced reverse short channel effects is described, as well as a method to make said FET. Germanium is implanted throughout a semiconductor substrate at an intensity and dose such that a peak ion concentration is created below the source and drain of the FET. The germanium can be implanted prior to gate and source and drain formation, and reduces the reverse short channel effect normally seen in FETs. The short channel effect normally occurring in FETs is not negatively impacted by the germanium implant.

Abstract: A process for fabricating a semiconductor device including MOS transistors of low breakdown voltage type and of high breakdown voltage type provided on a semiconductor substrate, the MOS transistor of high breakdown voltage type being operative at a higher voltage than the MOS transistor of low breakdown voltage type and having drift diffusion regions, the process comprises the steps of: forming a LOCOS oxide film on the semiconductor substrate; and performing ion implantation with the use of a single mask having openings respectively defining on the substrate a first region for formation of a first conductivity type MOS transistor of low breakdown voltage type, a second region in which the LOCOS oxide film is formed for isolation of a first conductivity type MOS transistor of high breakdown voltage type, and a third region for formation of a drift diffusion region of a second conductivity type MOS transistor of high breakdown voltage type, so that the first and third regions each have at least two concentrat

Abstract: A method of reducing the boron-penetrating effect in a CMOS transistor provides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, the boron ion (B+) is doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to from a polysilicon gate. The gate photoresist is used as a mask to dope the boron-fluorine ion (BF2+) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain on the silicon substrate.

Abstract: The present invention provides a method of using organic polymer as a covering layer for a device lightly doped drain (LDD) structure, wherein a photo resist is covered by organic polymer, and ion implantation of different energies and kinds are performed to the same region of different line widths, thereby achieving the effect of LDD. Additionally, the covering layer of organic polymer is removed by means of simple and easy oxygen plasma etch so as not to increase the complexity of fabrication process. The complex fabrication process of a device LDD structure in the prior art is thus greatly improved.

Abstract: A method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions is described. A gate structure having a gate insulating layer, a first conductive layer and a first dielectric layer is formed on a substrate. A thermal oxide layer is formed on the substrate and on sidewalls of the first conductive layer. Sidewall spacers are formed on sidewalls of the gate structure. The thermal oxide layer uncovered by the sidewall spacers is removed. The substrate is isotropically etched to form recessed regions on the substrate in regions uncovered by the gate structure and the sidewall spacers. A first metal layer is formed on the substrate after the first dielectric layer is removed. A source/drain/gate implantation is performed to the substrate, thereby forming source/drain regions under the recessed regions.

Abstract: A method of manufacturing a semiconductor device having transistors with lightly doped diffusion regions (LDD) and self-aligned contacts to a reduced inter-gate spaces is disclosed. According to one embodiment, a method may include forming a gate and top insulating layer (004 and 005) on a semiconductor substrate (001). LDD regions (007) may be formed in a first area (Rpc) and source/drain regions (011) may be formed in a second area (Rmc). An etch stop layer (012), which may comprise silicon nitride, can then be formed. Sidewalls (006), which may comprise silicon dioxide, may be formed on gate layer (004) in a first area (Rpc), while inter-gate spaces in the second area (Rmc) may be filled with a sidewall layer. Source/drain regions (008) may then be formed in a first area (Rpc). A heat treatment can be applied that can restore etch resistance properties of the etch stop layer (012) which can be degraded when source/drain regions (008) are formed.

Abstract: A transistor structure having dimensions below about 100 nm is provided. The transistor structure comprises a substrate with a first polarity. The substrate includes a shallow halo implant having the first polarity defined at a first depth within the substrate. The substrate also has a deep halo implant which is the same polarity as the substrate and is defined to a second depth deeper than the first depth of the shallow halo implant. The shallow halo implant and the deep halo implant allow a peak concentration of substrate impurities at a level below the gate such that the resistance of the transistor is minimized along with the threshold voltage, short channel effects and leakage current in the transistor.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. A first dielectric layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, the first silicon layer, and the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and the first dielectric layer is removed. A second silicon layer is formed on the semiconductor substrate and on the first silicon layer. Another doping step is performed to dope the second silicon layer. A series of process is then performed to form a metal silicide layer on the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A semiconductor device includes a semiconductor layer used as a substrate formed on an insulating film, a plurality of MOS transistors arranged on the semiconductor layer and each having a gate, a source, and a drain, a pair of MOS transistors of the plurality of MOS transistors constituting a detection circuit for detecting magnitudes of potentials applied to the gates as a difference between conductances of the pair of transistors, and a diffusion layer region of the same conductivity type as that of the semiconductor layer, arranged on one of portions of the sources and drains of the pair of MOS transistors constituting the detection circuit, for connecting portions serving as the substrates of the pair of MOS transistors to each other.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: A method of manufacturing a semiconductor device having shallow p-n junctions and silicide regions, capable of meeting both requirements of a high annealing temperature and a low annealing temperature. A lamination of two films made of materials having different etching characteristics is formed on the surface of a silicon substrate, covering an insulated gate electrode structure. The upper film is anisotropically etched to form side wall spacers. Impurity ions are implanted into a surface layer of the silicon substrate and sufficiently activated to a first level. The lower film is removed by using as a mask the side wall spacers, and a metal film capable of being silicided is deposited to perform a first silicidation reaction. The insulated gate electrode is exposed and impurity ions are implanted shallowly in the surface layer of the silicon substrate.

Abstract: A shielding layer 23 is selectively formed on a single crystal silicon layer, an active area 25 is formed in the single crystal silicon layer by using the shielding layer 23 as a mask and an impurity layer 26 is formed at the edges at the sides of the active area 25 by using the shielding layer 23 as a mask and implanting an impurity diagonally from above. As a result, since an impurity layer can be formed by implanting ions of the impurity at the edges at the sides of the active area even when the size of the active area is reduced to the absolute limit, the occurrence of the parasitic transistor phenomenon or the edge transistor phenomenon along the edges at the sides of the active area can be prevented.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: This invention provides a method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM. The DRAM on a predetermined area of a semiconductor wafer comprises memory cells arranged in a matrix format. Each memory cell comprises an N-type MOS transistor which comprises gate electrode layer, two spacers on two opposite side walls of the gate electrode layer, two lightly doped layers on the surface of the substrate below the two spacers, and two heavily doped layers act as the source and drain. This method uses two ion implantation processes to implant boron ions first into a region below one of the two lightly doped layers in a specified direction to form a first pocket implantation region, and then into a region below the other lightly doped layer in the opposite direction to form a second pocket implantation region so as to complete the pocket implantation.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Abstract: A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.

Abstract: A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

Abstract: A heterojunction transistor with high mobility carriers in the channel region includes a source region and a drain region formed in a semiconductor body with the source region and the drain region comprising doped semiconductor alloys separated from the substrate by heterojunctions. A channel region is provided between the source region and the drain region comprising an undoped layer of an alloy of the semiconductor material and a deposited layer of material of the semiconductor body overlying the undoped layer. A gate electrode is formed on a gate oxide over the channel region. In fabricating the high mobility heterojunction transistor, the spaced source and drain regions are formed in the substrate by implanting dopant of conductivity type opposite to the substrate and a material in the alloy and then annealing the structure to form the alloy of the semiconductor material under the undoped layer.

Abstract: There is provided a method for fabricating a semiconductor device comprising a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed within the semiconductor layer, a drain region of the second conductivity type formed within the semiconductor layer, a channel region provided between the source and drain regions, a gate electrode formed over the channel region, and a buried region of the first conductivity type having at least a part included in the drain region. The method for fabricating the semiconductor device comprises the steps of doping the semiconductor layer with a dopant of the second conductivity type for the drain region and doping the semiconductor layer with a dopant of the first conductivity type for the buried region.

Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.

Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.

Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Abstract: Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.

Abstract: Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.

Abstract: A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region.

Abstract: The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

Abstract: A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region which is in contact with n-type region and covers the periphery thereof. The n+ drain diffusion region, n-type region and p+ impurity region extend to region located immediately under the floating gate electrode. Thereby, the nonvolatile semiconductor memory device has a structure which can promote injection of high energy electrons along a gate electrode direction.

Abstract: One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.

Abstract: In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first active region of a first conductivity type in the semiconductor substrate; a first gate oxide film formed on the first active region and having increased thickness at the edge regions thereof than in the central region thereof in the direction of current flow; and a first electrode formed on the first gate oxide film and doped at a relatively low concentration with an impurity of a second conductivity type which is opposite to the first conductivity type; and the MOS transistor driven at the relatively low voltage comprises: a second active region of a first conductivity type in the semiconductor substrate; a second gate oxide film formed on the second active region; and a second electrode formed on the second gate oxide film and doped at a relativ

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor.

Abstract: A fuse link redundancy structure to implement redundant circuits within an integrated circuit has an insulating layer over a conductive layer of the fuse link is sufficiently thin and transparent to allow destruction of the conductive layer by an intense laser light. The redundancy structure has a fusible link formed of a layer of a conductive material deposited upon an insulating layer such as field oxide on the semiconductor substrate and connected between the redundant circuits and other circuits present on the integrated circuit. The layer of conductive material is either formed of a metal such as Aluminum or Tungsten, a heavily doped polycrystalline silicon, or an alloy of a metal such as Tungsten and a heavily doped polycrystalline silicon. A hard mask layer is placed upon the layer of conductive material during transistor processing to protect the layer of conductive material during formation of self-aligned sources and drains of transistors of the integrated circuit.

Abstract: A semiconductor device includes an interlevel insulating film, a contact plug, a barrier film, a first electrode, a capacitor insulating file, and a second electrode. The interlevel insulating film is formed on a semiconductor substrate. The contact plug extends through the interlevel insulating film and is formed from a conductive material. The barrier film is formed from a tungsten-based material on the upper surface of the contact plug. The first electrode is connected to the contact plug via the barrier film and formed from a metal material on the interlevel insulating film. The capacitor insulating film is formed from an insulating metal oxide on the first electrode. The second electrode is insulated by the capacitor insulating film and formed on the surface of the first electrode.

Abstract: For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second dopant is then implanted into the preamorphization region to have a dopant profile along a depth of the preamorphization region, and the dopant profile has a dopant peak within the preamorphization region. A RTA (Rapid Thermal Anneal) is performed to recrystallize a portion of the preamorphization region from an interface between the preamorphization region and the semiconductor substrate to below the dopant peak. A LTP (Laser Thermal Process) is then performed to recrystallize a remaining portion of the preamorphization region that has not been recrystallized during the RTA (Rapid Thermal Anneal) to activate a substantial portion of the second dopant in the preamorphization region.

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.