Abstract: A field effect transistor includes a drain region (12) having a first portion (18) and a second portion (20), with the second portion being more lightly doped than the first portion. A channel region (14) is adjacent to the second portion and a drain electrode (24) overlies the drain region. A gate electrode (16) overlies the channel region. A shield structure (30) overlies the drain region and has a first section (32) at a first distance (33) from a semiconductor substrate (10) and a second section (34) at a second distance (35) from the semiconductor substrate, the second distance being greater than the first distance. In a particular embodiment the FET includes a shield structure wherein the first and second sections are physically separate. The location of these shield sections may be varied within the FET, and the potential of each section may be independently controlled.

Abstract: A semiconductor process and structure (32) uses a disposable sidewall spacer (42) associated with lightly doped drain (LDD) transistors. The disposable sidewall spacers are efficiently removed by a gaseous fluorine ambient. Either molecular or atomic fluorine gas is used to remove a silicon germanium sidewall spacer with high selectivity to exposed insulating layers. This etch process is also isotropic. An additional benefit of using a gaseous fluorine ambient is incorporation of fluorine in isolation regions (48) surrounding the transistors, thereby reducing the dielectric constant. Improved insulating properties of the isolations regions can allow increased integration.

Abstract: According to one illustrative embodiment of the present invention, a method of forming a field effect transistor includes the formation of a doped high-k dielectric layer above a substrate including a gate electrode formed over an active region and separated therefrom by a gate insulation layer. A heat treatment is carried out with the substrate to diffuse dopants from the high-k dielectric layer into the active region to form extension regions. The high-k dielectric layer is patterned to form sidewall spacers at sidewalls of the gate electrode and an implantation process is carried out with the sidewall spacers as implantation mask to form source and drain regions.

Abstract: A semiconductor device is disclosed. The device includes a semiconductor region and P-type and N-type diffusion layers formed in the semiconductor region. The semiconductor region includes a germanium low-concentration region containing germanium of low concentration and a germanium high-concentration region containing germanium of high concentration. A boundary region between the P-type and N-type diffusion layers lies in the germanium high-concentration region. A silicide film is formed to extend from the P-type diffusion layer over to the boundary region and the N-type diffusion layer.

Abstract: A lateral CMOS-compatible RF-DMOS transistor (RFLDMOST) with low ‘on’ resistance, characterised in that disposed in the region of the drift space (20) which is between the highly doped drain region (5) and the control gate (9) and above the low doped drain region LDDR (22, 26) of the transistor is a doping zone (24) which is shallow in comparison with the penetration depth of the source/drain region (3, 5), of inverted conductivity type to the LDDR (22, 26) (hereinafter referred to as the inversion zone) which has a surface area-related nett doping which is lower than the nett doping of the LDDR (22, 26) and does not exceed a nett doping of 8E12 At/cm2.

Abstract: In one embodiment of the invention, source and drain regions are formed as well as source and drain contact regions. Thereafter source and drain extension regions are formed. In another embodiment, elevated source and drain regions are formed as well as source and drain extension regions. Thereafter source and drain contact regions are formed at a temperature up to about 600° C. and an annealing time of up to about one minute.

Abstract: In a semiconductor device for protecting an electrostatic discharge and a method of fabricating the same, a gate electrode is disposed on a semiconductor substrate of first conductivity type, and a heavily doped region and a vertical lightly doped region surround the heavily doped region. The heavily doped region and vertical lightly doped region have a second conductivity type and are disposed in the semiconductor substrate on both sides of the gate electrode. The vertical lightly doped region has a lower impurity concentration and a larger depth than the heavily doped regions. A horizontal lightly doped region, which has a lower impurity concentration than the vertical lightly doped region, is further disposed in an upper side of the vertical lightly doped region.

Abstract: A method of forming a stable junction on a microelectronic structure on a semiconductor wafer having a silicon surface layer on a substrate includes the following steps: implanting dopant ions into the surface layer; cleaning and oxidizing the surface layer, and twice annealing the wafer to recover a damaged silicon crystal structure of the surface layer resulting from the low energy ion implantation. The first annealing process uses a temperature range of 800° C. to 1200° C. for a duration from about a fraction of a second to less than about 1000 seconds, with a ramp-up rate of about 50° C./second to about 1000° C./second. The second annealing process uses a temperature range of 400° C. to 650° C. for a time period of from about 1 second to about 10 hours, and more preferably, from about 60 seconds to about 1 hour. Both annealing processes include cooling processes.

Abstract: A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region.

Abstract: An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

Abstract: LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.

Abstract: A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

Abstract: A method and system can compensate for anneal non-uniformities by implanting dopant in a pattern to provide higher dopant concentrations where the anneal non-uniformities result in lower active dopant concentrations. A pattern for the anneal non-uniformities may be determined by annealing a wafer having a uniform dopant distribution and measuring properties of the wafer after annealing, e.g., by obtaining a sheet resistance map of the wafer. In one embodiment, the non-uniformities may be measured by measuring temperature variations during annealing.

Abstract: A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A high voltage MOS transistor with a gate extension that has a reduced electric field in the drain region near the gate is provided. The high voltage MOS transistor includes a first and second gate layers, and a dielectric layer between the gate layers. The first and second gate layers are electrically coupled togther and form the gate of the transistor. The second gate layer extends over the drain of the transistor above the dielectric and gate oxide layers to form the gate extension. The gate extension reduces the peak electric field in the drain by providing a wide area for the voltage to drop between the drain and the gate of the transistor. The dielectric layer also reduces the peak electric field in the drain near the gate by providing insulation between the gate and the drain. A lower electric field in the drain reduces the impact generation rate of carriers.

Abstract: The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises exposing a portion (125) of an n-type substrate (105) to an arsenic dimer (130). The method also includes forming a p-type lightly doped drain (LDD) region (145) within the portion of the n-type substrate (125). Other embodiments advantageously incorporate the method into methods for making PMOS devices.

Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within a trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.

Abstract: A high voltage MOS transistor is provided that is compatible with low-voltage, sub-micron CMOS and BiCMOS processes. The high voltage transistor of the present invention has dopants that are implanted into the substrate prior to formation of the epitaxial layer. The implanted dopants diffuse into the epitaxial layer from the substrate during the formation of the epitaxial layer and subsequent heating steps. The implanted dopants increase the doping concentration in a lower portion of the epitaxial layer. The implanted dopants may diffuse father into the epitaxial layer than dopants in the buried layer forming an up-retro well that prevents vertical punch-through at high operating voltages for thin epitaxial layers. In addition, the doping concentration below the gate may be light so that the threshold voltage of the transistor is low.

Abstract: A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.

Abstract: In a high voltage device and a method for fabricating the same, a semiconductor substrate includes first, second, and third regions, the second and third regions neighboring the first region with boundaries. The first and second drift regions are respectively formed in the second and third regions at a first depth. Insulating films are formed at a second depth less than the first depth, having a predetermined width respectively based on the boundary between the first and second regions and the boundary between the first and third regions. A channel ion injection region is formed with a variable depth along a surface of the semiconductor substrate belonging to the first region and the insulating films. A gate insulating film is formed on the channel ion injection region, partially overlapping the insulating films at both sides around the channel ion injection region.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: A method is provided for maximizing activation of a gate electrode while preventing source and drain regions from being excessively doped. The gate electrode is partially doped when exposed the source/drain implantation step. Then, the gate electrode is fully doped by the selective implantation step while the source/drain regions are blocked. Separate annealing steps are provided subsequent to the gate doping step and the source and drain implantation step.

Abstract: A semiconductor device is a P-channel type MOS field effect transistor that comprises; a semiconductor substrate, a gate oxide film positioned on the semiconductor substrate, a gate electrode positioned on the gate oxide film; and two P+ source and drain diffusion areas, each of which has a P− offset area, that are formed in an n-well region of the semiconductor substrate. At least one of the gate electrode, the gate oxide film and the offset areas contains fluorine.

Abstract: The present invention allows the manufacturing of field effect transistors with reduced thermal budget. A first amorphized region and a second amorphized region are formed in a substrate adjacent to the gate electrode by implanting ions of a non-doping element, the presence of which does not significantly alter the conductive properties of the substrate. The formation of the amorphized regions may be performed before or after the formation of a source region, a drain region, an extended source region and an extended drain region. The substrate is annealed to achieve solid phase epitaxial regrowth of the amorphized regions and to activate dopants in the source region, the drain region, the extended source region and the extended drain region.

Abstract: A MOS field effect transistor for reducing the resistance between a source and a drain includes a gate insulation layer and a gate electrode sequentially formed on a semiconductor substrate includes deep source/drain regions formed in upper portions of the semiconductor substrate at both sides of the gate electrode. Source/drain extension regions are formed in upper portions of the semiconductor substrate extending from the deep source/drain regions toward a channel region below the gate electrode to be thinner than the deep source/drain regions. A first silicide layer having a first thickness is formed on the surface of each of the deep source/drain regions. A second silicide layer having a second thickness thinner than the first thickness of the first silicide layer is formed to extend from the first silicide layer in a predetermined upper portion of each of the source/drain extension regions.

Abstract: An active transistor area with a retrograde doping area on a substrate in bipolar technology is produced by a method including the following steps: providing a substrate; producing a buried doping area in the substrate; producing an epitaxy layer; producing a retrograde doping profile in said epitaxy layer, so that the highly doped area of the buried doping area is enlarged in the direction of the substrate surface.

Abstract: A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.

Abstract: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is fabricated by forming gate spacers on both sidewalls of a gate pattern in a semiconductor substrate including first and second regions. Then, a first impurity region is formed in the semiconductor substrate at the first region, and the gate spacer exposed at the first region is removed. A second impurity region is formed in the semiconductor substrate at the first region. A third impurity region is formed at the semiconductor substrate in the second region, and the gate spacer exposed at the second region is removed. A fourth impurity region is formed in the semiconductor substrate at the second region. The first and third impurity regions are formed deeper than the second and fourth impurity regions.

Abstract: A method of fabricating a thin film transistor (TFT) with self-aligned structure. A substrate is provided, with a semiconductor layer and gate insulation layer formed in sequence thereon, followed by formation of a conductive layer on the gate insulation layer, and definition of the conductive layer to form a gate conductive layer and a dummy conductive layer. The dummy conductive layer is on both sides of the gate conductive layer and provided with a gap therebetween. A first ion implantation is performed via the gap to form a lightly doped region on the semiconductor layer thereunder, and a sacrificial layer is formed to fill the gap. The dummy conductive layer is removed. The gate conductive layer and the remaining sacrificial layer are used as a mask. Finally, a second ion implantation is performed to form a heavily doped source/drain region on the semiconductor layer.

Abstract: In a semiconductor device (10), plural diffusion layer areas (2, 3) are formed so that the impurity concentration of the diffusion layer area (2) is set to be higher than that of the diffusion layer area (3), and a first contact wire (4) connected to the diffusion layer area (2) having the higher impurity concentration is set to be larger in sectional area than a second contact wire (5) connected to the diffusion layer area (3) having the lower impurity concentration.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: In a method of fabricating an LDMOS semiconductor device, a combined layer including a gate oxide film and a first nitride film is formed on a substrate within a first region. A mask body is formed on the combined layer within a second region that is inside of the first region. Then, first impurities are introduced into the substrate outside of the second region using the mask body as a mask. Next, second impurities are introduced into the substrate outside of the first region using the mask body and the combined layer as a mask. Finally, the introduced first and second impurities are diffused by a heat treatment so as to form a source/drain region and a well region.

Abstract: A semiconductor device able to secure electrical effective thicknesses required for insulating films of electronic circuit elements by using depletion of electrodes of the electronic circuit elements even if the physical thicknesses of the insulating films are not different, where gate electrodes of high withstand voltage use transistors to which high power source voltages are supplied contain an impurity at a relatively low concentration, so the gate electrodes are easily depleted at the time of application of the gate voltage; depletion of the gate electrodes is equivalent to increasing the thickness of the gate insulating films; the electrical effective thicknesses required of the gate insulating films can be made thicker; and the gate electrodes of high performance transistors for which a high speed and large drive current are required do not contain an impurity at a high concentration where depletion of the gate electrodes will not occur, so the electrical effective thickness of the gate insulating films

Abstract: A metal oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

Abstract: A method of forming source/drain regions in semiconductor devices. First, a substrate having at least one gate structure is provided. Next, first, second, and third insulating spacers are successively formed over the sidewall of the gate structure. Subsequently, ion implantation is performed on the substrate on both sides of the gate structure using the third insulating spacer as a mask to form first doping regions. After the third insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the second insulating spacer as a mask to form second doping regions serving as source/drain regions with the first doping regions. Finally, after the second insulating spacer is removed, ion implantation is performed on the substrate on both sides of the gate structure using the first insulating spacer as a mask to form third doping regions, thereby preventing punchthrough.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A P-type pocket layer is formed in the surficial portion of a semiconductor substrate, a sidewall insulating film having a thickness of as thin as 10 nm or around is formed, and P is implanted therethrough to thereby form an N-type extension layer in the surficial portion of the p-type pocket layer. Then, a sidewall insulating film is formed, and P is implanted to thereby form an N-type source and a drain diffusion layer. P, having a larger coefficient of diffusion than that of conventionally-used As, used in the formation of the pocket layer can successfully moderate a strong electric field in the vicinity of the channel, and can consequently reduce leakage current between the drain and the semiconductor substrate and thereby reduce the off-leakage current, even if the gate length is reduced to 100 nm or shorter.

Abstract: A method of manufacturing an LDMOS transistor includes providing a semiconductor substrate of a first conductivity type having a well region of a second conductivity type formed on a surface of the substrate. Ions of the first conductivity type are implanted into a part of the well region with a predetermined energy. The substrate is subjected to a heat treatment so that the implanted ions are diffused to form a diffusion region of the first conductivity type on the surface of the substrate. Then, a gate oxide layer and a gate electrode are formed on the surface of the substrate. Finally, a drain region is formed on the surface of the substrate. The predetermined energy for the implantation is set so that an accelerated oxidation during a formation of the gate oxide layer is inhibited.

Abstract: The present disclosure provides a method and system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. The method includes defining an electrode on a substrate, forming a spacer adjacent to at least one sidewall of the electrode, and performing a processing operation on the substrate. The processing operation, which can be an ion implantation process, can use the spacer as a mask, and as a result can create a layer, such as a polymer, on the spacer. The spacer can then be removed by applying a first dry etch process to remove the layer on the spacer and a second wet etch process to remove the spacer. The first dry etch utilizes a fluorine-contained plasma, such as one that uses a CF4, CHF3, CH2F2, or CH3F etchant. A third wet etch process can be used to remove an oxide layer underlying the spacer.

Abstract: A method of manufacturing a semiconductor integrated circuit device having a switching MISFET and a capacitor element formed over a semiconductor substrate, such as a DRAM, is disclosed. The dielectric film of the capacitor element is formed to be co-extensive with the capacitor electrode layer over it. The upper electrode of the capacitor element is formed to be larger than the lower electrode.

Abstract: Between a source/drain heavily-doped diffusion layer and a region below a side face of a gate electrode in an epitaxial semiconductor substrate, an extension heavily-doped diffusion layer where N-type As ions are diffused is formed to have shallower junction than the source/drain heavily-doped diffusion layer. A pocket heavily-doped diffusion layer where P-type indium ions, that is, heavy ions having a relatively large mass number, are diffused is formed under the extension heavily-doped diffusion layer.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: A method of manufacturing a semiconductor device with a transistor comprising an LDD region and a silicide layer is disclosed. The method may include forming a gate electrode on a substrate, forming a first preliminary source/drain region with shallow junction through an ion implantation process using the gate electrode as a mask, and forming a ILD pattern with contact holes on the substrate including the gate electrode, the contact holes exposing the top of the gate electrode and some part of the first preliminary source/drain region. The method may also include forming an expanded source/drain region through an ion implantation process using the ILD pattern as a mask, forming a silicide layer on the top of the gate electrode and the expanded source/drain region, and forming contact plugs by filling the contact holes with metal.

Abstract: Methods of fabricating MOSFETs in semiconductor/r devices are disclosed. One example method may include forming an isolation layer on a semiconductor substrate and forming a capping layer thereon, forming an epitaxial active region which is not covered with the isolation layer on said semiconductor substrate by using selectively epitaxial growth, and forming a gate dielectric layer and a gate electrode on said epitaxial active region, sequentially. The example method may also include forming a source/drain plug spaced apart from the both sides of said gate electrode in said epitaxial active region, forming a source/drain into said epitaxial active region on which said source/drain plug is formed, forming an interlayer dielectric layer on the entire surface of the resultant structure after the source/drain is formed; and forming contacts in said interlayer dielectric layer, wherein said contacts are connected to said gate electrode and said source/drain plug, respectively.

Abstract: A wafer has a substrate defined with a first region and a second region. An ONO layer, a first silicon layer, and a silicon nitride layer are formed on the substrate in sequence. Then the ONO layer, the first silicon layer, and the silicon nitride layer disposed on the second region are removed. At least one gate oxide layer is formed on the second region and a second silicon layer is deposited on the wafer. After that, a photo-etching process is performed to remove the second silicon layer and the silicon nitride layer on the first region. At least a third silicon layer is formed on the wafer. Photo-etching processes and a plurality of ion implantation processes are then performed to form a gate, a drain, and a source of each MOS transistor on the substrate.

Abstract: The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials.

Abstract: A process for fabricating an integrated circuit includes forming a gate on a crystalline silicon substrate, and amorphizing a region of the substrate to obtain an amorphous silicon region. Dopant is implanted in a subregion lying substantially within the amorphous silicon region of the substrate to form drain and source extensions. A source and drain are then formed at a low temperature.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: A method for improving the etch behavior of disposable features in the fabrication of a semiconductor device is disclosed. The semiconductor device comprises a bottom anti-reflective coating layer and/or a disposable sidewall spacer which are to be removed in a subsequent etch removal process. The bottom anti-reflective coating layer and/or the disposable sidewall spacer are irradiated by heavy inert ions to alter the structure of the irradiated features and to increase concurrently the etch rate of the employed materials, for example, silicon nitride or silicon reacted nitride.